CN106057116A - Shift register unit, driving method, gate driving circuit and display device - Google Patents

Abstract

The invention discloses a shift register unit, a driving method, a grid driving circuit and a display device, belonging to the field of display technology. The shift register unit includes: a control module, an output module and a chamfering module; the control module is respectively connected to an input signal terminal, a reset signal terminal, a control signal terminal, a first clock signal terminal, a pull-up node and an output terminal, for controlling the potential of the pull-up node and the output terminal; the output module is respectively connected to the second clock signal terminal, the pull-up node and the output terminal, and is used to output the second clock signal from the second clock signal terminal to the output terminal; the The chamfering module is respectively connected with the output terminal and the third clock signal terminal, and is used to output the third clock signal to the output terminal, so as to pull down the potential of the output signal of the output terminal of the shift register unit in the second output stage, Therefore, the range of grid voltage variation is slowed down, and phenomena such as flickering and afterimages on the display screen are avoided. The invention is used to display images.

Description

Shift register unit, driving method, gate driving circuit and display device

technical field

The invention relates to the field of display technology, in particular to a shift register unit, a driving method, a gate driving circuit and a display device.

Background technique

When the display device displays an image, it is necessary to use a shift register (gate drive circuit) to scan the pixel units. The shift register includes a plurality of cascaded shift register units, and each shift register unit corresponds to a row of pixel units, and can Scanning pulse signals are output to the gates of the thin film transistors in the row of pixel units, and the pixel units of the display device are driven by a plurality of shift register units to scan and drive row by row to display images.

In the related art, there is a shift register unit, which usually controls the potential level of the output signal at the output terminal through a plurality of transistors and capacitors. However, there is usually a parasitic capacitance between the gate and the source of the thin film transistor in the display device, so when the level of the scan pulse signal applied by the shift register to the gate of the thin film transistor changes, for example, from high level to When it reaches a low level, the gate potential will drop greatly, and affected by the parasitic capacitance, the source potential will also drop greatly, resulting in a feed through phenomenon, which will cause flickering and afterimages on the display screen. The display of the device is poor.

Contents of the invention

In order to solve the problem of poor display effect of the display device in the related art, the present invention provides a shift register unit, a driving method, a gate driving circuit and a display device. Described technical scheme is as follows:

In a first aspect, a shift register unit is provided, and the shift register unit includes:

Control module, output module and chamfering module;

The control module is respectively connected to the input signal terminal, the reset signal terminal, the control signal terminal, the first clock signal terminal, the pull-up node and the output terminal, and is used for receiving the input signal from the input signal terminal and the signal from the reset signal terminal. A reset signal, under the control of the control signal from the control signal terminal and the first clock signal from the first clock signal terminal, controls the potentials of the pull-up node and the output terminal;

The output module is respectively connected to the second clock signal terminal, the pull-up node and the output terminal, and is used to output the signal from the second clock signal terminal to the output terminal under the control of the pull-up node. a second clock signal;

The chamfering module is respectively connected to the output terminal and the third clock signal terminal, and is used to output the third clock signal to the output terminal under the control of the third clock signal from the third clock signal terminal .

Optionally, the control module includes: an input submodule, a reset submodule and a noise reduction submodule;

The input sub-module is respectively connected to the input signal terminal and the pull-up node, and is used to control the potential of the pull-up node under the control of the input signal from the input signal terminal;

The reset sub-module is respectively connected to the reset signal terminal, the control signal terminal, the pull-up node, the pull-down node and the output terminal, and is used for controlling the reset signal, the control signal and the pull-down node , controlling the potentials of the pull-up node and the output terminal;

The noise reduction sub-module is respectively connected to the first clock signal terminal, the pull-up node, the control signal terminal, the pull-down node and the output terminal, and is used for the first clock signal, the control Under the control of the signal and the pull-up node, noise reduction is performed on the pull-down node and the output terminal.

Optionally, the chamfering module includes: a first transistor;

The first pole of the first transistor is connected to the third clock signal terminal, and the gate and second pole of the first transistor are connected to the output terminal.

Optionally, the output module includes: a second transistor and a capacitor;

The gate of the second transistor is connected to the pull-up node, the first stage is connected to the second clock signal terminal, and the third pole is connected to the output terminal;

One end of the capacitor is connected to the pull-up node, and the other end is connected to the output end.

Optionally, the input sub-module includes: a third transistor;

The gate of the third transistor is connected to the input signal terminal, the first pole is connected to the input signal terminal, and the second pole is connected to the pull-up node;

The reset submodule includes: a fourth transistor, a fifth transistor and a sixth transistor;

The gate of the fourth transistor is connected to the reset signal terminal, the first pole is connected to the control signal terminal, and the second pole is connected to the pull-up node;

The gate of the fifth transistor is connected to the pull-down node, the first pole is connected to the control signal terminal, and the second pole is connected to the pull-up node;

The gate of the sixth transistor is connected to the reset signal terminal, the first pole is connected to the control signal terminal, and the second pole is connected to the output terminal;

The noise reduction sub-module includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

The gate of the seventh transistor is connected to the first clock signal terminal, the first pole is connected to the input signal terminal, and the second pole is connected to the pull-up node;

The gate of the eighth transistor is connected to the first clock signal terminal, the first pole is connected to the first clock signal terminal, and the second pole is connected to the gate of the ninth transistor;

The gate of the ninth transistor is respectively connected to the second pole of the eighth transistor and the second pole of the tenth transistor, and the first pole of the ninth transistor is connected to the first clock signal terminal, The second pole of the ninth transistor is connected to the pull-down node;

The gate of the tenth transistor is connected to the pull-up node, the first pole is connected to the control signal terminal, and the second pole is connected to the gate of the ninth transistor;

The gate of the eleventh transistor is connected to the pull-up node, the first pole is connected to the control signal terminal, and the second pole is connected to the pull-down node;

The gate of the twelfth transistor is connected to the first clock signal terminal, the first pole is connected to the control signal terminal, and the second pole is connected to the output terminal;

The gate of the thirteenth transistor is connected to the pull-down node, the first pole is connected to the control signal terminal, and the second pole is connected to the output terminal.

Optionally, the transistors are all N-type transistors.

In a second aspect, a driving method of a shift register unit is provided, which is used for the shift register unit described in the first aspect, and the shift register unit includes: a control module, an output module and a chamfering module, the method include:

In the input stage, the input signal input by the input signal terminal is a first potential, and the control module controls the potential of the pull-up node to be the first potential;

In the first output stage, the second clock signal input by the second clock signal terminal is the first potential, the pull-up node maintains the first potential, and the control module outputs the second clock from the second clock signal terminal to the output terminal Signal;

In the second output stage, the third clock signal input by the third clock signal terminal is a third potential, the second clock signal maintains the first potential, and the first potential is higher than the third potential, and the control module continues Outputting the second clock signal to the output terminal, the chamfering module outputs the third clock signal to the output terminal, so that the potential of the output signal at the output terminal is higher than the third potential and lower than said first potential;

In the reset phase, the first clock signal input by the first clock signal terminal is the first potential, the reset signal input by the reset signal terminal is the first potential, and the control signal input by the control signal terminal is the second potential, and the control modules respectively send The pull-up node and the output end output the control signal.

Optionally, the control module includes: an input submodule, a reset submodule and a noise reduction submodule;

In the input phase, the input signal is a first potential, and the input submodule controls the potential of the pull-up node to be the first potential;

In the reset phase, the first clock signal is a first potential, the noise reduction sub-module controls the potential of the pull-down node to be a first potential, the reset signal is a first potential, and the control signal is a second potential. two potentials, the reset submodule outputs the control signal to the pull-up node and the output terminal respectively.

Optionally, the first potential is a higher potential than the second potential;

The third potential is higher than the second potential.

Optionally, the pulse period of the third clock signal is half of the pulse period of the second clock signal.

Optionally, the duty cycle of the second clock signal is 1/2, and the duty cycle of the third clock signal is greater than or equal to 3/4.

In a third aspect, a gate driving circuit is provided, and the gate driving circuit includes at least two cascaded shift register units as described in the first aspect.

In a fourth aspect, a display device is provided, and the display device includes the gate driving circuit as described in the third aspect.

The beneficial effects brought by the technical scheme provided by the invention are:

The present invention provides a shift register unit, a driving method, a gate drive circuit and a display device. The chamfering module in the shift register unit can output a third clock signal to the output terminal in the second output stage, because In the second output stage, the signal output by the output end is a composite signal of the second clock signal and the third clock signal, and in the second output stage, the second clock signal is at the first potential, and the third clock signal is The third potential, so that the potential of the output signal at the output terminal is located between the two potentials, thereby achieving the effect of cutting the output signal at the output terminal, and preventing the output signal from directly falling from the first potential of the first output stage to reset The second potential of the stage, thereby slowing down the magnitude of the grid voltage change, avoiding flickering and afterimages on the display screen, and improving the display effect of the display device.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention;

FIG. 4 is a flowchart of a method for driving a shift register unit provided by an embodiment of the present invention;

FIG. 5 is a timing diagram of a driving process of a shift register unit provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present invention;

FIG. 7 is a timing diagram of an output terminal of a gate driving circuit provided by an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

The transistors used in all the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present invention are mainly switching transistors according to their functions in circuits. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source is referred to as the first stage, and the drain is referred to as the second stage. According to the form in the accompanying drawings, it is stipulated that the middle terminal of the transistor is the gate, the signal input terminal is the source terminal, and the signal output terminal is the drain terminal. In addition, the switch transistors used in the embodiments of the present invention include P-type switch transistors and N-type switch transistors, wherein the P-type switch transistors are turned on when the gate is at a low level, and are turned off when the gate is at a high level, and the N-type switch transistors are turned on when the gate is at a high level. Transistors are turned on when the gate is high and off when the gate is low. In addition, the multiple signals in each embodiment of the present invention correspond to the first potential and the second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities. It does not mean that the first potential or the second potential has a specific value throughout the text. The first control signal and the second control signal may be low potential signals.

FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention. As shown in FIG. 1 , the shift register unit may include: a control module 10 , an output module 20 and a chamfering module 30 .

The control module 10 is respectively connected with the input signal terminal INPUT, the reset signal terminal RST, the control signal terminal VSS, the first clock signal terminal CLK1, the pull-up node PU and the output terminal Output, and is used for receiving the input signal from the input signal terminal INPUT. , under the control of the reset signal from the reset signal terminal RST, the control signal from the control signal terminal VSS and the first clock signal from the first clock signal terminal CLK1, control the pull-up node PU and the output terminal Output Potential;

The output module 20 is respectively connected to the second clock signal terminal CLK2, the pull-up node PU and the output terminal Output, and is used to output the output signal from the second clock signal terminal CLK2 to the output terminal Output under the control of the pull-up node PU. the second clock signal;

The chamfering module 30 is respectively connected with the output terminal Output and the third clock signal terminal CLK3, and is used to output the third clock to the output terminal Output under the control of the third clock signal from the third clock signal terminal CLK3. Signal.

To sum up, the embodiment of the present invention provides a shift register unit, the chamfering module in the shift register unit can output the third clock signal to the output terminal in the second output stage, because in the second output stage In the output stage, the signal output by the output terminal is a composite signal of the second clock signal and the third clock signal, and in the second output stage, the second clock signal is at the first potential, and the third clock signal is at the third potential, The potential of the output signal at the output terminal is located between the two potentials, thereby achieving the effect of cutting the output signal at the output terminal, and preventing the output signal from directly falling from the first potential of the first output stage to the second of the reset stage. Potential, thereby slowing down the magnitude of the grid voltage change, avoiding flickering and afterimages on the display screen, and improving the display effect of the display device.

FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention. Referring to FIG. 2 , the control module 10 may include: an input submodule 101 , a reset submodule 102 and a noise reduction submodule 103 .

The input sub-module 101 is respectively connected to the input signal terminal INPUT and the pull-up node PU, and is used for controlling the potential of the pull-up node PU under the control of the input signal from the input signal terminal INPUT.

The reset sub-module 102 is respectively connected to the reset signal terminal RST, the control signal terminal VSS, the pull-up node PU, the pull-down node PD and the output terminal Output, for controlling the reset signal, the control signal and the pull-down node PD Next, control the potentials of the pull-up node PU and the output terminal Output.

The noise reduction sub-module 103 is respectively connected with the first clock signal terminal CLK1, the pull-up node PU, the control signal terminal VSS, the pull-down node PD and the output terminal Output, and is used for the first clock signal, the control signal and under the control of the pull-up node PU, noise reduction is performed on the pull-down node PD and the output terminal Output.

FIG. 3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention. Referring to FIG. 3 , the chamfering module 30 may include: a first transistor M1;

A first pole of the first transistor M1 is connected to the third clock signal terminal CLK3 , and a gate and a second pole of the first transistor M1 are connected to the output terminal Output.

The output module 20 includes: a second transistor M2 and a capacitor;

The gate of the second transistor M2 is connected to the pull-up node PU, the first stage is connected to the second clock signal terminal CLK2, and the third pole is connected to the output terminal Output;

One end of the capacitor is connected to the pull-up node PU, and the other end is connected to the output terminal Output.

The input sub-module 101 includes: a third transistor M3;

The gate of the third transistor M3 is connected to the input signal terminal INPUT, the first pole is connected to the input signal terminal INPUT, and the second pole is connected to the pull-up node PU;

The reset sub-module 102 includes: a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6;

The gate of the fourth transistor M4 is connected to the reset signal terminal RST, the first pole is connected to the control signal terminal VSS, and the second pole is connected to the pull-up node PU;

The gate of the fifth transistor M5 is connected to the pull-down node PD, the first pole is connected to the control signal terminal VSS, and the second pole is connected to the pull-up node PU;

The gate of the sixth transistor M6 is connected to the reset signal terminal RST, the first pole is connected to the control signal terminal VSS, and the second pole is connected to the output terminal Output;

The noise reduction sub-module 103 includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13;

The gate of the seventh transistor M7 is connected to the first clock signal terminal CLK1, the first pole is connected to the input signal terminal INPUT, and the second pole is connected to the pull-up node PU;

The gate of the eighth transistor M8 is connected to the first clock signal terminal CLK1, the first pole is connected to the first clock signal terminal CLK1, and the second pole is connected to the gate of the ninth transistor M9;

The gate of the ninth transistor M9 is respectively connected to the second pole of the eighth transistor M8 and the second pole of the tenth transistor M10, and the first pole of the ninth transistor M9 is connected to the first clock signal terminal CLK1, The second pole of the ninth transistor M9 is connected to the pull-down node PD;

The gate of the tenth transistor M10 is connected to the pull-up node PU, the first pole is connected to the control signal terminal VSS, and the second pole is connected to the gate of the ninth transistor M9;

The gate of the eleventh transistor M11 is connected to the pull-up node PU, the first pole is connected to the control signal terminal VSS, and the second pole is connected to the pull-down node PD;

The gate of the twelfth transistor M12 is connected to the first clock signal terminal CLK1, the first pole is connected to the control signal terminal VSS, and the second pole is connected to the output terminal Output;

The gate of the thirteenth transistor M13 is connected to the pull-down node PD, the first pole is connected to the control signal terminal VSS, and the second pole is connected to the output terminal Output.

Referring to FIG. 3, it can be seen that in the embodiment of the present invention, each shift register unit may include 13 transistors and 1 capacitor, and the external circuit signal input includes a control signal, a reset signal, 3 clock signals, an input signal and a reset signal, The input signal of each shift register unit can be the output signal of the upper shift register unit, the reset signal of each shift register unit can be the output signal of the next shift register unit, and the control signal terminal VSS input The control signal is a DC low level signal. It should be noted that, in practical applications, the number of transistors and the number of capacitors in each shift register unit can be increased or decreased according to actual conditions, which is not limited in this embodiment of the present invention.

To sum up, the embodiment of the present invention provides a shift register unit, the chamfering module in the shift register unit can output the third clock signal to the output terminal in the second output stage, because in the second output stage In the output stage, the signal output by the output terminal is a composite signal of the second clock signal and the third clock signal, and in the second output stage, the second clock signal is at the first potential, and the third clock signal is at the third potential, The potential of the output signal at the output terminal is located between the two potentials, thereby achieving the effect of cutting the output signal at the output terminal, and preventing the output signal from directly falling from the first potential of the first output stage to the second of the reset stage. Potential, thereby slowing down the magnitude of the grid voltage change, avoiding flickering and afterimages on the display screen, and improving the display effect of the display device.

Fig. 4 is a flowchart of a method for driving a shift register unit provided by an embodiment of the present invention, the method can be used to drive a shift register unit as shown in any one of Fig. 1 to Fig. 3, referring to Fig. 1, the shift The register unit may include: a control module 10, an output module 20 and a chamfering module 30, and the method may include:

Step 401 , in the input stage, the input signal input by the input signal terminal INPUT is a first potential, and the control module 10 controls the potential of the pull-up node PU to be the first potential.

Step 402, the first output stage, the second clock signal input by the second clock signal terminal CLK2 is the first potential, the pull-up node PU maintains the first potential, and the control module 10 outputs the second clock signal to the output terminal Output The second clock signal of terminal CLK2.

Step 403, the second output stage, the third clock signal input by the third clock signal terminal CLK3 is the third potential, the second clock signal maintains the first potential, the first potential is higher than the third potential, the control module 10 Continue to output the second clock signal to the output terminal Output, and the chamfering module 30 outputs the third clock signal to the output terminal Output, so that the potential of the output signal at the output terminal Output is higher than the third potential and lower than the third potential a potential.

Step 404, reset stage, the first clock signal input by the first clock signal terminal CLK1 is the first potential, the reset signal input by the reset signal terminal RST is the first potential, and the control signal input by the control signal terminal VSS is the second potential, the The control module 10 outputs the control signal to the pull-up node PU and the output terminal Output respectively.

In summary, the embodiment of the present invention provides a driving method for a shift register unit, the driving method includes a first output stage and a second output stage, wherein in the first output stage, the output terminal of the shift register unit outputs The signal is the second clock signal at the first potential, and in the second output stage, the signal output by the output terminal is a composite signal of the second clock signal and the third clock signal, because in the second output stage, the first The second clock signal is the first potential, and the third clock signal is the third potential, so that the potential of the output signal at the output terminal is between the first potential and the third potential, thereby realizing the effect of cutting the output signal at the output terminal, Prevent the output signal from directly falling from the first potential in the first output stage to the second potential in the reset stage, thereby slowing down the magnitude of the gate voltage change, avoiding flickering and afterimages on the display screen, and improving the display effect of the display device .

Optionally, referring to FIG. 2 , the control module 10 may include: an input submodule 101 , a reset submodule 102 and a noise reduction submodule 103 .

In the above step 401, in the input stage, the input signal is at the first potential, and the input sub-module 101 controls the potential of the pull-up node PU to be the first potential.

In the above step 403, in the reset phase, the first clock signal is the first potential, the noise reduction sub-module 103 controls the potential of the pull-down node PD to be the first potential, the reset signal is the first potential, and the control signal It is a DC low-level signal, and the potential of the control signal can be a second potential, and the reset sub-module 102 outputs the control signal to the pull-up node PU and the output terminal Output respectively.

FIG. 5 is a timing diagram of a shift register unit driving process provided by an embodiment of the present invention. Referring to FIG. The high potential of the clock signal is the first potential vgh, the low potential is the second potential vgl, the high potential of the third clock signal is the first potential vgh, and the low potential is the third potential vgh′.

In the input phase T1, the input signal input from the input signal terminal INPUT is the first potential vgh, at this time the third transistor M3 in FIG. 3 is turned on, and the third transistor M3 outputs the input signal to the pull-up node PU, thereby the The potential of the pull-up node PU is pulled up to the first potential vgh.

In the first output stage T2, the second clock signal input by the second clock signal terminal CLK2 is the first potential vgh, the third clock signal input by the third clock signal terminal CLK3 is the first potential vgh, and the pull-up node PU The potential continues to increase due to the coupling effect of the capacitor C. At this time, both the first transistor M1 and the second transistor M2 are in the on state, and the first transistor M1 outputs the third clock signal to the output terminal Output, and the second transistor M2 outputs the third clock signal to the output terminal Output. The output terminal Output outputs the second clock signal. Since the potentials of the second clock signal and the third clock signal are both the first potential vgh at this time, it can be seen from FIG. 5 that the output signal of the output terminal Output is The potential is also the first potential vgh.

In the second output stage T3, the second clock signal maintains the first potential vgh, the third clock signal input to the third clock signal terminal CLK3 is the third potential vgh', and the first potential vgh is higher than the third potential vgh ', since the third potential vgh' is higher than the second potential vgl, the first transistor M1 and the second transistor M2 are still turned on, and the second transistor M2 continues to output to the output terminal Output For the second clock signal, the third transistor M3 outputs the third clock signal to the output terminal Output, so that the output signal of the output terminal Output is a composite signal of the second clock signal and the third clock signal. Referring to FIG. 5, the first In the second output stage T3, the potential vgh" of the output signal at the output terminal Output is higher than the third potential vgh' and lower than the first potential vgh, thereby achieving the purpose of cutting the output signal at the output terminal Output. The potential vgh" of the output signal at the output terminal Output of the second output stage T3 is generated by the joint action of the first potential vgh and the third potential vgh', and the specific value of the potential vgh" is determined by the first transistor M1 and the second transistor M1. The width-to-length ratio W/L of transistor M2 is determined.

In the reset phase T4, the first clock signal input by the first clock signal terminal CLK1 is the first potential vgh, the control signal input by the control signal terminal VSS is the second potential vgl, the seventh transistor M7 and the eighth transistor M8 are turned on, and the first The seven transistors M7 output the input signal to the pull-up node PU. Since the input signal is the second potential vgl at this time, the potential of the pull-up node PU can be pulled down, and at the same time, the eighth transistor M8 sends the input signal to the ninth transistor M9. The gate outputs the first clock signal, the ninth transistor M9 is turned on, and the first clock signal is output to the pull-down node PD, so that the fifth transistor M5 and the thirteenth transistor M13 are turned on, and the fifth transistor M5 and the thirteenth transistor M13 are turned on. Transistor M13 respectively outputs a control signal to the pull-up node PU and the output terminal Output, and the control signal is the second potential vgl; at the same time, in the reset phase T4, the reset signal input by the reset signal terminal RST is the first potential vgh, and the fourth transistor M4 and the sixth transistor M6 are turned on, and the fourth transistor M4 and the sixth transistor M6 respectively output the control signal at the second potential vgl to the pull-up node PU and the output terminal Output.

It can be seen from FIG. 5 that when the shift register unit transitions from the second output stage T3 to the reset stage T4, because in the second output stage T3, the potential vgh" of the output signal at the output terminal Output is lower than the first A potential vgh, so as to achieve the effect of cutting the output signal at the output terminal, so that the potential change of the output signal can change from the first potential vgh of the first output stage T1 to the vgh” of the second output stage T3, and then from The vgh" changes to the second potential vgl in the reset phase T4, so the output signal can be prevented from directly falling from the first potential vgh in the first output phase T2 to the second potential vgl in the reset phase T4, slowing down the change of the gate voltage Amplitude, to avoid flickering and image afterimages on the display screen, and to improve the display effect of the display device.

It should be noted that, referring to FIG. 5, it can be seen that the pulse period of the first clock signal and the second clock signal are the same, and the duty cycle is the same, for example, both can be 1/2, and the pulse period of the third clock signal is the same as that of the second clock signal. half of the pulse period of the signal, so as to ensure that when the second clock signal transitions from low level to high level, the third clock signal also transitions from low level to high level. Further, it can be seen from FIG. 5 that the duration of the second output phase T3 (that is, the chamfering time) is equal to the duration of the third clock signal at the third potential within one pulse period, so the third clock The duty cycle of the signal can be determined according to the clipping time required by the shift register unit, since the clipping time is generally less than a quarter of the time that the second clock signal is at a high level in each pulse period, That is: the duration of T3≤(1/4)×(T2 duration+T3 duration), so when the duty cycle of the second clock signal is 1/2, the duty cycle of the third clock signal The duty ratio may be greater than or equal to three-quarters, and when the duty ratio of the second clock signal is less than one-half, the duty ratio of the third clock signal may be greater than three-quarters, so that the third clock signal is The duration of the third potential in each pulse period is less than or equal to a quarter of the duration of the first potential in each pulse period of the second clock signal. If the shift register unit is pre-charged, the duty cycle of the third clock signal can be set smaller than the case without pre-charge, that is, the duty cycle of the third clock signal can be set according to the shift The pre-charging condition of the register unit and the chamfering time are jointly determined.

It should also be noted that, in each of the above embodiments, the descriptions are made by taking the transistors as N-type transistors, the first potential and the third potential being high potentials, and the second potential being low potentials. Of course, the transistors can also use P-type transistors. When all transistors use P-type transistors, the first potential and the third potential can be low potentials, the second potential can be high potentials, and each signal terminal input The potential change of the signal can be opposite to the potential change shown in FIG. 5 (that is, the phase difference between the two is 180 degrees).

In summary, the embodiment of the present invention provides a driving method for a shift register unit, the driving method includes a first output stage and a second output stage, wherein in the first output stage, the output terminal of the shift register unit outputs The signal is the second clock signal at the first potential, and in the second output stage, the signal output by the output terminal is a composite signal of the second clock signal and the third clock signal, because in the second output stage, the first The second clock signal is the first potential, and the third clock signal is the third potential, so that the potential of the output signal at the output terminal is between the first potential and the third potential, thereby realizing the effect of cutting the output signal at the output terminal, Prevent the output signal from directly falling from the first potential in the first output stage to the second potential in the reset stage, thereby slowing down the magnitude of the gate voltage change, avoiding flickering and afterimages on the display screen, and improving the display effect of the display device .

FIG. 6 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present invention. The gate drive circuit may include at least two cascaded shift register units 00 as shown in any one of FIGS. 1 to 3 . 6. It can be seen that the reset signal terminal RST of the Nth-stage shift register unit GOA N is connected to the output terminal of the N+1-stage shift register unit GOA N+1, and the input of the N-stage shift register unit GOA N The signal terminal INPUT is connected to the output terminal of the N-1st stage shift register unit GOA N-1, wherein the input signal terminal INPUT of the first stage shift register unit is connected to the frame start signal terminal STV. The timing diagram of each output terminal in the gate drive circuit can be shown in Figure 7. In order to ensure that each output terminal in the gate drive circuit shifts and outputs the drive signal, the output modules and control modules in the adjacent two-stage shift register units The connected clock signal terminals are different. For example, if the clock signal terminal connected to the output module in the Nth stage shift register unit GOA N is the second clock signal terminal CLK2, the clock signal terminal connected to the control module is the first clock signal terminal. The signal terminal CLK1, the clock signal terminal connected to the output module in the N+1 shift register unit GOA N+1 is the first clock signal terminal CLK1, and the clock signal terminal connected to the control module is the second clock signal terminal CLK2 .

An embodiment of the present invention provides a display device, which may include a gate driving circuit as shown in FIG. 6 . The display device can be any product or component with a display function such as a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, or a navigator.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (13)

1. A kind of shift register unit, is characterized in that, described shift register unit comprises: Control module, output module and chamfering module; The control module is respectively connected to the input signal terminal, the reset signal terminal, the control signal terminal, the first clock signal terminal, the pull-up node and the output terminal, and is used for receiving the input signal from the input signal terminal and the signal from the reset signal terminal. A reset signal, under the control of the control signal from the control signal terminal and the first clock signal from the first clock signal terminal, controls the potentials of the pull-up node and the output terminal; The output module is respectively connected to the second clock signal terminal, the pull-up node and the output terminal, and is used to output the signal from the second clock signal terminal to the output terminal under the control of the pull-up node. a second clock signal; The chamfering module is respectively connected to the output terminal and the third clock signal terminal, and is used to output the third clock signal to the output terminal under the control of the third clock signal from the third clock signal terminal . 2. The shift register unit according to claim 1, wherein the control module comprises: an input submodule, a reset submodule and a noise reduction submodule; The input sub-module is respectively connected to the input signal terminal and the pull-up node, and is used to control the potential of the pull-up node under the control of the input signal; The reset sub-module is respectively connected to the reset signal end, the control signal end, the pull-up node, the pull-down node, and the output end, and is used to connect the reset signal, the control signal, and the pull-down Under the control of the node, control the potential of the pull-up node and the output terminal; The noise reduction sub-module is respectively connected to the first clock signal terminal, the pull-up node, the control signal terminal, the pull-down node and the output terminal, for Under the control of the control signal and the pull-up node, noise reduction is performed on the pull-down node and the output terminal. 3. The shift register unit according to claim 1, wherein the chamfering module comprises: a first transistor; The first pole of the first transistor is connected to the third clock signal terminal, and the gate and second pole of the first transistor are connected to the output terminal. 4. The shift register unit according to claim 1, wherein the output module comprises: a second transistor and a capacitor; The gate of the second transistor is connected to the pull-up node, the first stage is connected to the second clock signal terminal, and the third pole is connected to the output terminal; One end of the capacitor is connected to the pull-up node, and the other end is connected to the output end. 5. The shift register unit according to claim 2, characterized in that, The input sub-module includes: a third transistor; The gate of the third transistor is connected to the input signal terminal, the first pole is connected to the input signal terminal, and the second pole is connected to the pull-up node; The reset submodule includes: a fourth transistor, a fifth transistor and a sixth transistor; The gate of the fourth transistor is connected to the reset signal terminal, the first pole is connected to the control signal terminal, and the second pole is connected to the pull-up node; The gate of the fifth transistor is connected to the pull-down node, the first pole is connected to the control signal terminal, and the second pole is connected to the pull-up node; The gate of the sixth transistor is connected to the reset signal terminal, the first pole is connected to the control signal terminal, and the second pole is connected to the output terminal; The noise reduction sub-module includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The gate of the seventh transistor is connected to the first clock signal terminal, the first pole is connected to the input signal terminal, and the second pole is connected to the pull-up node; The gate of the eighth transistor is connected to the first clock signal terminal, the first pole is connected to the first clock signal terminal, and the second pole is connected to the gate of the ninth transistor; The gate of the ninth transistor is respectively connected to the second pole of the eighth transistor and the second pole of the tenth transistor, and the first pole of the ninth transistor is connected to the first clock signal terminal, The second pole of the ninth transistor is connected to the pull-down node; The gate of the tenth transistor is connected to the pull-up node, the first pole is connected to the control signal terminal, and the second pole is connected to the gate of the ninth transistor; The gate of the eleventh transistor is connected to the pull-up node, the first pole is connected to the control signal terminal, and the second pole is connected to the pull-down node; The gate of the twelfth transistor is connected to the first clock signal terminal, the first pole is connected to the control signal terminal, and the second pole is connected to the output terminal; The gate of the thirteenth transistor is connected to the pull-down node, the first pole is connected to the control signal terminal, and the second pole is connected to the output terminal. 6. The shift register unit according to any one of claims 3 to 5, characterized in that, The transistors are all N-type transistors. 7. A driving method of a shift register unit, used to drive the shift register unit described in any one of claims 1 to 6, wherein the shift register unit comprises: a control module, an output module and a chamfer module, the method comprising: In the input stage, the input signal input by the input signal terminal is a first potential, and the control module controls the potential of the pull-up node to be the first potential; In the first output stage, the second clock signal input from the second clock signal terminal is the first potential, the pull-up node maintains the first potential, and the control module outputs the second clock from the second clock signal terminal to the output terminal Signal; In the second output stage, the third clock signal input by the third clock signal terminal is the third potential, the second clock signal maintains the first potential, and the first potential is higher than the third potential, and the control module continues Outputting the second clock signal to the output terminal, the chamfering module outputs the third clock signal to the output terminal, so that the potential of the output signal at the output terminal is higher than the third potential and lower than said first potential; In the reset phase, the first clock signal input by the first clock signal terminal is the first potential, the reset signal input by the reset signal terminal is the first potential, and the control signal input by the control signal terminal is the second potential, and the control modules respectively send The pull-up node and the output end output the control signal. 8. The method according to claim 7, wherein the control module comprises: an input submodule, a reset submodule and a noise reduction submodule; In the input phase, the input signal is a first potential, and the input submodule controls the potential of the pull-up node to be the first potential; In the reset phase, the first clock signal is a first potential, the noise reduction sub-module controls the potential of the pull-down node to be a first potential, the reset signal is a first potential, and the control signal is a second potential. two potentials, the reset submodule outputs the control signal to the pull-up node and the output terminal respectively. 9. The method according to claim 7 or 8, characterized in that, the first potential is a high potential relative to the second potential; The third potential is higher than the second potential. 10. The method according to claim 7 or 8, characterized in that, The pulse period of the third clock signal is half of the pulse period of the second clock signal. 11. The method of claim 10, wherein, The duty cycle of the second clock signal is 1/2, and the duty cycle of the third clock signal is greater than or equal to 3/4. 12. A gate drive circuit, characterized in that the gate drive circuit comprises at least two cascaded shift register units according to any one of claims 1 to 6. 13. A display device, characterized in that the display device comprises the gate driving circuit according to claim 12.