CN1058815C - Surge Voltage Suppression Circuit - Google Patents

Abstract

A surge suppressing method features that a three-layer symmetrical surge suppressor with TCSS as main component is designed in such manner that it can fully absorb surge energy and is used to load it to power supply. The symmetrical surge suppressor comprises semiconductor element metal oxide varistor, semiconductor polymerization switch and hollow inductor, etc. to form three-layer suppressing circuit with different surge suppressing effect to suppress various interference surge in electric equipment and to protect the electric equipment tightly and safely.

Description

Surge Voltage Suppression Circuit

The present invention relates to a surge suppression circuit capable of completely absorbing surge energy, in particular to a three-layer symmetrical suppression circuit with Transients Voltage Surge Suppressors-TVSS as the main component The circuit is used in a power supply system, and the suppression circuit with fast surge suppression function and high-efficiency surge energy absorption with automatic recovery belongs to the technical category of suppressing surge interference.

The surge voltage in the power supply system is extremely destructive to electrical equipment. Generally, overload protection or automatic power-off devices (such as fuses) are installed at the power supply end. Although partial control effects can be achieved by cutting off the power supply, such devices After disconnection, it needs to be manually restored or replaced with a new product, and it cannot be automatically restored, so most of them are only suitable for household power supply systems below 220V, but for sudden high voltage and high current on the power supply system, such as lightning interference waves caused by lightning The surge voltage, or the switch interference surge voltage caused by the switch on and off of the load equipment, input, etc., cannot be effectively suppressed, and cause damage to the power supply circuit, digital circuit, analog circuit, etc. of electrical equipment.

Most industries use surge protection devices (Surge Protection Device_SPD) as circuit protection; for example:

1. Use metal oxide varistor (Metal Oxide Varistor, MOV) to clamp the surge voltage below a certain range, but the residual surge voltage and discharge current after MOV operation are allowed to enter the electrical equipment Medium; this method cannot effectively protect precision electronic equipment with low operating voltage and fast action speed, and most of the IC components in electronic equipment are still damaged due to this. As shown in Figure 1, under the protection of MOV, the IC circuit board still burned by the residual surge is enlarged through the electron microscope. It can be seen that MOV is still incomplete for surge suppression.

2. Use the lightning arrester to guide the surge to other places. This way of sacrificing others to protect yourself cannot solve the problem, and the fault caused by the lightning arrester under certain load changes continues (Holdover) The phenomenon cannot be effectively avoided, so it is prone to failure and loss of protection effect.

Therefore, it can be seen that the traditional surge suppression circuit suppresses the surge voltage and current direction, and it is always difficult to be perfect and practical.

In order to solve this problem, the present invention goes against the tradition and focuses on completely absorbing the energy of the surge, and provides a surge suppression circuit, in particular, a surge suppressor designed with a symmetrical structure. It has a high-efficiency suppression circuit with automatic recovery, fast surge suppression, and complete absorption of surge energy, which can effectively solve various surge interference problems in low-voltage power supply systems, and has industrial applicability.

The main purpose of the present invention is a surge suppressor using TVSS in a three-layer mix. According to the present invention, both the receptive interference surge and the vulnerable interference surge have obvious absorption and suppression effects, and the surge The energy absorption rate can reach more than 99.5%, and it is an unprecedented surge suppression circuit.

Another object of the present invention is to provide a commercialized socket that can be used alone on an AC power socket or a DC power supply circuit, and can also be connected in parallel with the power supply circuit, digital circuit, analog circuit input terminal, output terminal, etc. of electrical equipment. Surge suppressors are used to suppress various interference surges in electrical equipment, so that electrical equipment is strictly and safely protected.

The surge suppression circuit of the present invention is used to suppress the surge circuit by means of the surge voltage suppressor installed in the power supply circuit, digital circuit, analog circuit, and control circuit of the electrical equipment, wherein the suppressor is used to absorb the surge The way of voltage energy, with the transient surge voltage suppression element as the main component, constitutes a three-layer symmetrical surge voltage suppressor. Among them, the three-layer symmetrical surge suppressor consists of a semiconductor polymerization switch and a circuit connected in series as the first layer, a metal oxide varistor connected in series as a lightning arrester as the second layer, and a T composed of an inductor and a metal oxide varistor. The type suppression circuit is the third layer, which constitutes a three-layer symmetrical type suppression circuit.

The surge suppression circuit of the present invention uses the aforementioned TVSS to form a three-layer symmetrical surge suppressor, which can clearly and effectively absorb surge energy and suppress surge voltage. And the structure of the embodiment of the present invention, in actual manufacture and application, the three-layer symmetrical surge suppression circuit can be made into a single body, or connected to electrical equipment, so it can be used alone and plugged into an AC power socket, or On the DC power supply circuit, it can also be used in parallel with the input and output terminals of the power supply circuit, digital circuit, and analog circuit of electrical equipment, or the circuits of each layer of the three-layer symmetrical surge suppression circuit can be separated as needed. Individually applied to the circuits of the above-mentioned electrical equipment, all kinds of interference surges can be suppressed by absorbing the surge energy, so that the electrical equipment is strictly and completely protected.

Figure 1 is an enlarged view of an IC circuit damaged by a residual surge under an electron microscope. The scorched black mark in the lower right part is caused by the surge.

Fig. 2 is a circuit diagram of an embodiment of the present invention.

Figure 3 is the voltage waveform at both ends of the aggregation switch when the 0.5μS-100KHz 6KV ringing surge wave is used for surge. The upper figure is the surge current, and the lower figure is the voltage, showing that the voltage value changes with the current.

Figure 4 shows the voltage waveforms at both ends of the aggregation switch when the combined wave is 1.2/50μS, 6KV, 8/20μS, and 3KA. rise and increase.

Figure 5 is a test diagram of the disconnection time of the aggregation switch. The test result shows that the disconnection time of the aggregation switch is 31.7mS.

Figure 6 is a general fuse breaking time test chart, the test results show that the fuse breaking time is 214.5mS.

Figure 7 is a test chart of the arc voltage generated when a general fuse is blown by a surge current. Under 1.2/50μS, 6KV, 8/20μS, 3KA combined wave surge, the arc voltage generated by a general fuse blown is as high as 14KV or more .

Figure 8 shows the continued phenomenon of lightning arrester failure and the formation of freewheeling.

Figure 9 shows that the lightning arrester failure continues to cause periodic power interruptions.

Figure 10 shows the elimination of the continuous phenomenon of lightning arrester failure. The lightning arrester series MOV has no fault persistence and freewheeling phenomenon under 1.2/50μS, 6KV, 8/20μS, 3KA combined wave surge, and returns to normal after 3.26mS. The upper figure shows the voltage waveform at both ends, and the lower figure shows the current waveform.

Figure 11 shows that the lightning arrester series MOV has no fault persistence and freewheeling phenomenon under the 0.5μS_100KHz 6KV ringing wave surge, and returns to normal after 100μS. The upper figure shows the voltage waveform at both ends, and the lower figure shows the current waveform.

Figure 12 shows the voltage waveform at both ends of the discharge current flowing through the air-core inductor under 1.2/50μS, 6KV, 8/20μS, 3KA combined wave surge. The upper figure is the discharge current waveform, and the lower figure is the voltage waveform.

Figure 13 shows the discharge current flowing through the air-core inductor and the voltage waveform at both ends under the impact of 0.5μS_100KHz 6KV ringing wave surge. The upper figure is the discharge current waveform, and the lower figure is the voltage waveform.

Figure 14 shows the discharge current waveform and the energy absorbed by the clamping voltage waveform at both ends of the MOV under the surge, which shows that the MOV absorbs 44 under the combined surge of 1.2/50μS, 6KV, 8/20μS, and 3KA joule energy.

Figure 15 shows that the MOV absorbs 62m Joule energy under 0.5μS_100KHz 6KV ringing wave surge.

Figure 16 shows 1.2/50μS, 6KV, 8/20μS, 3KA over 100 joules combined wave surge after passing through the symmetrical surge suppressor and entering the residual surge voltage, current, and energy waveforms of the six-and-a-half-digit high-precision digital ammeter monitor.

CH(1): Surge suppressor clamping voltage

CH(2): Surge suppressor discharge current

CH(3): Residual voltage entering electrical equipment

CH(4): Residual surge discharge current entering electrical equipment

Fig. 17 is the expansion of the horizontal axis of Fig. 16 at different magnifications.

Fig. 18 is the expansion of the horizontal axis of Fig. 16 at different magnifications.

Fig. 19 is the expansion of the horizontal axis of Fig. 16 at different magnifications.

Figure 20 is the residual surge energy waveform obtained after mathematical operation of the waveform in Figure 19:

CH(1): The residual surge energy waveform flowing into the 6.5-digit high-precision digital ammeter is 34.17mJ

CH(2): product of absolute value |V| and |I|

CH(3): The absolute value waveform of the residual surge voltage at the power supply terminal of a six-and-a-half-digit high-precision digital ammeter

CH(4): The absolute value waveform of the residual surge current flowing into the 6.5-digit high-precision digital ammeter

Figure 21 shows the clamping voltage and total discharge current of the second layer and third layer suppression circuit under the common mode coupling surge of the combined wave surge above 6KV/3KA in the embodiment of the present invention, and the four groups of waveforms in the figure are from top to bottom , respectively:

CH(1): The discharge current of one side of the third layer suppression circuit -684A

CH(2): Clamping voltage on one side of the third layer suppression circuit -432V

CH(3): Total surge discharge current -3.64KA

CH(4): Clamping voltage on one side of the second layer suppression circuit -862V

Figure 22 shows the energy absorbed by the second layer of suppression circuit under the common mode coupling surge of the combined wave surge of 6KV/3KA according to the embodiment of the present invention,

The four groups of waveforms in the figure are from top to bottom, namely:

CH(1): The product of the clamp circuit of the second layer suppression circuit and the discharge current (VXI)

CH(2): The energy absorbed by one side of the second suppression circuit - 30 joules (VS)

CH(3): Total surge discharge current -3.6KA

CH(4): Clamping voltage on one side of the second layer suppression circuit -862V

Figure 23 shows the clamping voltage of the output terminal under the common mode coupling surge of the 6KV/3KA combined wave surge in the embodiment of the present invention. The four groups of waveforms in the figure are from top to bottom, respectively:

CH(1): Discharge current on one side of the third layer suppression circuit -688A

CH(2): Clamping voltage -48V in common mode mode at the output of the suppression circuit (high common mode rejection ratio)

CH(3): Total surge discharge current -3.66KA

CH(4): Clamping voltage on one side of the second layer suppression circuit -934

Figure 24 is 1.2/50μS, 6KV, 8/20μS, 3KA positive polarity combined wave surge common mode coupling, superimposed on AC110V 90 degree phase (online).

FIG. 25 is an expanded view of different magnifications on the horizontal axis of FIG. 24 .

FIG. 26 is an expanded view of different magnifications on the horizontal axis of FIG. 24 .

FIG. 27 is an expanded view of different magnifications on the horizontal axis of FIG. 24 .

FIG. 28 is an expanded view of different magnifications on the horizontal axis of FIG. 24 .

Figure 29 is 1.2/50μS, 6KV, 8/20μS, 3KA negative polarity combined wave surge common mode coupling, superimposed on AC110V 130 degree phase (online).

FIG. 30 is an expanded view of different magnifications on the horizontal axis of FIG. 29 .

Fig. 31 is an expanded view of different magnifications on the 29th horizontal axis.

Figure 32 shows the clamping voltage and the maximum and minimum values of the total discharge current of the second-layer suppression circuit under the 6KV/3KA combined surge normal-mode coupled surge. The waveforms of the four groups in the figure are from bottom to bottom, respectively:

CH(1): VI product of the second layer of suppression circuit

CH(2): Absorbed energy of the second layer suppression circuit - 44 Joules (VS)

CH(3): Total surge discharge current -2.24KA

CH(4): The clamping voltage of the second layer suppression circuit -1.4KV

Figure 33 shows the clamping voltage, discharge current, VI product and absorbed energy of the second-layer suppression circuit under the 6KV/3KA combined surge normal-mode coupled surge. The four groups of waveforms in the figure are from top to bottom, respectively:

CH(1): VI product of the second layer of suppression circuit

CH(2): Absorbed energy of the second layer suppression circuit - 44 Joules (VS)

CH(3): Total surge discharge current -2.24KA

CH(4): The clamping voltage of the second layer suppression circuit -1.4KV

Figure 34 shows the maximum and minimum values of the clamping voltage and discharge current of the third-layer suppression circuit under the 6KV/3KA combined surge and normal-mode coupled surge. The four groups of waveforms in the figure are from top to bottom, respectively:

CH(1): VI product of the third-layer suppression circuit

CH(2): The absorbed energy of the third layer suppression circuit -8.5 joules (VS)

CH(3): The discharge current of the third layer suppression circuit -663A

CH(4): Clamping voltage of the third layer suppression circuit -600V

Figure 35 shows the clamping voltage, discharge current, VI product and absorbed energy of the third-layer suppression circuit under the 6KV/3KA combined surge normal-mode coupled surge. The four waveforms in the figure are from top to bottom, respectively:

CH(1): VI product of the third-layer suppression circuit

CH(2): The absorbed energy of the third layer suppression circuit -8.5 joules (VS)

CH(3): The discharge current of the third layer suppression circuit -663A

CH(4): Clamping voltage of the third layer suppression circuit -600V

Figure 36 is 1.2/50μS, 6KV, 8/20μS, 3KA positive polarity combined wave surge normal mode coupling, superimposed on AC110V 270 degree phase (online).

FIG. 37 is an expanded view of different magnifications on the horizontal axis of FIG. 36 .

FIG. 38 is an expanded view of different magnifications on the horizontal axis of FIG. 36 .

FIG. 39 is an expanded view of different magnifications on the horizontal axis of FIG. 36 .

FIG. 40 is an expanded view of different magnifications on the horizontal axis of FIG. 36 .

Figure 41 is based on 1.2/50μS, 6KV, 8/20μS, 3KA positive level combined surge normal mode coupling, superimposed on DC_48V (online).

FIG. 42 is an expanded view of different magnifications on the horizontal axis of FIG. 41 .

FIG. 43 is an expanded view of different magnifications on the horizontal axis of FIG. 41 .

Figure 44 is an expanded view of different magnifications on the horizontal axis of Figure 41,

Figure 45 shows the clamping voltage, total discharge current, VI product and absorbed energy of the second-layer suppression circuit under the 0.5μS_100KHz 6KV ringing surge common mode coupling surge. The four groups of waveforms in the figure are from top to bottom, respectively for:

CH(1): Inrush total discharge current

CH(2): Clamping voltage of the second layer suppression circuit

CH(3): VI product of the second layer of suppression circuit

CH(4): Energy absorbed by the second layer suppression circuit

Figure 46 is the clamping voltage, discharge current, VI product and absorbed energy of the third-layer suppression circuit under the common mode coupling surge of 0.5μS_100KHz 6KV ringing surge. The four groups of waveforms in the figure are from bottom to bottom, respectively:

CH(1): The discharge current of the third layer suppression circuit

CH(2): Clamping voltage of the third layer suppression circuit

CH(3): VI product of the third-layer suppression circuit

CH(4): The third layer suppresses the energy absorbed by the circuit

Figure 47 is superimposed on AC110V 270-degree phase (online) with 0.5μS_100KHz 6KV ringing surge common-mode coupling. The upper figure is the discharge current waveform, and the lower figure is the clamping voltage waveform.

FIG. 48 is an expanded view of different magnifications on the horizontal axis of FIG. 41 .

FIG. 49 is an expanded view of different magnifications on the horizontal axis of FIG. 41 .

FIG. 50 is an expanded view of different magnifications on the horizontal axis of FIG. 41 .

Figure 51 is the clamping voltage, total discharge current, VI product and absorbed energy of the second-layer suppression circuit under the normal mode coupling surge of 0.5μS_100KHz 6KV ringing surge. The four groups of waveforms in the figure are from top to bottom, respectively:

CH(1): Inrush total discharge current

CH(2): Clamping voltage of the second layer suppression circuit

CH(3): VI product of the second layer of suppression circuit

CH(4): Energy absorbed by the second layer suppression circuit

Figure 52 is the clamping voltage, discharge current, VI product and absorbed energy of the third-layer suppression circuit under the normal-mode coupling surge of 0.5μS_100KHz 6KV ringing surge. The four groups of waveforms in the figure are from top to bottom, respectively:

CH(1): The discharge current of the third layer suppression circuit

CH(2): Clamping voltage of the third layer suppression circuit

CH(3): VI product of the third-layer suppression circuit

CH(4): The third layer suppresses the energy absorbed by the circuit

Figure 53 is a 0.5μS_100KHz 6KV ringing surge normal-mode coupling superimposed on AC110V 270-degree phase (online). The upper figure is the discharge current waveform, and the lower figure is the clamping voltage waveform.

FIG. 54 is an expanded view of different magnifications on the horizontal axis of FIG. 53 .

FIG. 55 is an expanded view of different magnifications on the horizontal axis of FIG. 53 .

FIG. 56 is an expanded view of different magnifications on the horizontal axis of FIG. 53 .

Figure 57 is superimposed on DC_48V (online) with 0.5μS_100KHz 6KV ringing surge normal mode coupling. The upper figure is the discharge current waveform, and the lower figure is the clamping voltage waveform.

FIG. 58 is an expanded view of different magnifications on the horizontal axis of FIG. 57 .

FIG. 59 is an expanded view of different magnifications on the horizontal axis of FIG. 57 .

FIG. 60 is an expanded view of different magnifications on the horizontal axis of FIG. 57 .

Fig. 61 shows the surge capacity parameters of the surge generating equipment manufactured by KEYTEK.

Figure 62 is the test of the common-mode coupling suppression capability of the vulnerable interference surge under the offline condition (the expressed value of the absorbed energy is the unilateral energy of a symmetrical circuit).

Figure 63 is a 1.2/50μS, 6KV, 8/20μS, 3KA positive and negative polarity combined surge, alternately stacked on AC110V 0 degree to 315 degree phase, and tested by common mode coupling.

Figure 64 is the test of the normal-mode coupling suppression capability of the vulnerable disturbance surge under the offline condition.

Figure 65 is a 1.2/50μS, 6KV, 8/20μS, 3KA positive and negative polarity combined surge, alternately stacked on the phase of AC110V 0° to 315°, and tested by normal mode coupling.

Figure 66 is a 1.2/50μS, 6KV, 8/20μS, 3KA positive and negative polarity combined surge, alternately stacked on DC_48V, and tested by normal mode coupling.

Figure 67 is the test of the common-mode coupling suppression capability of the inductive interference surge under the offline condition (absorbed energy value is unilateral energy of a symmetrical circuit).

Figure 68 is a 0.5μS_100KHz 6KV/500A ring wave positive and negative, polarity alternately superimposed on the AC110V 0 degree to 315 degree phase, and the test is carried out by common mode coupling.

Figure 69 is an offline test of the normal-mode coupling suppression capability of perceptual interference surges (absorbed energy value is unilateral energy of a symmetrical circuit).

Figure 70 is a 0.5μS_100KHz 6KV/500A ringing surge positive and negative, polarity alternately superimposed on the phase of AC110V 0 degrees to 315 degrees, and tested by normal mode coupling.

Figure 71 is a 0.5μS_100KHz 6KV/500A ringing surge, with positive and negative polarities alternately superimposed on DC_48V, and tested by normal mode coupling.

The specific examples of the present invention will be described in detail below in conjunction with the accompanying diagrams and experimental data charts.

The present invention is a three-layer symmetrical suppressor 10 with TVSS as the main component. It is applied to the power supply system with the focus on "absorbing surge energy", and has the function of fast surge suppression, automatic recovery, and High-efficiency surge suppression circuit that completely absorbs surge energy.

The aforementioned symmetrical surge suppressor 10, its best embodiment is shown in Figure 2, for example, comprises the first layer connected in series with the circuit by a semiconductor polymerization switch (poly switch) 11, and the lightning arrester 13 connected in series by a metal oxide varistor 12 as the second layer. The second layer, the T-shaped suppression circuit composed of the inductor 14 and the metal oxide varistor 12 is the third layer, forming a three-layer symmetrical surge suppression circuit.

When the duration of the sudden surge is more than tens of mS, the surge energy and current will rise sharply, and the aggregation switch 11 will be disconnected (high impedance state). The disconnection speed is determined by I2. When the current is larger, it will be disconnected. The faster the speed. Under the same environment, the opening time of the aggregation switch 11 is only one-sixth of the fusing time of the general fuse, and when the general fuse is blown by a surge current, an arc voltage will be generated, but the aggregation switch 11 does not have this shortcoming (see below for details) The original test analysis is attached). In addition, because the polymerization switch 11 can be reset and does not need to be replaced, it cannot be achieved by a fuse. Therefore, it is designed as the first layer of surge suppression in the circuit of the present invention to fully utilize its characteristics.

The second layer of surge suppression in the circuit is based on the avoidance of "V_I characteristic curve discontinuity effect" and the consideration of surge energy absorption. The metal oxide varistor 12 associated with the lightning arrester 13 will cause a discontinuous effect on the V_I characteristic curve, which can be avoided by connecting the metal oxide varistor 12 in series. When the typical lightning surge (1.2/50μS) enters the symmetrical surge suppression circuit, because the time of 50μS is not enough to disconnect the aggregation switch 11, the metal oxide varistor 12 needs to be connected in series with the second layer of surge arrester 13. The surge absorption circuit functions to suppress the surge voltage below the clamping voltage and absorb a large amount of energy contained in the surge.

The residual surge suppressed by the second-layer surge absorbing circuit is then passed through the T-shaped third-layer suppressing circuit composed of the inductor 14 and the metal oxide varistor 12 to suppress the surge current with the inductor 14 and the metal oxide varistor 12 The secondary clamping and energy absorption make the surge residual energy absorbed to such a small degree that it is no longer harmful to the electrical equipment 15 .

The above-mentioned symmetrical suppression circuit 10 of the present invention can obtain a very high common-mode rejection ratio, and when the surge enters in the common-mode mode (Common Mode), it will be offset at the output end, so that the electrical equipment is completely and completely protected . For floating grounded electrical equipment, when the surge enters the normal mode (Normal Mode), the symmetrical surge suppression circuit 10 of the present invention uses the internal TVSS in a series configuration, through two layers of surge energy absorption, voltage suppression, Together with current limiting, the surge is non-destructive to the electrical equipment 15.

The test analysis of each component of the present invention under the surge environment:

The behavior mode test and analysis of components such as semiconductor polymer switch 11, metal oxide varistor 12, lightning arrester 13, and inductor 14 in a surge environment are as follows:

1. Semiconductor aggregation switch:

The aggregation switch 11 is a positive temperature coefficient element, and its internal resistance is proportional to the amount of current flowing through it. When the current is larger, its internal resistance becomes larger, so that the voltage at both ends rises and finally enters a high impedance state; this behavior also causes the current to drop rapidly. To achieve the effect of suppressing the surge current. As shown in Figures 3 and 4 below, the voltage test at both ends of the aggregation switch, in which Figure 3 is the voltage waveform at both ends of the aggregation switch when a 0.5μS_100KHz 6KV Ring wave surge is used to surge, showing that the voltage value varies with The magnitude of the current varies. Figure 4 is the voltage waveform at both ends of the aggregation switch when the 1.2/50μS 6KV, 8/20μS 3KA combination wave (Bi-wave) negative polarity surge surges, showing that the voltage value increases with the current rise. The turn-off speed of the aggregation switch is determined by I2. The test result shows that the turn-off time of the aggregation switch is 31.7mS (as shown in Figure 5), which is significantly faster than the fuse blowing time of 214.5mS (as shown in Figure 6). And because when a general fuse is blown by a surge current, the arc voltage generated is much higher than the surge voltage on the circuit, as shown in Figure 7; under 1.2μS 6KV, 8/20μS 3KV combined surge , Generally, the arc voltage generated when the fuse is blown is as high as below 14KV, but the aggregation switch 11 does not have this phenomenon.

2. Lightning arrester:

Lightning arrester 13 is a guiding element, which does not absorb energy itself, and its breakdown action voltage is a function of the surge voltage rise rate; in the non-conducting state, the impedance at both ends is as high as 10MΩ, and once it breaks down, it will quickly guide , Eliminate inrush current. The biggest shortcoming of the lightning arrester is the continuous flow caused by the fault continuation (Hold over), as shown in Figures 8 and 9. Figure 8 shows the continued phenomenon of lightning arrester faults to form freewheeling, and Figure 9 shows the continuous phenomenon of lightning arrester failures to form periodic power supply interruptions. The existence of the above-mentioned freewheeling will cause the lightning arrester to burn. In the circuit 10 of the present invention, the second layer metal oxide varistor (MOV) 12 is connected in series with the arrester 13, and the test results show that there is no freewheeling situation (as shown in Figure 10), and the MOV in series with the arrester is 1.2/50μS 6KV, Under 8/20μS3KA combined wave surge, there is no fault persistence and freewheeling, and it returns to normal after 3.26mS; Figure 11 shows that the lightning arrester series MOV has no fault persistence and continuous flow under 0.5μS_100KHz 6KV ringing wave surge. If freewheeling exists, it will return to normal after 100μS.

3. Air core inductor:

The surge impedance (Z=LS/CS) is inversely proportional to the surge current. The higher the surge impedance value, the lower the surge current value. Therefore, the inductance 14 can suppress the surge current and reduce the metal oxide varistor (MOV) 12 clamping voltage, to achieve the effect of complete absorption. The voltage waveforms at both ends of the inductor under surge are shown in Figures 12 and 13. Figure 12 shows the discharge current and the voltage waveform at both ends of the air-core inductor under 1.2/50μS 6K V, 8/20μS 3KA combined wave surge; Figure 13 shows the discharge current flowing through the air-core inductor at 0.5μS_100KHz 6KV, the ringing wave surge and the voltage waveform at both ends.

4. Metal oxide varistor (MOV):

Metal Oxide Varistors (MOVs) are non-linear surge absorbing components that inherently absorb surge energy. The clamping voltage value of the MOV is determined by the surge current, and the clamping voltage waveform of the MOV and the discharge current waveform through it determine the energy it absorbs ( $\mathrm{E.}={{\∫}^{t2}}_{t1}\left(\mathrm{VXI}\right)\mathrm{dt}$ , t1-t2 is the time when the current waveform exists). Figure 14 and Figure 15 show the clamping voltage waveform and the discharge current waveform of the MOV under surge. In Figure 14, it is shown that the MOV absorbs 44 Joules of energy ( $\mathrm{E.}={{\∫}^{t2}}_{t1}\left(\mathrm{VXI}\right)\mathrm{dt}$ ); in Figure 15, it is shown that the MOV absorbs 62m joule energy under the 0.5μS_100KHz 6KV ringing wave surge ( $\mathrm{E.}={{\∫}^{t2}}_{t1}\left(\mathrm{VXI}\right)\mathrm{dt}$ ).

The circuit components of the present invention, through the above-mentioned test analysis, can know the functionality of each component on the three-layer symmetrical suppression circuit; on the power supply system, the circuit of the present invention can be used to "absorb surge energy" Suppress various interference surges in electrical equipment, so that electrical equipment is closely and safely protected.

The comprehensive test and analysis of the suppression ability of the high-efficiency symmetrical surge suppression circuit of the present invention:

This circuit uses the surge generating equipment manufactured by KEYTEK as the surge source, and its surge energy is shown in Table 1 for details. In the offline (Off-Line) and online (On-Lin) situations, with personal computers and communication equipment as the protected objects, using vulnerable interference surges for more than 200 consecutive surges at intervals of 30 seconds; susceptibility interference surges 10 There are more than 1,000 continuous surges at intervals of one second. During the entire test process, there is no damage or movement of the personal computer and the reading device. The surge method and test records are as follows:

(1) Analysis of energy absorption efficiency:

The absorbed energy of the surge suppression method = (the surge energy contained in the surge source) - (the residual surge energy entering the electrical equipment).

When the surge energy contained in the surge source is known, use a digital oscilloscope with digital operation function to calculate the residual surge energy entering the electrical equipment with (E=∫(VXI)dt), and you can know the surge energy energy absorbed by the surge suppression method. In Figures 16, 17, 18 and 19, the combined wave surge with energy above 1.2/50μS 6KV and 8/20μS 3KA100 joules is superimposed on the AC110V power supply, and then enters six and a half digits through the symmetrical surge suppressor of the present invention. Waveform monitoring of residual surge voltage, current, and energy of high-precision digital ammeters. Figures 17, 18 and 19 are the expansions of the horizontal axis in Figure 16 at different magnifications; from top to bottom are the clamping voltage inside the surge suppressor circuit, the discharge current, the residual surge voltage and residual discharge current entering the electrical equipment. Among the waveforms in Figure 20, the first waveform from top to bottom is the waveform of the residual surge energy entering the six-and-a-half-digit high-precision digital meter obtained after the mathematical operation of the waveform in Figure 19, which is 34.1m joules (in vector mode, the integral The unit of obtained energy value is represented by VS).

It can be seen from the above analysis that the surge suppression circuit of the present invention can absorb more than 99.96 joules of surge energy out of 100 joules of energy, and the surge absorption efficiency is more than 99.9%, almost completely suppressing and absorbing external surge energy.

(2) Vulnerability interference surge testing:

The main purpose of the vulnerability interference surge test is to check whether the tested object is burned or malfunctioned due to the surge energy.

A. Off-line, vulnerable interference surge common-mode coupling suppression capability test:

Combined surge: open circuit voltage 1.2/50μS 6KV or more, short circuit 8/20μS 3KA or more, and output energy of more than 100 joules to test the surge suppression capability of the circuit of the present invention in common mode coupling mode. For details of clamping voltage and discharge current waveform, see Figure 21, 22 and 23, each parameter value, see Table 2.

B. Single-phase three-wire type, offline, vulnerable interference surge common mode coupling suppression ability test:

With 1.2/50μS, 6KV, 8/20μS 3KA and above, the positive and negative polarities of the combined wave surge are alternated, superimposed on different phases of AC110V, with a general PC as the load, with an interval of 30 seconds, and two cycles of 64 consecutive surges For the test, the detailed computer records are shown in Table 3, and there is no abnormal situation on the PC. In the off-line condition, the positive polarity surge clamping voltage waveforms were taken after the time axis was unfolded several times, as shown in Figures 24, 25, 26, 27 and 28. See Figures 29, 30 and 31 for negative polarity surge clamping voltage waveforms.

The average clamping voltage is 285V and the standard deviation is 150V

The average value of the total discharge current is 3306A and the standard deviation is 64A

The common mode surge on the AC110V power supply is suppressed by the symmetrical surge suppression circuit, and the AC110V power supply has returned to normal within 8mS.

C. In the offline situation, the vulnerability interference surge normal mode coupling suppression ability test:

With 1.2/50μS, 6KV, 8/20μS, and 3KA combined wave surge, the circuit of the present invention is tested for surge suppression capability in normal mode coupling mode. See Figures 32, 33, 34 and 35 for details of clamping voltage and discharge current waveforms. See Table 4 for parameter values.

D. AC single-phase three-wire type, in the online situation, the vulnerability interference surge normal mode coupling suppression ability test:

With 1.2/50μS, 6KV, 8/20μS, and above 3KA, the positive and negative polarities of combined wave surges are alternated, superimposed on different phases of AC110V, and a general PC is used as the load, with an interval of 30 seconds, for two cycles of 64 consecutive surge tests , the detailed computer records are shown in Table 5, and there is no abnormal situation on the PC. In the online situation, the surge clamping voltage waveforms captured after the time axis has been unfolded several times are shown in Figures 36, 37, 38, 39 and 40.

The average clamping voltage at the output terminal is 602V and the standard deviation is 123V

The average value of the total discharge current is 2737A and the standard deviation is 34A

E.DC_48V, under the online condition, the vulnerability interference surge normal mode coupling suppression ability test:

With 1.2/50μS, 6KV, 8/20μS, and 3KA or more, the positive and negative polarities of the combined wave surge are alternated, superimposed on DC_48V, and the general telephone switchboard is used as the load, with an interval of 30 seconds, and two cycles of 20 consecutive surge tests are performed. Details The computer records are shown in Attachment 6, and there was no abnormal situation on the telephone switchboard. In the online situation, the surge clamping voltage waveforms captured after the time axis has been expanded several times are shown in Figures 41, 42, 43 and 44.

The average clamping voltage at the output terminal is 1456V and the standard deviation is 490V

The average value of the total discharge current is 2564A and the standard deviation is 59A

(3) Susceptibility ineterference surge testing:

The main purpose of the susceptibility interference surge test is to check whether there is any malfunction of the tested object due to the rapid rise of the surge.

A. In the offline situation, the common mode coupling suppression ability test of the perceptual interference surge:

Surge with ringing wave: open circuit voltage 0.5μS_100KHz 6KV, short circuit current 500A or more, and output 7 joules to test the surge suppression capability of the circuit of the present invention in common mode coupling mode. The clamping voltage and discharge current waveform are shown in Figures 45 and 46. The parameter values are shown in Table VII.

B. In the case of receptive interference surge common mode coupling suppression capability test (online):

With 0.5μS_100KHz 6KV ringing wave surge: superimposed on different phases of AC110V, with a general PC as the load, with an interval of 10 seconds, conduct a continuous surge test of 400 times for five cycles, see the attached table 8 for detailed computer records, and the PC has no abnormalities Situation happens. In the online situation, the surge clamping voltage waveforms captured after the time axis has been unfolded several times are shown in Figures 47, 48, 49 and 50.

The average clamping voltage at the output terminal is 523V and the standard deviation is 162V

The average value of the total discharge current is 493A and the standard deviation is 13A

The common mode surge on the AC110V power supply is suppressed by the symmetrical surge suppression circuit, and the AC110V power supply has returned to normal within 40μS.

C. Responsive interference surge normal mode coupling suppression ability test (on-line):

Surge with ringing wave: open circuit voltage 0.5μS_100KHz 6KV, short-circuit circuit 500A or more, output 7 joules to test the surge suppression capability of the circuit of the present invention in normal mode coupling mode, the clamp voltage and discharge current waveform are shown in Figures 51 and 52. The parameter values are shown in Table 9.

D. Responsive interference surge normal mode coupling suppression ability test (on-line):

With 0.5μS_100KHz 6KV ringing wave surge: superimposed on different phases of AC110V, with a general PC as the load, with an interval of 10 seconds, five cycles of 400 continuous surge tests, detailed computer records are shown in Appendix 10, and the PC has no abnormalities Situation happens. In the online situation, the waveforms of the surge clamping voltage captured after the time axis has been unfolded several times are shown in Figures 53, 54, 55 and 56 for details.

The average clamping voltage at the output terminal is 1061V and the standard deviation is 129V

The average value of the total discharge current is 386A and the standard deviation is 6A

E.DC_48V, under the online condition, the normal mode coupling suppression ability test of the perceptual interference surge:

With 0.5μS_100KHz 6KV ringing wave surge: superimposed on DC_48V, with a general telephone switchboard as the load, with an interval of 30 seconds, conduct 200 consecutive surge tests for 20 cycles. See attached table 11 for detailed computer records. The telephone switchboard has no An abnormal situation occurred. In the online situation, the waveforms of the surge clamping voltage captured after the time axis has been unfolded several times are shown in Figures 57, 58, 59 and 60.

The average output clamp voltage is 872V The standard deviation is 209V The average total discharge current is 333A The standard deviation is 23A

Claims (4)

1. surge restraint circuit, system is by the surge suppressor in the power circuit of being located at electric equipment, digital circuit, analog circuit, the control circuit, be used for suppressing to disturb surge, it is characterized in that, inhibitor wherein is to absorb the mode of surge energy, is main member by transient voltage surge suppression element, constitute three-layer type symmetric form surge suppressor

Wherein, described three-layer type symmetric form surge suppressor, system comprise by the semiconductor polymeric switch connect with circuit be ground floor, by the lightning-arrest pipe of metal oxide varistor series connection be the second layer, the T type inhibition circuit be made up of inductance and metal oxide varistor is the 3rd layer, the three-layer type symmetric form inhibition circuit that is constituted.

2. the surge restraint circuit described in claim 1 is characterized in that, described three-layer type symmetric form surge suppressor is to can be made into the independent interference surge inhibition protected location that uses on following low-voltage alternating current power supply of 220V or the socket.

3. the surge restraint circuit described in claim 1 is characterized in that, described three-layer type symmetric form surge suppressor is to can be made into the independent interference surge inhibition protected location that uses on the DC power supply circuit.

4. the surge restraint circuit described in claim 1 is characterized in that, described three-layer type symmetric form surge suppressor is wherein each layer circuit separation can be applied to respectively in the circuit of various electric equipments.

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