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CN105810666A - Fabrication method for package structure having electromagnetic shielding function - Google Patents

Fabrication method for package structure having electromagnetic shielding function Download PDF

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Publication number
CN105810666A
CN105810666A CN201610190042.5A CN201610190042A CN105810666A CN 105810666 A CN105810666 A CN 105810666A CN 201610190042 A CN201610190042 A CN 201610190042A CN 105810666 A CN105810666 A CN 105810666A
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China
Prior art keywords
chip
substrate
film
electromagnetic shielding
shielding function
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CN201610190042.5A
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Inventor
王仕勇
包旭升
王孙艳
梁新夫
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN201610190042.5A priority Critical patent/CN105810666A/en
Publication of CN105810666A publication Critical patent/CN105810666A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
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    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

本发明涉及一种具有电磁屏蔽功能的封装结构的制作方法,所述方法包括以下步骤:步骤一、将芯片通过倒装工艺设置在基板上;步骤二、取一张膜,在芯片上表面进行真空压膜,使得膜覆盖在基板上表面,并与芯片表面和侧面贴合;步骤三、通过光刻显影蚀刻工艺去除屏蔽芯片周围多余的膜;步骤四、将其他芯片或无源器件电性连接至基板上;步骤五、对基板进行包封,植球,最后切割成单品。本发明一种具有电磁屏蔽功能的封装结构的制作方法,它采用一种带有金属镀层的粘性膜直接贴在射频芯片表面或其他需要电磁屏蔽的芯片上,从而达到屏蔽电磁干扰的目的。

The present invention relates to a manufacturing method of a packaging structure with electromagnetic shielding function. The method comprises the following steps: step 1, setting a chip on a substrate through a flip-chip process; step 2, taking a film and performing Vacuum film pressing, so that the film covers the upper surface of the substrate and adheres to the surface and side of the chip; Step 3, remove the excess film around the shielding chip through photolithography, development and etching process; Step 4, electrically connect other chips or passive devices Connect to the substrate; step five, encapsulate the substrate, plant balls, and finally cut into individual products. The invention discloses a manufacturing method of a packaging structure with electromagnetic shielding function, which adopts a viscous film with a metal plating layer to be directly pasted on the surface of a radio frequency chip or other chips requiring electromagnetic shielding, thereby achieving the purpose of shielding electromagnetic interference.

Description

一种具有电磁屏蔽功能的封装结构的制作方法A method for manufacturing a packaging structure with electromagnetic shielding function

技术领域 technical field

本发明涉及一种具有电磁屏蔽功能的封装结构的制作方法,属于半导体封装技术领域。 The invention relates to a manufacturing method of a packaging structure with electromagnetic shielding function, belonging to the technical field of semiconductor packaging.

背景技术 Background technique

现有的电磁屏蔽结构为:直接在塑封体上通过溅射或电镀的方式,在塑封体表面覆盖金属,起到电磁屏蔽的效果。其主要存在的缺陷如下: The existing electromagnetic shielding structure is as follows: the surface of the plastic package is directly covered with metal by sputtering or electroplating on the plastic package to achieve the effect of electromagnetic shielding. Its main defects are as follows:

1、在塑封体表面进行溅射或电镀方式,工艺较为复杂,而且成本较为昂贵; 1. Sputtering or electroplating on the surface of the plastic package, the process is more complicated and the cost is more expensive;

2、镀层金属与塑封体的结合力比较难控制; 2. The bonding force between the plated metal and the plastic package is difficult to control;

3、对多芯片的模组来说,很难实现对局部单芯片的电磁屏蔽。 3. For multi-chip modules, it is difficult to achieve electromagnetic shielding for partial single chips.

发明内容 Contents of the invention

本发明所要解决的技术问题是针对上述现有技术提供一种具有电磁屏蔽功能的封装结构的制作方法,它采用一种带有金属镀层的粘性膜直接贴在射频芯片表面或其他需要电磁屏蔽的芯片上,从而达到屏蔽电磁干扰的目的。 The technical problem to be solved by the present invention is to provide a method for manufacturing a packaging structure with electromagnetic shielding function in view of the above-mentioned prior art, which uses a kind of adhesive film with metal plating to directly stick on the surface of the radio frequency chip or other devices that require electromagnetic shielding. On the chip, so as to achieve the purpose of shielding electromagnetic interference.

本发明解决上述问题所采用的技术方案为:一种具有电磁屏蔽功能的封装结构的制作方法,所述方法包括以下步骤: The technical solution adopted by the present invention to solve the above problems is: a method for manufacturing a packaging structure with electromagnetic shielding function, said method comprising the following steps:

步骤一、将芯片通过倒装工艺设置在基板上; Step 1, setting the chip on the substrate through the flip-chip process;

步骤二、取一张膜,在芯片上表面进行真空压膜,使得膜覆盖在基板上表面,并与芯片表面和侧面贴合; Step 2. Take a piece of film, and vacuum-press the film on the upper surface of the chip, so that the film covers the upper surface of the substrate and adheres to the surface and side of the chip;

步骤三、通过光刻显影蚀刻工艺去除屏蔽芯片周围多余的膜; Step 3, removing excess film around the shielding chip through photolithography, development and etching process;

步骤四、将其他芯片或无源器件电性连接至基板上; Step 4, electrically connecting other chips or passive devices to the substrate;

步骤五、对基板进行包封,植球,最后切割成单品。 Step 5: Encapsulate the substrate, plant balls, and finally cut into individual products.

所述芯片为普通芯片,所述芯片通过底部填充胶设置于基板上。 The chip is an ordinary chip, and the chip is arranged on the substrate through the bottom filling glue.

所述芯片为表面声波芯片,芯片上表面真空压膜后在芯片与基板之间形成空腔。 The chip is a surface acoustic wave chip, and a cavity is formed between the chip and the substrate after the upper surface of the chip is vacuum-pressed.

所述膜为表面带金属层的粘性膜。 The film is an adhesive film with a metal layer on the surface.

多个芯片倒装于基板上,在多个芯片上表面进行真空压膜 Multiple chips are flip-chip on the substrate, and vacuum lamination is performed on the upper surface of multiple chips

与现有技术相比,本发明的优点在于: Compared with the prior art, the present invention has the advantages of:

1、采用带金属镀层的膜与芯片粘结,避免了金属镀层与塑封体结合不良的问题; 1. The film with metal coating is bonded to the chip, which avoids the problem of poor bonding between the metal coating and the plastic package;

2、封装过程无需加入传统的电镀工艺和金属溅射工艺,采用贴膜方式,操作方便,简化了工艺流程,极大地降低了加工成本; 2. The packaging process does not need to join the traditional electroplating process and metal sputtering process. It adopts the film method, which is easy to operate, simplifies the process flow, and greatly reduces the processing cost;

3、适用于多芯片模组封装,可以对单个芯片起到电磁屏蔽的效果,能更有效的避免芯片与芯片之间的电磁干扰; 3. It is suitable for multi-chip module packaging, which can play an electromagnetic shielding effect on a single chip, and can more effectively avoid electromagnetic interference between chips;

4、适用于表面声波芯片的封装,可以简化工艺步骤,缩小封装体积。 4. It is suitable for the packaging of surface acoustic wave chips, which can simplify the process steps and reduce the packaging volume.

附图说明 Description of drawings

图1为本发明一种具有电磁屏蔽功能的封装结构的示意图。 FIG. 1 is a schematic diagram of a packaging structure with electromagnetic shielding function according to the present invention.

图2为本发明一种具有电磁屏蔽功能的封装结构另一实施例的示意图。 FIG. 2 is a schematic diagram of another embodiment of a package structure with electromagnetic shielding function according to the present invention.

其中: in:

基板1 Substrate 1

金属凸块2 Metal bump 2

芯片3 chip 3

膜4 film 4

塑封料5 Plastic compound 5

锡球6 Solder ball 6

底部填充胶7 Underfill 7

空腔8。 Cavity 8.

具体实施方式 detailed description

以下结合附图实施例对本发明作进一步详细描述。 The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

如图1所示,本实施例中的一种具有电磁屏蔽功能的封装结构,它包括基板1,所述基板1上通过金属凸块2倒装有芯片3,所述芯片3上方包覆有膜4,所述膜4与芯片3表面和侧面相结合,所述基板1上方包封有塑封料5,所述基板1底部设置有锡球6。 As shown in Figure 1, a packaging structure with electromagnetic shielding function in this embodiment includes a substrate 1, on which a chip 3 is flip-mounted through a metal bump 2, and the top of the chip 3 is covered with A film 4 , the film 4 is combined with the surface and side of the chip 3 , the top of the substrate 1 is encapsulated with a molding compound 5 , and the bottom of the substrate 1 is provided with solder balls 6 .

所述芯片3为普通芯片,所述芯片3与基板1之间设置有底部填充胶7。 The chip 3 is an ordinary chip, and an underfill glue 7 is disposed between the chip 3 and the substrate 1 .

所述膜4为表面带有金属层的粘性膜。 The film 4 is an adhesive film with a metal layer on its surface.

其制造方法包括如下步骤: Its manufacturing method comprises the following steps:

步骤一、将芯片通过倒装工艺设置在基板上; Step 1, setting the chip on the substrate through the flip-chip process;

步骤二、取一张膜,在芯片上表面进行真空压膜,使得膜覆盖在基板上表面,并与芯片表面和侧面贴合; Step 2. Take a piece of film, and vacuum-press the film on the upper surface of the chip, so that the film covers the upper surface of the substrate and adheres to the surface and side of the chip;

步骤三、通过光刻显影蚀刻工艺去除屏蔽芯片周围多余的膜; Step 3, removing excess film around the shielding chip through photolithography, development and etching process;

步骤四、将其他芯片或无源器件电性连接至基板上; Step 4, electrically connecting other chips or passive devices to the substrate;

步骤五、对基板进行包封,植球,最后切割成单品。 Step 5: Encapsulate the substrate, plant balls, and finally cut into individual products.

参见图2,本实施例中的一种具有电磁屏蔽功能的封装结构,所述芯片3为表面声波芯片,芯片3与基板1之间形成空腔8。 Referring to FIG. 2 , a packaging structure with electromagnetic shielding function in this embodiment, the chip 3 is a surface acoustic wave chip, and a cavity 8 is formed between the chip 3 and the substrate 1 .

所述膜4包覆的芯片可以有多个。 There may be multiple chips covered by the film 4 .

除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。 In addition to the above-mentioned embodiments, the present invention also includes other implementations, and any technical solution formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the claims of the present invention.

Claims (5)

1.一种具有电磁屏蔽功能的封装结构的制作方法,其特征在于所述方法包括以下步骤: 1. A method for making a packaging structure with electromagnetic shielding function, characterized in that said method may further comprise the steps: 步骤一、将芯片通过倒装工艺设置在基板上; Step 1, setting the chip on the substrate through the flip-chip process; 步骤二、取一张膜,在芯片上表面进行真空压膜,使得膜覆盖在基板上表面,并与芯片表面和侧面贴合; Step 2. Take a piece of film, and vacuum-press the film on the upper surface of the chip, so that the film covers the upper surface of the substrate and adheres to the surface and side of the chip; 步骤三、通过光刻显影蚀刻工艺去除屏蔽芯片周围多余的膜; Step 3, removing excess film around the shielding chip through photolithography, development and etching process; 步骤四、将其他芯片或无源器件电性连接至基板上; Step 4, electrically connecting other chips or passive devices to the substrate; 步骤五、对基板进行包封,植球,最后切割成单品。 Step 5: Encapsulate the substrate, plant balls, and finally cut into individual products. 2.根据权利要求1所述的一种具有电磁屏蔽功能的封装结构的制作方法,其特征在于:所述芯片为普通芯片,所述芯片通过底部填充胶设置于基板上。 2 . The manufacturing method of a packaging structure with electromagnetic shielding function according to claim 1 , wherein the chip is a common chip, and the chip is arranged on the substrate through an underfill glue. 3 . 3.根据权利要求1所述的一种具有电磁屏蔽功能的封装结构的制作方法,其特征在于:所述芯片为表面声波芯片,芯片上表面真空压膜后在芯片与基板之间形成空腔。 3. The manufacturing method of a packaging structure with electromagnetic shielding function according to claim 1, characterized in that: the chip is a surface acoustic wave chip, and a cavity is formed between the chip and the substrate after the vacuum lamination on the upper surface of the chip . 4.根据权利要求1所述的一种具有电磁屏蔽功能的封装结构的制作方法,其特征在于:所述膜为表面带金属层的粘性膜。 4 . The method for manufacturing a packaging structure with electromagnetic shielding function according to claim 1 , wherein the film is an adhesive film with a metal layer on the surface. 5.根据权利要求1所述的一种具有电磁屏蔽功能的封装结构的制作方法,其特征在于:多个芯片倒装于基板上,在多个芯片上表面进行真空压膜。 5. The manufacturing method of a packaging structure with electromagnetic shielding function according to claim 1, characterized in that: a plurality of chips are flip-chip mounted on the substrate, and vacuum lamination is performed on the upper surfaces of the plurality of chips.
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273418A (en) * 2018-11-08 2019-01-25 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 Chip package structure and method
CN110010507A (en) * 2019-04-04 2019-07-12 中电海康无锡科技有限公司 SIP module subregion is electromagnetically shielded packaging method
CN110248298A (en) * 2019-05-13 2019-09-17 苏州捷研芯纳米科技有限公司 Silicon microphone and its processing method
US10643955B2 (en) 2018-06-14 2020-05-05 Universal Scientific Industrial (Shanghai) Co., Ltd. Method of manufacturing SiP module based on double plastic-sealing and the SiP module
CN111642122A (en) * 2020-05-27 2020-09-08 维沃移动通信有限公司 Electromagnetic shielding structure and manufacturing method thereof
US10798814B2 (en) 2018-06-14 2020-10-06 Universal Scientific Industrial (Shanghai) Co., Ltd. SiP module and manufacturing method of the SiP module
CN112701096A (en) * 2020-12-22 2021-04-23 杰群电子科技(东莞)有限公司 Semiconductor module packaging process and semiconductor module
CN113140660A (en) * 2020-01-20 2021-07-20 光宝光电(常州)有限公司 Packaging structure and manufacturing method thereof
CN113206052A (en) * 2021-04-28 2021-08-03 全讯射频科技(无锡)有限公司 Packaging structure and manufacturing method of radio frequency module
CN113604184A (en) * 2021-10-09 2021-11-05 武汉市三选科技有限公司 Chip packaging material, chip packaging structure and packaging method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1293485A (en) * 1999-10-15 2001-05-02 汤姆森无线电报总公司 Electron element packaging method
US20030009864A1 (en) * 2001-07-12 2003-01-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter package
US20060151203A1 (en) * 2002-08-22 2006-07-13 Hans Krueger Encapsulated electronic component and production method
US20090170242A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. System-in-Package Having Integrated Passive Devices and Method Therefor
CN202705026U (en) * 2011-05-23 2013-01-30 埃普科斯股份有限公司 Apparatus having MEMS devices
CN103493371A (en) * 2011-04-21 2014-01-01 株式会社村田制作所 Circuit module

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1293485A (en) * 1999-10-15 2001-05-02 汤姆森无线电报总公司 Electron element packaging method
US20030009864A1 (en) * 2001-07-12 2003-01-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter package
US20060151203A1 (en) * 2002-08-22 2006-07-13 Hans Krueger Encapsulated electronic component and production method
US20090170242A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. System-in-Package Having Integrated Passive Devices and Method Therefor
CN103493371A (en) * 2011-04-21 2014-01-01 株式会社村田制作所 Circuit module
CN202705026U (en) * 2011-05-23 2013-01-30 埃普科斯股份有限公司 Apparatus having MEMS devices

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10643955B2 (en) 2018-06-14 2020-05-05 Universal Scientific Industrial (Shanghai) Co., Ltd. Method of manufacturing SiP module based on double plastic-sealing and the SiP module
US10798814B2 (en) 2018-06-14 2020-10-06 Universal Scientific Industrial (Shanghai) Co., Ltd. SiP module and manufacturing method of the SiP module
CN109273418A (en) * 2018-11-08 2019-01-25 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 Chip package structure and method
CN110010507A (en) * 2019-04-04 2019-07-12 中电海康无锡科技有限公司 SIP module subregion is electromagnetically shielded packaging method
CN110248298A (en) * 2019-05-13 2019-09-17 苏州捷研芯纳米科技有限公司 Silicon microphone and its processing method
CN113140660A (en) * 2020-01-20 2021-07-20 光宝光电(常州)有限公司 Packaging structure and manufacturing method thereof
CN111642122A (en) * 2020-05-27 2020-09-08 维沃移动通信有限公司 Electromagnetic shielding structure and manufacturing method thereof
CN112701096A (en) * 2020-12-22 2021-04-23 杰群电子科技(东莞)有限公司 Semiconductor module packaging process and semiconductor module
CN113206052A (en) * 2021-04-28 2021-08-03 全讯射频科技(无锡)有限公司 Packaging structure and manufacturing method of radio frequency module
CN113604184A (en) * 2021-10-09 2021-11-05 武汉市三选科技有限公司 Chip packaging material, chip packaging structure and packaging method

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