CN105789334B - A kind of Schottky barrier semiconductor rectifier and its manufacturing method - Google Patents

Abstract

The invention discloses a Schottky barrier semiconductor rectifier, which comprises a Schottky barrier metal layer, an epitaxial layer and a first groove, and an isolation layer and a silicon dioxide gate oxide layer are arranged in the first groove, and the silicon dioxide The silicon gate oxide layer extends upwards to form a dielectric wall. Conductive polysilicon sidewalls are provided on both sides of the dielectric wall. A second trench is provided between the upper part of the epitaxial layer and the conductive polysilicon sidewall. The upper part of the epitaxial layer is provided with a horizontal uniform doping area and a gradient In the doping region, a channel is provided between the gradient doping region and the silicon dioxide gate oxide layer, and a spacer is provided between the lower part of the epitaxial layer, the lateral uniform doping region, the gradient doping region and the silicon dioxide gate oxide layer, A third groove is arranged in the second groove, and the Schottky barrier metal layer is located on the inner surface of the third groove and contacts the epitaxial layer to form a Schottky barrier. The invention has good forward conduction characteristics and device reliability. The invention also discloses a manufacturing method of the Schottky barrier semiconductor rectifier, which has a large process window, is easy to control, has less photolithography times and low manufacturing cost.

Description

A Schottky barrier semiconductor rectifier and its manufacturing method

technical field

The invention relates to the technical field of semiconductor device manufacturing, in particular to a Schottky barrier semiconductor rectifier and a manufacturing method thereof.

Background technique

As a conversion device of electric energy, semiconductor rectifiers have higher and higher requirements for performance improvement such as reducing forward voltage drop, increasing reverse blocking voltage, reducing reverse leakage, and increasing switching speed for the sake of improving system efficiency. .

The PN junction diode used as a semiconductor rectifier earlier, due to the need to overcome the PN junction barrier during forward conduction, resulting in high forward conduction voltage drop, and the low switching speed caused by minority carrier injection during forward conduction, has been adopted by SCHOTT in many application fields. base barrier diodes instead. Schottky barrier diodes are usually composed of an N-type epitaxial layer with a low doping concentration and a metal layer deposited on the top surface to form a Schottky barrier. The voltage required to overcome the Schottky barrier is lower than the PN junction barrier when the device is forward-conducting, and the Schottky barrier diode is a multi-subconductive device with fast switching speed. Even so, due to the existence of the Schottky barrier, a small forward conduction current will also produce a certain forward conduction voltage drop. By selecting different metals, the barrier height can be reduced to reduce the forward conduction voltage drop, but the reverse leakage will increase accordingly, and the reverse blocking voltage may also decrease. At the same time, the Schottky barrier diode also has the effect of reducing the barrier height, that is, the phenomenon that the barrier height decreases with the increase of the reverse bias voltage, which will further increase the reverse leakage, reduce the reverse blocking voltage and Reduce device reliability, thereby limiting the application of low barrier height in devices. In order to overcome the above problems, US Patent No. 5,365,102 discloses a trench Schottky barrier diode, which is characterized in that there are several periodically arranged trench gates in the N-type epitaxial layer, and the N-type epitaxial layer and the top surface A Schottky barrier formed by the deposited metal layer exists between the trench gates. The trench gate is composed of a trench extending into the N-type epitaxial layer, an isolation layer covering the surface of the trench, and a conductive material filled therein and connected to a metal layer deposited on the top surface. The periodically arranged trench gate structure reduces the electric field intensity at the Schottky barrier when the device is reverse-biased, partially suppresses the effect of reducing the barrier height, and enables the device to adopt a lower barrier height. However, the Schottky barrier still exists, and the trench gate structure occupies the conductive surface area, so that the problem of large forward conduction voltage drop under low current of the device still exists.

U.S. Patent US 5818084 discloses a semiconductor rectifier without Schottky barrier. The anode of the device is formed by shorting the gate, source, and body electrodes of the trench MOSFET device, and the cathode is formed by the drain of the trench MOSFET device. pole pose. The salient feature of this technology is the use of a trench gate structure, the channel is perpendicular to the surface of the semiconductor wafer, and the body effect of the MOSFET device is used to reduce the turn-on threshold voltage, so that the anode of the device is positively charged, that is, when it is forward biased, a conductive channel is formed. The required voltage is lower than the forward turn-on voltage of the PN junction diode. At the same time, because the forward conduction channel of the rectifier is the channel of the MOSFET device, there is no minority carrier injection phenomenon in the forward conduction process. The rectifier is integrated in the trench MOSFET chip, which can prevent the parasitic PN junction diode of the MOSFET from turning on, thereby further avoiding the large reverse recovery current and high reverse recovery voltage introduced when the parasitic diode switches from forward conduction to reverse conduction Spike question. However, devices based on this technology act as stand-alone semiconductor rectifiers with a forward voltage drop greater than that of a Schottky barrier diode. US Patent No. 6,420,225 discloses a semiconductor rectifier based on a planar MOSFET, that is, the anode of the device is formed by shorting the gate, source and body electrodes of the planar MOSFET device, and the cathode is formed by the drain. The device forms a dielectric side wall by anisotropic etching, and uses the side wall to protect the ion implantation region below to form a channel. US Patent No. 6,448,160 discloses a semiconductor rectifier based on a planar MOSFET. The photoresist is partially stripped by an oxygen plasma isotropic etching method, and a channel is formed under the stripped area of the photoresist by ion implantation. US Patent US 6765264 discloses a semiconductor rectifier based on a planar MOSFET. The device uses isotropic etching to change the sidewall of the dielectric mask from vertical to the surface of the silicon wafer to have a certain slope. Through the slope side The wall is implanted with ions to form a channel, and the doping concentration of the channel has a gradient. The salient feature of these technologies is the use of a planar gate structure, the channel is parallel to the surface of the semiconductor wafer, and the channel length is short. Due to the short channel and channel doping gradient distribution, the threshold voltage of the conductive channel is significantly reduced, thereby reducing the forward conduction voltage drop of the device, especially the forward conduction voltage drop under small current is significantly lower than Xiao Tertyl barrier diode. However, due to the limitations of the methods for forming short channels and channel doping gradient distribution, such devices are usually based on a planar gate structure, and there are junction field effect transistors formed by parasitic body doping regions inside the device, and the parasitic junction field effect transistors increase The series resistance on the conductive channel is increased, and at the same time, the increase of the conductive channel density is limited; in order to avoid the possible punch-through leakage caused by the short channel when the device is reverse biased, the doping concentration of the epitaxial layer is usually low, which further increases the Series resistance on the conduction channel; the above two points make the forward conduction voltage drop of the device high under high current, usually higher than that of trench Schottky barrier diode.

It can be seen that the prior art still lacks in the forward conduction voltage drop of the semiconductor rectifier, and it is of great significance to further improve the device structure and manufacturing method.

Contents of the invention

The present invention is to solve the above-mentioned problems existing in the semiconductor rectifier in the prior art, and provides a trench gate structure based on a short channel and a Schottky barrier contact, which has better forward conduction characteristics, especially It is a Schottky barrier semiconductor rectifier with better forward voltage drop performance under high current and better device reliability.

The present invention also provides a method for manufacturing a Schottky barrier semiconductor rectifier. The manufacturing method has a large process window, is easy to control, has few manufacturing steps, and has low manufacturing cost. The impurity gradient distribution can effectively improve the forward conduction performance of the device.

In order to achieve the above object, the present invention adopts the following technical solutions:

A Schottky barrier semiconductor rectifier of the present invention comprises an anode metal layer, a Schottky barrier metal layer, a lightly doped epitaxial layer of the first conductivity type, and a monolayer heavily doped of the first conductivity type from top to bottom. A crystalline silicon substrate and a cathode metal layer, the upper part of the epitaxial layer is laterally provided with a plurality of first grooves at intervals, the first grooves are filled with conductive polysilicon, and isolation is provided between the conductive polysilicon and the first grooves Layer, the isolation layer is provided with a silicon dioxide gate oxide layer, the thickness of the silicon dioxide gate oxide layer is smaller than the isolation layer, the top of the silicon dioxide gate oxide layer extends upward and is higher than the top surface of the epitaxial layer to form a dielectric wall, so Conductive polysilicon sidewalls of the first conductivity type are provided on both sides of the dielectric wall, the area between the upper part of the epitaxial layer and the conductive polysilicon sidewall outside the dielectric wall forms a second groove, and the bottom of the conductive polysilicon sidewall located outside the dielectric wall A heavily doped region of the first conductivity type is provided higher than the bottom of the second trench, and a second conductive region separating the second trench, the heavily doped region of the first conductivity type and the epitaxial layer is provided on the upper part of the epitaxial layer. Type non-uniformly doped region, the second conductivity type non-uniformly doped region includes a lateral uniformly doped region and a gradient doped region, and the gradiently doped region is located on both sides of the lateral uniformly doped region and the silicon dioxide The gate oxide layer is contacted to form a channel, and a spacer is provided between the lower part of the epitaxial layer, the horizontal uniformly doped region, the gradient doped region and the silicon dioxide gate oxide layer, and the horizontal uniformly doped region has doped in the longitudinal direction. Gradient distribution, the second groove is provided with a third groove, the third groove penetrates the non-uniformly doped region of the second conductivity type and extends into the epitaxial layer, and the Schottky barrier metal layer covers Inside the third trench and in contact with the epitaxial layer to form a Schottky barrier.

A method for manufacturing a Schottky barrier semiconductor rectifier, comprising the following steps:

(1) Growing a lightly doped epitaxial layer of the first conductivity type on a heavily doped single crystal silicon substrate of the first conductivity type.

(2) Forming a first trench in the epitaxial layer by photolithography and dry etching.

(3) A silicon dioxide layer is grown on the top layer of the entire structure as an isolation layer.

(4) A silicon nitride layer is deposited on the entire surface of the structure as a mask layer.

(5) Depositing a silicon dioxide filling layer on the entire surface of the structure to fill the first trench.

(6) Selectively removing part of the silicon dioxide filling layer by wet etching to expose the upper part of the first trench.

(7) Selectively remove the mask layer not protected by the silicon dioxide filling layer by wet etching.

(8) Wet etching is used to selectively remove the isolation layer not protected by the mask layer and the remaining silicon dioxide filling layer.

(9) Wet etching is used to remove the remaining mask layer.

(10) A silicon dioxide gate oxide layer is grown on the top layer of the entire structure.

(11) Depositing conductive polysilicon on the top layer of the entire structure, so that the conductive polysilicon fills the first trench.

(12) Selectively remove part of the conductive polysilicon by dry etching, so that the top surface of the conductive polysilicon is flush with the top surface of the epitaxial layer.

(13) Part of the silicon dioxide gate oxide layer is selectively removed by dry etching, so that the tops of the epitaxial layer on both sides of the first trench are exposed.

(14) Selectively remove part of the conductive polysilicon and the epitaxial layer by dry etching, so that the silicon dioxide gate oxide layer is higher than the top surface of the epitaxial layer to form a dielectric wall.

(15) Depositing polysilicon of the first conductivity type on the top layer of the entire structure.

(16) Heat treatment is used to diffuse impurities in the polysilicon of the first conductivity type into the top of the epitaxial layer to form a heavily doped region of the first conductivity type.

(17) Use dry etching to remove part of the conductive polysilicon of the first conductivity type and the epitaxial layer, form the conductive polysilicon sidewalls of the first conductivity type on both sides of the dielectric wall, and form the second trench in the epitaxial layer without sidewall barriers groove, and the depth of the second groove is greater than the thickness of the heavily doped region of the first conductivity type.

(18) Using the first ion implantation to introduce the first laterally evenly distributed impurity region of the second conductivity type into the epitaxial layer below the second trench, and introduce the impurity region of the second conductivity type under the heavily doped region of the first conductivity type The first gradient distribution impurity region.

(19) Use the second ion implantation to introduce a second laterally evenly distributed impurity region of the second conductivity type into the epitaxial layer below the second trench, and introduce a second conductivity type impurity region under the heavily doped region of the first conductivity type. The second gradient distribution impurity region.

(20) Using the third ion implantation to introduce a third lateral uniformly distributed impurity region of the second conductivity type into the epitaxial layer below the second trench.

(21) The implanted impurities are activated by heat treatment. The first uniformly distributed impurity region, the second uniformly distributed impurity region, and the third uniformly distributed impurity region form a uniformly doped lateral region. The first gradiently distributed impurity region, the second The two gradiently distributed impurity regions constitute a gradient doping region, and the lateral uniform doping region and the gradient doping region constitute a second conductivity type non-uniform doping region to separate the first conductivity type heavily doped region, the second trench and the The lower part of the epitaxial layer.

(22) The third trench is formed in the middle of the second trench by photolithography and dry etching, and the depth of the third trench exceeds the bottom of the non-uniformly doped region of the second conductivity type by controlling the etching time.

(23) Depositing a Schottky barrier metal layer on the top surface of the entire structure.

(24) Deposit an anodic metal layer on the top surface of the entire structure.

(25) After thinning the heavily doped single crystal silicon substrate of the first conductivity type, a cathode metal layer is deposited on the bottom surface to obtain a semiconductor rectifier with trench gate structure.

Preferably, the implantation energy used for the third ion implantation in step (20) is lower than the implantation energy used for the second ion implantation in step (19).

Therefore, the present invention has following beneficial effect:

(1) The trench gate structure is adopted to eliminate the parasitic junction field effect transistor, reduce the series resistance on the conductive channel, and reduce the forward voltage drop of the device;

(2) Using trench gate structure, it is easy to increase the density of conductive channels and reduce the forward conduction voltage drop of the device;

(3) The adjacent trench gate extending into the epitaxial layer can form a pinch-off when the device is reverse biased to protect the channel, reduce the electric field intensity at the channel, and suppress short-channel punch-through leakage, so that the epitaxial layer can Higher doping concentration is used to reduce the forward conduction voltage drop of the device;

(4) The trench gate adopts a structure combining a thick isolation layer and a thin gate oxide layer. A thicker isolation layer is conducive to sharing more reverse bias voltage, reducing the electric field intensity at the channel, and suppressing short-channel punch-through leakage; thinner The gate oxide layer can effectively reduce the threshold voltage;

(5) The spacer region set in the device can form a pinch-off to protect the channel when the device is reverse biased, and further suppress the short-channel punch-through leakage, so that the epitaxial layer can use a higher doping concentration, thereby reducing the positive current of the device. conduction pressure drop;

(6) The channel length is short and the doping concentration can be adjusted in gradients, which can effectively reduce the threshold voltage, thereby reducing the forward conduction voltage drop of the device, and at the same time can suppress the short-channel punch-through leakage that may occur when the device is reverse-biased;

(7) The channel length and channel doping concentration can be modulated by the sidewall morphology, and can also be modulated by the energy, dose, and implantation times of ion implantation, which is easy to realize short channels;

(8) The heavily doped region is realized by contacting the conductive polysilicon with the epitaxial layer and thermally diffusing. The impurity concentration in the heavily doped region is evenly distributed, which has little effect on the channel length and is easy to realize a short channel;

(9) The silicon dioxide gate oxide layer extends out of the surface of the epitaxial layer to form a dielectric wall, which will not affect the channel length due to process loss and other factors, and is easy to realize a short channel;

(10) The width of the spacer can be modulated by the shape of the sidewall, and the depth of the spacer can be modulated by the depth of the second trench, the energy of ion implantation, and the number of implants, which is easy to form pinch-off;

(11) Introducing the Schottky barrier region, as the forward bias voltage of the device increases, the Schottky barrier region participates in conduction, which can reduce the forward conduction voltage drop of the device under high current, or when the device is in a long time large Under the current forward conduction condition, as the junction temperature rises, the Schottky barrier begins to conduct forward conduction, reducing the burden on the conductive channel and improving device reliability;

(12) The process adopts a self-alignment process, which has a large process window and is easy to control. The number of photolithography in the whole process is small, the manufacturing steps are few, the manufacturing process is short, and the manufacturing cost is low.

Description of drawings

Fig. 1 is a sectional view of a structure of the present invention.

Fig. 2 is a schematic structural diagram of step (6) of embodiment 1.

Fig. 3 is a schematic structural diagram of step (nine) of embodiment 1.

Fig. 4 is a schematic structural diagram of step (12) of embodiment 1.

Fig. 5 is a schematic structural diagram of step (16) of embodiment 1.

Fig. 6 is a schematic structural diagram of step (20) of embodiment 1.

Fig. 7 is a schematic structural diagram of step (21) of Embodiment 1.

Fig. 8 is a schematic structural diagram of step (twenty-three) of embodiment 1.

In the figure: anode metal layer 1, epitaxial layer 2, monocrystalline silicon substrate 3, cathode metal layer 4, first trench 5, conductive polysilicon 6, isolation layer 7, dielectric wall 8, conductive polysilicon sidewall 9, second Trench 10, first conductivity type heavily doped region 11, second conductivity type non-uniform doping region 12, lateral uniform doping region 13, gradient doping region 14, channel 15, spacer region 16, first lateral uniform doping region Distribution impurity region 17, first gradient distribution impurity region 18, second lateral uniform distribution impurity region 19, second gradient distribution impurity region 20, third lateral uniform distribution impurity region 21, mask layer 22, silicon dioxide filling layer 23 , a silicon dioxide gate oxide layer 24 , a third trench 25 , a Schottky barrier metal layer 26 , and a conductive polysilicon 27 of the first conductivity type.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

A Schottky barrier semiconductor rectifier as shown in Figure 1, from top to bottom includes an anode metal layer 1, a Schottky barrier metal layer 26, a lightly doped epitaxial layer 2 of the first conductivity type, a first conductive A type of heavily doped single crystal silicon substrate 3 and a cathode metal layer 4, a plurality of first trenches 5 are arranged laterally at intervals on the upper part of the epitaxial layer, the first trenches are filled with conductive polysilicon 6, and the gap between the conductive polysilicon and the first trenches An isolation layer 7 is arranged between them, and a silicon dioxide gate oxide layer 24 is arranged on the isolation layer. The thickness of the silicon dioxide gate oxide layer is smaller than that of the isolation layer, and the top of the silicon dioxide gate oxide layer extends upward and is higher than the top surface of the epitaxial layer to form a dielectric wall. 8. Conductive polysilicon sidewalls 9 of the first conductivity type are provided on both sides of the dielectric wall, and the area between the upper part of the epitaxial layer and the conductive polysilicon sidewall outside the dielectric wall forms a second trench 10. The conductive polysilicon sidewall located outside the dielectric wall The bottom of the sidewall is provided with a first conductivity type heavily doped region 11 higher than the bottom of the second trench, and the upper part of the epitaxial layer is provided with a second trench, the first conductivity type heavily doped region and the epitaxial layer. Two conductive type non-uniformly doped regions 12, the second conductive type non-uniformly doped region includes a lateral uniformly doped region 13 and a gradient doped region 14, the gradient doped region is located on the upper part and the isolation layer on both sides of the lateral uniformly doped region A channel 15 is formed by contact, and a spacer 16 is provided between the lower part of the epitaxial layer, the lateral uniformly doped region, the gradient doped region, and the isolation layer, and the lateral uniformly doped region has a doping gradient distribution in the vertical direction. There is a third trench 25, the third trench penetrates the non-uniformly doped region of the second conductivity type and extends into the epitaxial layer, the Schottky barrier metal layer covers the inside of the third trench, and contacts the epitaxial layer to form a Schottky barrier metal layer. Teki barrier.

The Schottky barrier semiconductor rectifier is obtained by the following manufacturing method:

(1) growing a lightly doped epitaxial layer 2 of the first conductivity type on the heavily doped single crystal silicon substrate 3 of the first conductivity type;

(2) Forming the first trench 5 in the epitaxial layer by photolithography and dry etching;

(3) growing a silicon dioxide layer on the top layer of the entire structure as an isolation layer 7;

(4) Depositing a silicon nitride layer as a mask layer 22 on the entire surface of the structure;

(5) Depositing a silicon dioxide filling layer 23 on the entire surface of the structure to fill the first groove;

(6) Selectively remove the silicon dioxide filling layer by wet etching, exposing the upper part of the first trench (see Figure 2);

(7) Using wet etching to selectively remove the mask layer not protected by the silicon dioxide filling layer;

(8) Using wet etching to selectively remove the isolation layer not protected by the mask layer and the remaining silicon dioxide filling layer;

(9) Remove the remaining mask layer by wet etching (see Figure 3);

(10) growing a silicon dioxide gate oxide layer 24 on the top layer of the entire structure;

(11) Deposit conductive polysilicon 6 on the top layer of the entire structure, so that the conductive polysilicon fills the first trench;

(12) Selectively remove part of the conductive polysilicon by dry etching, so that the top surface of the conductive polysilicon is flush with the top surface of the epitaxial layer (see Figure 4);

(13) Selectively removing part of the silicon dioxide gate oxide layer by dry etching, so that the tops of the epitaxial layers on both sides of the first trench are exposed;

(14) Selectively remove part of the conductive polysilicon and epitaxial layer by dry etching, so that the silicon dioxide gate oxide layer is higher than the top surface of the epitaxial layer to form a dielectric wall 8;

(15) Depositing the first conductive type conductive polysilicon 27 on the top layer of the entire structure;

(16) Heat treatment is used to diffuse the impurities in the conductive polysilicon of the first conductivity type into the top of the epitaxial layer to form the heavily doped region 11 of the first conductivity type (see FIG. 5 );

(17) Use dry etching to remove part of the conductive polysilicon of the first conductivity type and the epitaxial layer, form the conductive polysilicon sidewall 9 of the first conductivity type on both sides of the dielectric wall, and form the second conductive polysilicon sidewall 9 in the epitaxial layer without sidewall barriers. A trench 10, and the depth of the second trench is greater than the thickness of the heavily doped region of the first conductivity type;

18) Use the first ion implantation to introduce the first lateral uniformly distributed impurity region 17 of the second conductivity type into the epitaxial layer below the second trench, and introduce the second conductivity type under the heavily doped region of the first conductivity type The first gradient distribution impurity region 18;

(19) Use the second ion implantation to introduce a second laterally evenly distributed impurity region 19 of the second conductivity type into the epitaxial layer below the second trench, and introduce the second conductivity type under the heavily doped region of the first conductivity type The second gradient distribution impurity region 20;

(20) The third ion implantation is used to introduce the third laterally evenly distributed impurity region 21 of the second conductivity type into the epitaxial layer below the second trench, and the implantation energy used for the third ion implantation is lower than that of the second ion implantation The injection energy used for the injection (see Figure 6);

(21) Heat treatment is used to activate the implanted impurities. The first uniformly distributed impurity region, the second uniformly distributed impurity region, and the third uniformly distributed impurity region form a uniformly doped lateral region 13. The first gradiently distributed impurity region, The second gradient distribution impurity region constitutes the gradient doping region 14, and the lateral uniform doping region and the gradient doping region constitute the second conductivity type non-uniform doping region 12 to separate the first conductivity type heavily doped region, the second The trench and the lower part of the epitaxial layer (see Figure 7);

(22) Forming the third trench 25 in the middle of the second trench by photolithography and dry etching, and controlling the etching time so that the depth of the third trench exceeds the bottom of the non-uniformly doped region of the second conductivity type;

(23) Depositing a Schottky barrier metal layer 26 on the top surface of the entire structure (see FIG. 8 );

(24) Depositing an anode metal layer 1 on the top surface of the entire structure;

(25) After thinning the heavily doped single crystal silicon substrate of the first conductivity type, a cathode metal layer 4 is deposited on the bottom surface to obtain a semiconductor rectifier with a trench gate structure (see Figure 1).

The embodiment described above is only a preferred solution of the present invention, and does not limit the present invention in any form. There are other variations and modifications on the premise of not exceeding the technical solution described in the claims.

Claims (3)

1. a kind of Schottky barrier semiconductor rectifier includes anode metal layer from top to bottom（1）, schottky barrier metal layer （26）, the epitaxial layer that is lightly doped of the first conduction type（2）, the first conduction type heavy doping monocrystalline substrate（3）And cathode gold Belong to layer（4）, the epitaxial layer upper lateral is arranged at intervals with several first grooves（5）, the first groove is interior to be filled with conduction Polysilicon（6）, which is characterized in that the conductive polycrystalline silicon（6）With first groove（5）Inner surface between be equipped with separation layer（7）, The separation layer is equipped with silica grid oxide layer（24）, the silica grid oxide layer thickness is less than separation layer, silica It is upwardly extended at the top of grid oxide layer and is higher than epitaxial layer top surface and form medium wall（8）, the two sides of the medium wall are equipped with first The conductive polycrystalline silicon side wall of conduction type（9）, area between epitaxial layer top and the conductive polycrystalline silicon side wall of medium outer wall Domain forms second groove（10）, it is equipped with positioned at the conductive polycrystalline silicon side wall bottom of medium outer wall above second groove bottom The first conduction type heavily doped region（11）, the epitaxial layer top is equipped with second groove, the first conduction type heavily doped region The the second conduction type non-uniform doping area separated with epitaxial layer（12）, the second conduction type non-uniform doping area includes cross To Uniform Doped area（13）With grade doping area（14）, the grade doping area be located at the top of laterally homogeneous doped region two sides with Silica grid oxide layer contacts to form channel（15）, the epitaxial layer lower part, laterally homogeneous doped region, grade doping area and dioxy Spacer region is equipped between SiClx grid oxide layer（16）, the laterally homogeneous doped region longitudinally has a doping gradient distribution, and described the Third groove is equipped in two grooves（25）, the third groove penetrates the second conduction type non-uniform doping area and extends into extension Layer, the schottky barrier metal layer is covered on the inside of third groove, and contacts to form Schottky barrier with epitaxial layer.

2. a kind of Schottky barrier semiconductor rectifier manufacturing method as described in claim 1, which is characterized in that including following Step：

（One）In the heavy doping monocrystalline substrate of the first conduction type（3）The epitaxial layer that upper one conduction type of growth regulation is lightly doped （2）；

（Two）First groove is formed using photoetching and dry etching in the epitaxial layer（5）；

（Three）In total top layer growth silicon dioxide layer as separation layer（7）；

（Four）On total surface, deposited silicon nitride layer is as mask layer（22）；

（Five）Silica-filled layer is deposited on total surface（23）It is filled first groove；

（Six）Using wet etching selective removal part of silica filled layer, first groove top is exposed；

（Seven）The mask layer that do not protected by silica-filled layer using wet etching selective removal；

（Eight）The separation layer and remaining silica-filled layer that do not protected by mask layer using wet etching selective removal；

（Nine）Remaining mask layer is removed using wet etching；

（Ten）Silica grid oxide layer is grown in total top layer（24）；

（11）In total top layer deposition conductive polycrystalline silicon（6）, conductive polycrystalline silicon is made to fill full first groove；

（12）Using the partially electronically conductive polysilicon of dry etching selective removal, keep conductive polycrystalline silicon top surface and epitaxial layer top surface neat It is flat；

（13）Using dry etching selective removal part of silica grid oxide layer, make the top of the epitaxial layer of first groove two sides Portion is exposed；

（14）Using the partially electronically conductive polysilicon of dry etching selective removal and epitaxial layer, it is higher by silica grid oxide layer outer Prolong layer top surface and forms medium wall（8）；

（15）In total top layer deposition the first conduction type conductive polycrystalline silicon（27）；

（16）Enter the impurity diffusion in the first conduction type conductive polycrystalline silicon at the top of epitaxial layer using heat treatment, forms first Conduction type heavily doped region（11）；

（17）Part the first conduction type conductive polycrystalline silicon and epitaxial layer are removed using dry etching, in the two sides of medium wall Form the conductive polycrystalline silicon side wall of the first conduction type（9）, second groove is formed in the epitaxial layer that no side wall stops（10）, and the The depth of two grooves is greater than the first conduction type heavily doped region thickness；

（18）Introduce the second conduction type in the epitaxial layer below second groove using first time ion implanting first is horizontal To being uniformly distributed impurity range（17）, the first gradient distribution of the second conduction type is introduced below the first conduction type heavily doped region Impurity range（18）；

（19）Introduce the second conduction type in the epitaxial layer below second groove using second of ion implanting second is horizontal To being uniformly distributed impurity range（19）, the second gradient distribution of the second conduction type is introduced below the first conduction type heavily doped region Impurity range（20）；

（20）The third for introducing the second conduction type in the epitaxial layer below second groove using third time ion implanting is horizontal To being uniformly distributed impurity range（21）；

（21）It is the first laterally uniform impurity range, second laterally uniform using the impurity of heat treatment activation injection The laterally uniform impurity range of impurity range, third constitutes laterally homogeneous doped region（13）, first gradient distribution impurity range, the second ladder Degree distribution impurity range constitutes grade doping area（14）, laterally homogeneous doped region and grade doping area the second conduction type of composition are non- Even doped region（12）, to separate the first conduction type heavily doped region, second groove and epitaxial layer lower part；

（22）Using photoetching and it is dry-etched in formation third groove in the middle part of second groove（25）, pass through etch period control System, making third trench depth is more than the second conduction type non-uniform doping area bottom；

（23）In total top surface Schottky barrier metal layer（26）；

（24）In total top surface deposition anode metal layer（1）；

（25）After the monocrystalline substrate of first conduction type heavy doping is thinned, in bottom surface deposition cathode metal layer（4）, i.e., Obtain trench gate structure semiconductor rectifier.

3. Schottky barrier semiconductor rectifier manufacturing method according to claim 2, which is characterized in that step（20） The Implantation Energy that middle third time ion implanting uses is lower than step（19）In second of ion implanting use Implantation Energy.