CN105680869A - Buffer serial circuit based on transient voltage suppression - Google Patents
Buffer serial circuit based on transient voltage suppression Download PDFInfo
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- CN105680869A CN105680869A CN201610061975.4A CN201610061975A CN105680869A CN 105680869 A CN105680869 A CN 105680869A CN 201610061975 A CN201610061975 A CN 201610061975A CN 105680869 A CN105680869 A CN 105680869A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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Abstract
The invention discloses a buffer serial circuit based on transient voltage suppression; the invention relates to the field of signal conversion and aims to solve the technical problems that the existing serializer exists mismatching of clock frequencies collected by different clock generators in the serializer, leads to relatively large output data error and simultaneously has switching loss and the like. The structure mainly comprises a first clock generator, a first multiplexing circuit, a feedback clock generator, a second multiplexing circuit and a reset circuit, wherein the first clock generator outputs a first clock signal and is used for constructing a signal collecting time window; a sampling clock port of the first multiplexing circuit receives the first clock signal output by the first clock generator, the input end receives a parallel source signal, and the output end outputs a mixed signal; and the reset circuit comprises a passive buffer circuit. The buffer serial circuit disclosed by the invention is used for high-speed serialization of the signal.
Description
Technical field
The present invention relates to signal conversion art, it is specifically related to a kind of buffering serial circuit based on transient voltage suppressing.
Background technology
Serial device receive and row data and it is converted to serial data stream; Input signal is generally 8 bit parallel data, and certain encoding scheme usually also can be utilized to convert 8 bit data to 10 bit data when upper Serial output link transmission. The device that unstrings is then a contrary process. It receives serial data, decodes if desired, then is converted to the data of parallel form. The device that unstrings also to be recovered data clock, and clock is forwarded to follow-up element together with data. In SerDes, these 2 complementary elements provide and a kind of convert original parallel data to serial data thus carry out the effective means of high efficiency of transmission; SerDes also has phaselocked loop (PLL) module, its receiving system reference clock, and by its frequency multiplication to corresponding data speed. The serial data that the clock lock using this frequency multiplication to cross is inputted by independent sampler module.
Buffer circuit can be divided into be opened buffer circuit and turns off buffer circuit. Opening buffer circuit utilizes inductance and devices in series to carry out the current-rising-rate of suppression device, utilization be the principle that inductive current can not suddenly change. But opening buffer inductance can have shutoff action to produce to turn off point peak voltage constantly at device, causing device overvoltage, being relatively used less so opening buffer circuit. Turning off the most basic thought of buffer circuit is that the principle utilizing capacitance voltage not suddenly change reduces the change of device transient voltage and suppresses point peak voltage, can also reduce the switch loss of device simultaneously.
Existing serial device, particularly, adopts some optocoupler devices, have impact on operating rate, and current consumption also can rise in unicircuit; And optocoupler serial device is not long for work-ing life, it is easy to cause card; There is clock shake and data dithering; Lack detection check interface.
Summary of the invention
For above-mentioned prior art, the object of the invention is to provide a kind of buffering serial circuit based on transient voltage suppressing, it is intended to solve existing serial device existence collection clock and chooses unreasonable to former data windowed regions, clock producer collection clock requency different in identical serial device is not mated and is caused output data error bigger, there is data serial speed slower simultaneously, the technical problems such as operational efficiency is limited, switch loss.
For achieving the above object, the technical solution used in the present invention is as follows:
Based on a buffering serial circuit for transient voltage suppressing, comprise parallel source signal, also comprise the first clock producer: export the first clocksignal, for building signals collecting time window; First multiplex electronics: its sampling clock port receives the first clocksignal that the first clock producer exports, and input terminus receives parallel source signal and output terminal exports mixed signal; Feedback clock producer: the first clocksignal receiving the first clock producer output is to obtain benchmark clock, and output feedack clocksignal, for building time delay signals collecting time window; 2nd multiplex electronics: its sampling clock port receives the feedback clock signal that feedback clock producer exports, input terminus receives mixed signal and the output terminal output serial signal that the first multiplex electronics exports; 2nd clock producer: export the 2nd clocksignal, recovers signals collecting time window for building; Clock data recovery circuit: there is half numeral inside and outside ring structure, its inner ring road receives the 2nd clocksignal reception serial signal that the 2nd clock producer exports, and exports the parallel signal relative to serial signal half frequency; Described reset circuit, comprise passive snubber circuit, wherein, first diode～the 4th diode, the first inductance, the 2nd inductance, the first electric capacity, the 2nd electric capacity, resistance and triode, wherein, the output terminal contact resistance of the first diode, the output terminal of the 3rd diode, the input terminus of the first diode connects the first electric capacity, and the other end of the first electric capacity connects the input terminus of the 3rd diode and the output terminal of the 4th diode; The other end of resistance connects the first inductance, and the other end of the first inductance connects the input terminus of the 2nd diode and the drain electrode of triode; The output terminal of the 2nd diode connects the 2nd inductance and the 2nd electric capacity, and the other end of the 2nd inductance connects the input terminus of the 4th diode, the emitter-base bandgap grading of the other end connecting triode of the 2nd electric capacity.
In such scheme, the 3rd multiplex electronics: its sampling clock port receives the feedback clock signal that feedback clock producer exports, and input terminus receives high low logic level and output terminal output difference sub-signal. There is bigger loss in feedback clock signal generative process, input signal is clamped down on and difference by the 3rd multiplexed device so that feedback clock signal has higher identification degree for the next circuit, increases device response speed.
In such scheme, described feedback clock producer, comprises phase-detection circuit: receives and compares the first reverse clocksignal and difference signal, exports first and compares signal; Boosting-step-down circuit: receive first and compare signal, export control voltage signal; Reset circuit: output switching signal is to boosting-step-down circuit; Divide frequency circuit: receive the first clocksignal, export the first clocksignal of half frequency; Time delay circuit: receive control voltage signal to adjust the time delay time, and receive the clocksignal of point frequency circuit output, output feedack clocksignal. Phase-detection circuit by the first clocksignal comparison the 3rd multiplex electronics output terminal difference signal of the reversion in a phase place, specifically, by the positive rise of the first clocksignal of reversion and the edge of the difference signal of the 3rd multiplex electronics. The comparison signal exported when phase-detection circuit is logic high level, namely illustrates that the first clocksignal of reversion is not mated with the difference signal of the 3rd multiplex electronics. Control voltage scope can be impacted by the reference time delay of time delay circuit, specifically, reduces the rank time of time delay circuit, reduces time delay time range, it is possible to reduce circuit complexity and electric quantity consumption, and reduces noise and shake further; After shake reduces, it is possible to increasing the acquisition time window that multiplex electronics applies, data can pass through more quickly switching device more.
In such scheme, it may be preferred that described reset circuit, comprises the first comparer: export the 2nd and compare signal;2nd comparer: export the 3rd and compare signal; First or door: receive first and compare signal and the 2nd and compare signal; The first phase inverter connected successively with first or door, the 2nd phase inverter and snubber; 2nd or door: its input terminus is connected with first or the output terminal of door and the output terminal of the 2nd phase inverter; 3rd phase inverter: its input terminus connects the output terminal of the 2nd or door; First triode: base stage connects the output terminal of the 3rd phase inverter, emtting electrode junction circuit height electricity end; 2nd triode: base stage connects the output terminal of the 2nd or door, emtting electrode junction circuit low electricity end; First node is the output terminal of first or door, is connected to time delay circuit; Section Point is the output terminal of snubber, is connected to the output terminal of boosting-step-down circuit; 3rd node is the collector electrode potential end of the first triode, is connected to the 3rd multiplex electronics; 4th node is reference voltage potential point. The control voltage level that the switch signal that reset circuit exports exports based on boosting-step-down circuit. Boosting-step-down circuit has high threshold voltage and low threshold voltage, when control voltage level is lower than low threshold voltage and higher than high threshold voltage, reset circuit closes boosting-step-down circuit, and control voltage level is reset between low threshold voltage and high threshold voltage, specifically, the 50% of voltage of supply is reset to. High threshold voltage scope and low threshold voltage scope are respectively voltage of supply 0 to 30% and 85% to 100%. Reset circuit is to the control of time delay circuit, it is possible to the sampling of the first multiplex electronics is windowed the time by control further, and the system that improves is to the identification of data waveform and judgement speed.
In such scheme, it may be preferred that the 2nd bit rate clock signal is 1/2nd of the first clocksignal. The system clock of clock data recovery circuit is provided.
In such scheme, it may be preferred that described clock data recovery circuit, comprises inner ring road: comprising phaselocked loop, phaselocked loop exports multi-phase clock signal; The outer ring being connected with phaselocked loop: comprising the phase sensitive rectifier forming clock recovery loop, digital filter and phase place interpolation device, serial signal is inputted by phase sensitive rectifier input terminus and multi-phase clock signal is inputted by phase place interpolation device. Serial signal converts the also row data of two to after the clock sampling of half rate, then compares through phase sensitive rectifier and produces phase place discriminative information. Phase place discriminative information gives ratio and the integral element of digital filter simultaneously, finally produces phase control information and gives phase place interpolation device. The parallel signal of half frequency is the sign of serial signal, it is achieved that the feedback of output signal and detection.
Compared with prior art, the useful effect of the present invention is: modulate to control acquisition window width to collection clock by data signal self-feedback, obtains more reasonably parallel signal and turns serial signal self-feedback modulation circuit structure; Data waveform rising time and negative edge time significantly reduce; Promote and the travelling speed of row data conversion serial data, reduce system loss and waveform shake; Utilize and turn off buffer circuit principle, to realize the control to the change of device transient voltage and the suppression of sharp peak voltage close to passive energy expenditure, it is to increase the capacity usage ratio of device.
Accompanying drawing explanation
Fig. 1 is model calling relation schematic diagram of the present invention;
Fig. 2 is that the present invention resets the embodiment of circuit;
Fig. 3 is the embodiment of time delay circuit of the present invention;
Fig. 4 is the embodiment of passive snubber circuit of the present invention.
Embodiment
All features disclosed in this specification sheets, or the step in disclosed all methods or process, except mutually exclusive feature, beyond step, all can combine by any way.
Below in conjunction with accompanying drawing, the present invention will be further described:
Fig. 1 is model calling relation schematic diagram of the present invention, a kind of buffering serial circuit based on transient voltage suppressing, first clock producer and the 2nd clock producer, it is contemplated that concrete implementation environment, can use the standard pulse output terminal of treater in electronic system to replace. In signal conversion operation process, the first clocksignal and serial signal are locked in the equivalent delay locked loop of feedback clock producer, and during serial signal, clock rate is the half of the first clock signal clock speed of the first clock signal clock speed or reversion.
Embodiment 1
Fig. 2 is that the present invention resets the embodiment of circuit, and in the present embodiment, phase inverter U4 and phase inverter U5 is the simplest time delay device, and described time delay circuit can be selected to replace phase inverter U4 and phase inverter U5 to obtain better function of initializing. After replacement, 4th node is reference voltage input node, its size depends on the comparer selected and the threshold voltage of the required setting of comparer, or door U3 based on the comparison device U1 and comparer U2 export the 2nd compare signal, the 3rd and compare signal, generate the first control signal, or the first control signal that door U3 exports is sent to first node. Time delay circuit is by the first control signal time delay, and the reference voltage of the 4th node input is depended in time delay interval, and specifically, the time delay time depends on that the size of the reference voltage difference of the 4th node input and reference voltage difference are loaded into the time used in the first control signal.
Embodiment 2
Fig. 3 is the embodiment of time delay circuit of the present invention, the snubber U9-U12 of series connection, and classification time is access in tunable capacitor C1-C3; 5th node and the 7th node are input node, and the 6th node is for exporting node; 7th node access boosting-step-down circuit, the capacitance of boosting-step-down control circui tunable capacitor, snubber U9-U12 produces phase delay.
Embodiment 3
Described boosting-step-down circuit, i.e. BOOST circuit, can use spatial volume situation shared by circuit to carry out reducing replacement according to reality; As, when needing less circuit space volume, it is possible to change and elect electric charge pump as. Electric charge pump, its energy storage device can be electric capacity, and output terminal is multiple series connection and the collector and emitter of the complementary triode of raceway groove about output terminal symmetry, and input terminus is the base stage of multiple triode, the logic realized as required adds certain logical gate in base stage, it is achieved electric charge pump; Relative to BOOST circuit, electric charge pump cloth plate bulk is relatively little, and circuit structure does not need inductance, and response speed is extremely fast.
Embodiment 4
Fig. 4 is the embodiment of passive snubber circuit of the present invention, described passive snubber circuit, in the inner circuit of the described snubber U9-U12 mentioned before being specifically employed to; Specifically, by electric capacity C3, C4, diode and inductance L 1, L2 composition. Between the device VT off period, electric capacity C4 is charged to voltage of supply Ud, and owing to load current is through afterflow, the voltage on C3 is zero. When device VT opens, the energy storage in C4, through L2, VD and C3 electric discharge, is turned and is stored in C3 and L4 by electric capacity C4. When to discharge into voltage be zero to C4, due to the existence of diode, the energy storage in L2 continues to transfer in C3, and the discharge loop of L2 is VD1, C3.When current damping to zero in L2, the energy storage on electric capacity C4 is all transferred on electric capacity C3. When device VT turns off again, load voltage is from, the process of Ud vanishing, C3, by VD1, R1 and L1 electric discharge, makes the energy storage of C3 be sent to load, until C3 voltage is zero.
The above; it is only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any belongs to those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.
Claims (3)
1., based on a buffering serial circuit for transient voltage suppressing, comprise parallel source signal, it is characterised in that, also comprise
First clock producer: export the first clocksignal, for building signals collecting time window;
First multiplex electronics: its sampling clock port receives the first clocksignal that the first clock producer exports, and input terminus receives parallel source signal and output terminal exports mixed signal;
Feedback clock producer: comprising reset circuit, the first clocksignal receiving the first clock producer output is to obtain benchmark clock, and output feedack clocksignal, for building time delay signals collecting time window;
2nd multiplex electronics: its sampling clock port receives the feedback clock signal that feedback clock producer exports, input terminus receives mixed signal and the output terminal output serial signal that the first multiplex electronics exports;
Described reset circuit, comprise passive snubber circuit, wherein, first diode～the 4th diode, the first inductance, the 2nd inductance, the first electric capacity, the 2nd electric capacity, resistance and triode, wherein, the output terminal contact resistance of the first diode, the output terminal of the 3rd diode, the input terminus of the first diode connects the first electric capacity, and the other end of the first electric capacity connects the input terminus of the 3rd diode and the output terminal of the 4th diode; The other end of resistance connects the first inductance, and the other end of the first inductance connects the input terminus of the 2nd diode and the drain electrode of triode; The output terminal of the 2nd diode connects the 2nd inductance and the 2nd electric capacity, and the other end of the 2nd inductance connects the input terminus of the 4th diode, the emitter-base bandgap grading of the other end connecting triode of the 2nd electric capacity.
2. a kind of buffering serial circuit based on transient voltage suppressing according to claim 1, it is characterised in that, also comprise
3rd multiplex electronics: its sampling clock port receives the feedback clock signal that feedback clock producer exports, and input terminus receives high low logic level and output terminal output difference sub-signal.
3. a kind of buffering serial circuit based on transient voltage suppressing according to claim 1, it is characterised in that, described feedback clock producer, comprises
Phase-detection circuit: receive and compare the first reverse clocksignal and difference signal, exports first and compares signal;
Boosting-step-down circuit: receive first and compare signal, export control voltage signal;
Reset circuit: output switching signal is to boosting-step-down circuit;
Divide frequency circuit: receive the first clocksignal, export the first clocksignal of half frequency;
Time delay circuit: receive control voltage signal to adjust the time delay time, and receive the clocksignal of point frequency circuit output, output feedack clocksignal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610061975.4A CN105680869A (en) | 2016-01-29 | 2016-01-29 | Buffer serial circuit based on transient voltage suppression |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610061975.4A CN105680869A (en) | 2016-01-29 | 2016-01-29 | Buffer serial circuit based on transient voltage suppression |
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| CN105680869A true CN105680869A (en) | 2016-06-15 |
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| CN201610061975.4A Pending CN105680869A (en) | 2016-01-29 | 2016-01-29 | Buffer serial circuit based on transient voltage suppression |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111726105A (en) * | 2019-03-19 | 2020-09-29 | 美光科技公司 | Signal conditioning apparatus |
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