CN105634454B - A kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA - Google Patents

Abstract

A single-event hardened power-on reset circuit suitable for SRAM FPGAs used in aerospace, which includes a power supply VCC, three identical power-on redundant modules, error detection and redundant output control modules, and three controllable output buffers The error detection and redundant output control module can detect the faulty power-on redundant module, and reset the power-on redundant module to clear the accumulation of single event effects; the error detection and redundant output control module can control the controllable The output buffer cuts off the output of the faulty power-on redundancy module to ensure the correct output of the power-on reset circuit. The power-on reset circuit clears the error accumulation phenomenon caused by the single event reversal effect, and at the same time controls the output of the module, eliminates the influence of the single event effect on the output, and achieves a significant ability to resist the single event effect.

Description

A single-event hardened power-on-reset circuit suitable for SRAM-type FPGAs used in aerospace

technical field

The invention relates to a single-event reinforced power-on reset circuit suitable for SRAM type FPGA used in aerospace, and belongs to the field of anti-single-event effect reinforced integrated circuits.

Background technique

The SRAM type FPGA chip needs a power-on reset process when starting. The power-on reset circuit gives a reset signal when the FPGA chip is started, and keeps a valid level. After the power supply voltage rises to a level where other circuits can work normally, the reset signal is changed, and other circuits on the chip are started. After success, maintain a stable state and make the chip work normally. When the existing power-on reset circuit is used in SRAM FPGA for aerospace, it will face serious reliability problems: the power-on reset circuit will generate single event upset (SEU) and single event transient (SET) in the harsh environment of space. single event effects. When single event upset (SEU) and single event transient (SET) occur in the power-on reset circuit, a wrong power-on reset signal will be generated, resulting in power-off of the chip and loss of user functions, seriously affecting the reliability of aerospace SRAM FPGAs , with the progress of the technology, the sensitivity of the SRAM FPGA chip to the single event effect is increasing, which puts forward higher requirements for the reliability of the power-on reset circuit. At the same time, the reinforced SRAM FPGA for aerospace contains a variety of storage units. These storage units adopt different reinforcement measures due to different radiation resistance requirements, resulting in different voltages and different clearing times for these storage units to work normally. , the existing power-on reset circuit is difficult to guarantee a reasonable reset pulse width, especially as the process size shrinks, the deviation of different types of memory cells continues to increase, and higher requirements are placed on the correctness of the reset pulse width.

Contents of the invention

The technical problem solved by the present invention is: to overcome the deficiencies in the prior art, to provide a single-event-reinforced power-on reset circuit suitable for aerospace SRAM-type FPGAs, and to control the errors of single-event effects through error detection and redundant output control modules. The output of the power-on redundant module is turned off, so that the final power-on reset output remains correct; a delay deburring circuit with a reset input is used to remove the transient fluctuations of the level monitoring module due to power fluctuations and single event effects, and at the same time When the power-on redundant module makes an error, the delay deburring circuit is reset through the output of the error detection and redundant output control module; a digital auxiliary delay module with a reset input is adopted, and when the power-on redundant module makes an error At the same time, the digital auxiliary delay module is reset and cleared through the error detection and the output of the redundant output control module, and the cumulative effect of the single event reversal is cleared, so that it returns to the correct state, thereby realizing the anti-single event reversal effect and anti-single event reversal. Particle transient effect capability; through the internal storage unit state monitoring module, the minimum time required for a complete read and write operation of the hardened storage unit in the FPGA is monitored, ensuring that the reset pulse width can meet the correct reset of all the hardened storage units by the FPGA.

The technical solution solved by the present invention is: a single particle reinforced power-on reset circuit suitable for aerospace SRAM type FPGA, including power supply VCC, three identical power-on redundant modules, error detection and redundant output control modules and Three controllable output buffers; three identical power-on redundant modules, namely the first power-on redundant module, the second power-on redundant module, and the third power-on redundant module; three controllable output buffers The devices are respectively the first controllable output buffer, the second controllable output buffer, and the third controllable output buffer;

Each power-on redundant module includes a level monitoring module, a delay deburring circuit, an internal storage unit status monitoring module, and a digital auxiliary delay module;

The power supply supplies power to the level monitoring module, and the level monitoring module detects the voltage value of the power supply in real time. When the voltage value of the power supply is greater than or equal to the set upper threshold voltage Vthr, the level monitoring module outputs a high level signal and sends it to the delay In the glitch circuit, the high level signal ends the reset signal. When the voltage value of the power supply is lower than the set upper threshold voltage Vthr, the level monitoring module outputs a low level signal and sends it to the delay deburring circuit;

The delay deburring circuit receives the high-level signal or low-level signal sent by the level monitoring module, and judges that when the feedback from the error detection and redundant output control module is a high-level signal, at the same time when it receives the high-level signal from the level monitoring module When the single pulse width of the high-level signal or low-level signal is less than or equal to the set pulse width, the single pulse is filtered out as a glitch, and a smooth high-level signal or a smooth low-level signal is sent to the internal storage Unit state monitoring module; when judging that the feedback from the error detection and redundant output control module is a low-level signal, when the pulse in the low-level signal fed back by the error detection and redundant output control module is less than or equal to the set pulse width, The single pulse is filtered out as a glitch, and the smooth low-level signal is sent to the internal storage unit status monitoring module;

An internal storage unit status monitoring module, including multiple storage units;

The internal storage unit status monitoring module, when receiving the smooth low-level signal sent by the delay deburring circuit, locks multiple storage units in the internal storage unit status monitoring module, that is, stops writing data to the storage unit, and at the same time Output high-level signals to the digital auxiliary delay module; the internal storage unit status monitoring module, when receiving the smooth high-level signal sent by the delay deburring circuit, writes to multiple storage units in the internal storage unit status monitoring module Enter the value opposite to the value stored in the storage unit, and then lock multiple storage units, that is, stop writing data to the storage unit, and output a low level signal to the digital auxiliary delay module at the same time;

The digital auxiliary delay module includes multiple registers and an oscillator;

The digital auxiliary delay module receives the high-level signal or low-level signal sent by the internal storage unit status monitoring module, and when the high-level signal is received from the internal storage unit status monitoring module, the error detection and redundant output control module When the feedback is high level, multiple registers in the digital auxiliary delay module are locked, that is, the value stored in the register remains unchanged, and a low level signal is output, that is, the output of the digital auxiliary delay module is a low level signal;

When a high level signal is received from the internal storage unit status monitoring module and the feedback from the error detection and redundant output control module is low level, or when a low level signal is received from the internal storage unit status monitoring module and the error detection And when the feedback from the redundant output control module is high level, or when a low level signal is received from the internal storage unit status monitoring module and the feedback from the error detection and redundant output control module is low level, the oscillator starts to oscillate and output The clock signal, the register counts once after each oscillation, and when the register is full, it outputs a high level, that is, the output of the digital auxiliary delay module is a high level signal;

The output of the first power-on redundant module is recorded as POR_Good1 signal, the second power-on redundant module POR_Good2 signal, the third power-on redundant module POR_Good3 signal; the output of the first power-on redundant module is recorded as POR_Good1 signal, Both the POR_Good2 signal of the second power-on redundant module and the POR_Good3 signal of the third power-on redundant module are sent to the error detection and redundant output control module; the output of the first power-on redundant module is recorded as the POR_Good1 signal and sent to the first control output buffer; record the output of the second power-on redundant module as POR_Good2 signal and send it to the second controllable output buffer; record the output of the third power-on redundant module as POR_Good3 signal and send it to the third controllable output buffer;

The error detection and redundant output control module has three inputs and three outputs, the three outputs are OUT1, OUT2 and OUT3, and the output of OUT1 is fed back to the delay deburring circuit of the first power-on redundant module and the digital auxiliary delay module And sent to the first controllable output buffer, the output of OUT2 is fed back to the delay and deburring circuit of the second power-on redundant module, and the digital auxiliary delay module is sent to the second controllable output buffer, and the output of OUT3 is fed back to the second The delay deburring circuit of the three-power-on redundant module and the digital auxiliary delay module are sent to the third controllable output buffer;

The three inputs of the error detection and redundant output control module compare the received POR_Good1 signal, POR_Good2 signal, and POR_Good3 signal respectively. If the POR_Good1 signal, POR_Good2 signal, and POR_Good3 signal are all the same, the three inputs of the error detection and redundant output control module Each output OUT1, OUT2 and OUT3 are high level; if POR_Good1 signal is different from POR_Good2 signal and POR_Good3 signal, then OUT1 is low level, OUT2 and OUT3 are high level; if POR_Good2 signal is different from POR_Good1 signal and POR_Good3 signal, Then OUT2 is low level, OUT1 and OUT3 are high level; if the POR_Good3 signal is different from the POR_Good1 signal and POR_Good2 signal, then OUT3 is low level, and OUT1 and OUT2 are high level;

When the first controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good1 signal of the first power-on redundant module after inversion; when the first controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the first controllable output buffer does not output the signal;

When the second controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good2 signal of the second power-on redundant module after inversion; when the second controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the second controllable output buffer does not output the signal;

When the third controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good3 signal of the third power-on redundant module after inversion; when the third controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the third controllable output buffer does not output the signal.

The level monitoring module includes: PMOS transistor M2, PMOS transistor M3, PMOS transistor M5, PMOS transistor M5, NMOS transistor M1, NMOS transistor M4, NMOS transistor M7, capacitor C1, capacitor C2, and an inverter;

The gate of the PMOS transistor M2 is grounded, the source of the PMOS transistor M2 is connected to the power supply VCC, and the drain of the PMOS transistor M2 is simultaneously connected to the gate of the NMOS transistor M1, one end of the drain capacitor C1, and the gate of the PMOS transistor M3; the NMOS transistor M1 The source of the ground;

The other end of the capacitor C1 is connected to the power supply VCC, the gate of the NMOS transistor M4 is connected to the power supply VCC, the source of the PMOS transistor M3 is connected to the power supply VCC, the drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M4, one end of the capacitor C2, and the PMOS transistor The drain of M5, the gate of PMOS transistor M6, and the gate of NMOS transistor M7; the source of NMOS transistor M4 is grounded; the other end of capacitor C2 is grounded; the source of PMOS transistor M5 is connected to the power supply VCC, and the gate of PMOS transistor M5 Connect the drain of the PMOS transistor M6 to the drain of the NMOS transistor M7 and the input terminal of the inverter; the source of the PMOS transistor M6 is connected to the power supply VCC; the source of the NMOS transistor M7 is grounded; the output terminal VCC_Good of the inverter is used as the level Monitor the output of the module.

The delay deburring circuit includes: AND gate AND31, inverter INV31, inverter INV32, inverter INV33, inverter INV34, capacitor C31, capacitor C32, capacitor C33 and NAND gate NAND31;

One input terminal of the AND gate AND31 is VCC_Good connected to the output VCC_Good of the level monitoring module, and the other input terminal is connected to the output of the error detection and redundant output control module ER_RST, wherein the delay deburring circuit of the first power-on redundant module Connect the output OUT1 of the error detection and redundant output control module, the delay deburring circuit of the second power-on redundant module, connect the output OUT2 of the error detection and redundant output control module, and the delay of the third power-on redundant module The deburring circuit is connected to the output OUT3 of the error detection and redundant output control module; the output terminal of the AND gate AND31 is connected to the input terminal of the inverter INV31, and simultaneously connected to an input terminal of the NAND gate NAND31 and one end of the capacitor C31; the output terminal of the capacitor C31 The other end is connected to the power supply VCC; the output end of the inverter INV31 is connected to one end of the capacitor C32 and the input end of the inverter INV32; the other end of the capacitor C32 is grounded; the output end of the inverter INV32 is connected to the input of the inverter INV33 end; the output end of the inverter INV33 is connected to the input end of the inverter INV34; the output end of the inverter INV34 is connected to one end of the capacitor C33 while connecting the other input end of the NAND gate NAND31; the other end of the capacitor C33 is connected to Power supply VCC; the output terminal Power_Good of the NAND gate NAND31 is used as the output of the delay deburring circuit.

The internal storage unit status monitoring module includes: inverter INV41, inverter INV42, ..., inverter INV4n, storage unit SRAM41, storage unit SRAM42, ..., storage unit SRAM4n, NMOS tube M41, NMOS tube M42 ,..., NMOS tube M4n, OR gate OR4n;

The input end of the inverter INV41 is connected to the output end Power_Good of the delay deburring circuit, and simultaneously connected to the input end of the inverter INV42, the input end of the inverter INV4n, the R input end of the storage unit SRAM41, and the R input end of the storage unit SRAM42. R input terminal, the R input terminal of the storage unit SRAM4n, the grid of the NMOS transistor M41, the grid of the NMOS transistor M42, and the grid of the NMOS transistor M4n; the output terminal of the inverter INV41 is connected to the RN input terminal of the storage unit SRAM41; The output end of the inverter INV42 is connected to the RN input end of the storage unit SRAM42; the output end of the inverter INV4n is connected to the RN input end of the storage unit SRAM4n; the Z output end of the storage unit SRAM41 is connected to the first input of the OR gate OR4n end; the ZN output end of the storage unit SRAM41 is connected to the drain of the NMOS transistor M41; the Z output end of the storage unit SRAM42 is connected to the second input end of the OR gate OR4n; the ZN output end of the storage unit SRAM42 is connected to the drain of the NMOS transistor M42 The Z output terminal of the storage unit SRAM4n is connected to the nth input terminal of the OR gate OR4n; the ZN output terminal of the storage unit SRAM4n is connected to the drain of the NMOS transistor M4n; the source of the NMOS transistor M41 is grounded; the source of the NMOS transistor M42 ground; the source of the NMOS tube M4n is grounded; the POR_Latch output of the OR gate OR4n is connected to the WL of the storage unit SRAM41, the WL input of the storage unit SRAM42, and the WL input of the storage unit SRAM4n, and at the same time as the internal storage unit status monitoring module output.

The digital auxiliary delay module includes: AND gate AND51, oscillator OSC, register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, register FF59;

One input terminal of AND gate AND51 is the output of ER_RST connection error detection and redundant output control module, wherein the delay deburring circuit of the first power-on redundant module is connected with output OUT1 of the error detection and redundant output control module, the second The delay deburring circuit connection error detection of the power-on redundant module and the output OUT2 of the redundant output control module are connected, and the delay deburring circuit connection error detection of the third power-on redundant module is connected to the output OUT3 of the redundant output control module ; The output terminal of the AND gate AND51 is connected to the R input terminal of the register register FF51, and is connected to the control input terminal of the oscillator OSC at the same time; the R input terminal of the register FF52 is POR_Latch, which accepts the output POR_Latch of the internal storage unit status monitoring module, and is connected to the register FF53 at the same time The R input terminal of register FF54, the R input terminal of register FF55, the R input terminal of register FF56, the R input terminal of register FF57, the R input terminal of register FF58, the R input terminal of register FF59; the oscillator OSC The output terminal of register FF51 is connected to the clock input terminal of register FF51; the QN output terminal of register FF51 is connected to the D input terminal of register FF51; the Q output terminal of register FF51 is connected to the clock input terminal of register FF52; the QN output terminal of register FF52 is connected to the register FF52 D input; the Q output of register FF51 is connected to the clock input of register FF53; the QN output of register FF53 is connected to the D input of register FF53; the Q output of register FF53 is connected to the clock input of register FF54; the QN of register FF54 The output terminal is connected to the D input terminal of register FF54; the Q output terminal of register FF54 is connected to the clock input terminal of register FF55; the QN output terminal of register FF55 is connected to the D input terminal of register FF55; the Q output terminal of register FF55 is connected to the clock input terminal of register FF56 terminal; the QN output terminal of register FF56 is connected to the D input terminal of register FF56; the Q output terminal of register FF56 is connected to the clock input terminal of register FF57; the QN output terminal of register FF57 is connected to the D input terminal of register FF57; the Q output terminal of register FF57 Connect the clock input terminal of register FF58; the QN output terminal of register FF58 is connected to the D input terminal of register FF58; the Q output terminal of register FF58 is connected to the clock input terminal of register FF59; the D input terminal of register FF59 is connected to the power supply VCC; The Q output terminal is connected to the other input terminal of the AND gate AND51 and at the same time serves as the output POR_Good of the digital auxiliary delay module.

The error detection and redundant output control module includes: XOR gate XOR61, XOR gate XOR62, XOR gate XOR63, NAND gate NAND61, NAND gate NAND62, NAND gate NAND63;

An input terminal POR_Good1 of the exclusive OR gate XOR61 is connected to the output of the digital auxiliary delay module of the first power-on redundant module, and is connected to an input terminal of the exclusive OR gate XOR62 at the same time; the other input terminal POR_Good2 of the exclusive OR gate XOR62 is connected to the second The output of the digital auxiliary delay module of the power-on redundant module is connected to an input terminal of the exclusive OR gate XOR63 at the same time; the other input terminal POR_Good3 of the exclusive OR gate XOR63 is connected to the digital auxiliary delay module of the third power-on redundant module Output, connect another input end of XOR gate XOR61 at the same time; The output end of XOR gate XOR61 connects an input end of NAND gate NAND61 and connects an input end of NAND gate NAND63 at the same time; The output end of XOR gate XOR62 connects and One input end of the NOT gate NAND62 is connected with the other input end of the NAND gate NAND61 simultaneously; The output end of the XOR gate XOR63 is connected with the other input end of the NAND gate NAND63 while connecting the other input end of the NAND gate NAND62; The output terminal of the gate NAND61 is used as the output terminal OUT1 of the error detection and redundant output control module; the output terminal of the NAND gate NAND62 is used as the output terminal OUT2 of the error detection and redundant output control module; the output terminal of the NAND gate NAND63 is used as the error detection And the output terminal OUT3 of the redundant output control module.

The NMOS transistor M1 in the level monitoring module is a large-scale device, and the width-to-length ratio of the large-size device is 10; the PMOS transistor M2 is an inverse ratio transistor, and the width-to-length ratio of the inverse ratio transistor is 1/10; the width and length of the NMOS transistor M1 is The ratio is 100 times the width-to-length ratio of the PMOS tube M2; the PMOS tube is a large-size device of M3, and the width-to-length ratio of the large-size device is 10; the NMOS tube M4 is an inverted tube, and the width-to-length ratio of the inverted tube is 1/20; The width-to-length ratio of the PMOS transistor M3 is 200 times that of the NMOS transistor M4.

The advantage of the present invention compared with prior art is:

(1) The present invention uses an error detection and redundant output control module to detect the output of three power-on redundant modules, and closes the output of the power-on redundant module that causes an output error due to a single event effect, so as to ensure the final power-on reset output Correct, at the same time, clear and reset the sub-circuit to make it return to the correct state, and clear the accumulation of single event upset, so as to realize the anti-single event upset effect and anti-single event transient effect ability.

(2) The present invention realizes level monitoring by using 4 PMOS transistors, 3 NMOS transistors and two capacitors. Compared with traditional level monitoring, the present invention uses fewer delay units and makes the overall area smaller.

(3) The present invention adopts a time-delay deburring circuit with a reset input terminal, and when the single event effect occurs in the power-on redundant module, the output of the error detection and redundant output control module can be conducted to the internal storage unit state monitoring module .

(4) The internal storage unit state monitoring module ensures that the level meets the requirements of various storage units, and ensures that various storage units can be reset correctly.

(5) the present invention adopts the digital auxiliary time-delay module that has the reset input end, when single event effect occurs in this power-on redundant module, can reset the digital auxiliary time-delay module by the output of error detection and redundant output control module, clear Effects of single event upsets that have occurred, avoiding their accumulation.

(6) The error detection and redundant output control module of the present invention can detect the error of any one of the three paths through three XOR gates and three AND gates, and cut off the output of the path and reset the path through the output .

(7) In the level monitoring module of the present invention, the PMOS tube M2 is an inverse tube with a width-to-length ratio of 1/10, and the NMOS tube M4 is an inverse tube with a width-to-length ratio of 1/20, so that the PMOS tube M1 and the NMOS tube The leakage in the subthreshold region of the tube M4 is very small, which reduces the power consumption of the entire module; the width-to-length ratio of the NMOS tube M1 is 100 times that of the PMOS tube M2, so that when the power supply VCC is greater than the turn-on threshold of the NMOS tube and the turn-on threshold of the PMOS tube, The voltage of node NOD1 is close to the turn-on threshold of the NMOS transistor; the width-to-length ratio of the PMOS transistor M3 is 200 times the width-to-length ratio of the NMOS transistor M4, so that when the power supply VCC is equal to the sum of the turn-on threshold of the NMOS transistor and the turn-on threshold of the PMOS transistor, the node NOD2 The voltage can be instantly pulled up to the voltage value of the power supply VCC by M3.

Description of drawings

Fig. 1 is the overall block diagram of the power-on reset circuit of the present invention;

Fig. 2 is a circuit diagram of the level monitoring module of the present invention;

Fig. 3 is the delay deburring circuit diagram of the present invention;

Fig. 4 internal storage unit state monitoring module circuit diagram of the present invention;

Fig. 5 digital auxiliary delay module circuit diagram of the present invention;

Fig. 6 is the circuit diagram of error detection and redundant output control module of the present invention;

FIG. 7 is a comparison diagram of the single event experimental results of the power-on reset circuit of the present invention and the original single event experimental results of the power-on reset circuit.

Detailed ways

The basic idea of the present invention is: a single particle reinforced power-on reset circuit suitable for aerospace SRAM type FPGA, which internally includes a power supply VCC, three identical power-on redundant modules, error detection and redundant output control modules And three controllable output buffers, the error detection and redundant output control module can detect the faulty power-on redundant module, and reset the power-on redundant module to clear the accumulation of single event effects; error detection and redundancy The output control module can control the controllable output buffer to cut off the output of the faulty power-on redundant module, so as to ensure the correct output of the power-on reset circuit. The power-on reset circuit clears the error accumulation phenomenon caused by the single event reversal effect, and at the same time controls the output of the module, eliminates the influence of the single event effect on the output, and achieves a significant ability to resist the single event effect.

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 1, the present invention proposes an anti-single event hardened power-on reset circuit suitable for aerospace SRAM FPGAs, its structure is shown in Figure 2, and it is characterized in that it includes: a power supply VCC, three identical upper An electrical redundancy module, an error detection and redundant output control module, and three controllable output buffers; three identical electrical redundancy modules are respectively the first electrical redundancy module, the second electrical redundancy module, The third power-on redundant module; the three controllable output buffers are respectively the first controllable output buffer, the second controllable output buffer, and the third controllable output buffer;

Each power-on redundant module includes a level monitoring module, a delay deburring circuit, an internal storage unit status monitoring module, and a digital auxiliary delay module;

The power supply supplies power to the level monitoring module, and the level monitoring module detects the voltage value of the power supply in real time. When the voltage value of the power supply is greater than or equal to the set upper threshold voltage Vthr, the level monitoring module outputs a high level signal and sends it to the delay In the glitch circuit, the high level signal ends the reset signal. When the voltage value of the power supply is lower than the set upper threshold voltage Vthr, the level monitoring module outputs a low level signal and sends it to the delay deburring circuit;

The delay deburring circuit receives the high-level signal or low-level signal sent by the level monitoring module, and judges that when the feedback from the error detection and redundant output control module is a high-level signal, at the same time when it receives the high-level signal from the level monitoring module When the single pulse width of the high-level signal or low-level signal is less than or equal to the set pulse width, the single pulse is filtered out as a glitch, and a smooth high-level signal or a smooth low-level signal is sent to the internal storage Unit state monitoring module; when judging that the feedback from the error detection and redundant output control module is a low-level signal, when the pulse in the low-level signal fed back by the error detection and redundant output control module is less than or equal to the set pulse width, The single pulse is filtered out as a glitch, and the smooth low-level signal is sent to the internal storage unit status monitoring module;

An internal storage unit status monitoring module, including multiple storage units;

The internal storage unit status monitoring module, when receiving the smooth low-level signal sent by the delay deburring circuit, locks multiple storage units in the internal storage unit status monitoring module, that is, stops writing data to the storage unit, and at the same time Output high-level signals to the digital auxiliary delay module; the internal storage unit status monitoring module, when receiving the smooth high-level signal sent by the delay deburring circuit, writes to multiple storage units in the internal storage unit status monitoring module Enter the value opposite to the value stored in the storage unit, and then lock multiple storage units, that is, stop writing data to the storage unit, and output a low level signal to the digital auxiliary delay module at the same time;

The digital auxiliary delay module includes multiple registers and an oscillator;

The digital auxiliary delay module receives the high-level signal or low-level signal sent by the internal storage unit status monitoring module, and when the high-level signal is received from the internal storage unit status monitoring module, the error detection and redundant output control module When the feedback is high level, multiple registers in the digital auxiliary delay module are locked, that is, the value stored in the register remains unchanged, and a low level signal is output, that is, the output of the digital auxiliary delay module is a low level signal;

When a high level signal is received from the internal storage unit status monitoring module and the feedback from the error detection and redundant output control module is low level, or when a low level signal is received from the internal storage unit status monitoring module and the error detection And when the feedback from the redundant output control module is high level, or when a low level signal is received from the internal storage unit status monitoring module and the feedback from the error detection and redundant output control module is low level, the oscillator starts to oscillate and output The clock signal, the register counts once after each oscillation, and when the register is full, it outputs a high level, that is, the output of the digital auxiliary delay module is a high level signal;

The output of the first power-on redundant module is recorded as POR_Good1 signal, the second power-on redundant module POR_Good2 signal, the third power-on redundant module POR_Good3 signal; the output of the first power-on redundant module is recorded as POR_Good1 signal, Both the POR_Good2 signal of the second power-on redundant module and the POR_Good3 signal of the third power-on redundant module are sent to the error detection and redundant output control module; the output of the first power-on redundant module is recorded as the POR_Good1 signal and sent to the first control output buffer; record the output of the second power-on redundant module as POR_Good2 signal and send it to the second controllable output buffer; record the output of the third power-on redundant module as POR_Good3 signal and send it to the third controllable output buffer;

The error detection and redundant output control module has three inputs and three outputs, the three outputs are OUT1, OUT2 and OUT3, and the output of OUT1 is fed back to the delay deburring circuit of the first power-on redundant module and the digital auxiliary delay module And sent to the first controllable output buffer, the output of OUT2 is fed back to the delay and deburring circuit of the second power-on redundant module, and the digital auxiliary delay module is sent to the second controllable output buffer, and the output of OUT3 is fed back to the second The delay deburring circuit of the three-power-on redundant module and the digital auxiliary delay module are sent to the third controllable output buffer;

The three inputs of the error detection and redundant output control module compare the received POR_Good1 signal, POR_Good2 signal, and POR_Good3 signal respectively. If the POR_Good1 signal, POR_Good2 signal, and POR_Good3 signal are all the same, the three inputs of the error detection and redundant output control module Each output OUT1, OUT2 and OUT3 are high level; if POR_Good1 signal is different from POR_Good2 signal and POR_Good3 signal, then OUT1 is low level, OUT2 and OUT3 are high level; if POR_Good2 signal is different from POR_Good1 signal and POR_Good3 signal, Then OUT2 is low level, OUT1 and OUT3 are high level; if the POR_Good3 signal is different from the POR_Good1 signal and POR_Good2 signal, then OUT3 is low level, and OUT1 and OUT2 are high level;

When the first controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good1 signal of the first power-on redundant module after inversion; when the first controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the first controllable output buffer does not output the signal;

When the second controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good2 signal of the second power-on redundant module after inversion; when the second controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the second controllable output buffer does not output the signal;

When the third controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good3 signal of the third power-on redundant module after inversion; when the third controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the third controllable output buffer does not output the signal.

The invention adopts the error detection and redundant output control module to detect the output of three power-on redundant modules. When the space particle hits the power-on reset circuit, if the space particle hits the level monitoring module of a power-on redundant module, the output of the level detection module will generate a current pulse, and this current pulse is transmitted to the delay deburring When the circuit is connected, the current pulse will be removed by the delay deburring circuit as a burr, and will not continue to be transmitted to the next stage; when the space particles hit the internal storage unit status monitoring module or the storage unit or register in the digital auxiliary delay module These storage units or registers may be flipped over time, and finally the power-on redundant module generates an erroneous output. The error detection and redundant output control module can detect the power-on redundant module, and then pass the single-event effect The output of the power-on redundant module that causes an output error is turned off to ensure that the output of the final power-on reset is correct, and at the same time, the sub-circuit is cleared and reset to make it return to the correct state, clearing the accumulation of single event flips, so as to achieve anti-single event flips effects and immunity to single event transient effects.

The level monitoring module of the present invention is shown in Figure 2, including: PMOS tube M2, PMOS tube M3, PMOS tube M5, PMOS tube M6, NMOS tube M1, NMOS tube M4, NMOS tube M7, capacitor C1, capacitor C2 , Inverter; the gate of the PMOS transistor M2 is grounded, the source of the PMOS transistor M2 is connected to the power supply VCC, the drain of the PMOS transistor M2 is simultaneously connected to the gate of the NMOS transistor M1 and one end of the drain capacitor C1, and the gate of the PMOS transistor M3 The source of the NMOS transistor M1 is grounded; the other end of the capacitor C1 is connected to the power supply VCC, the gate of the NMOS transistor M4 is connected to the power supply VCC, the source of the PMOS transistor M3 is connected to the power supply VCC, and the drain of the PMOS transistor M3 is connected to the NMOS transistor M4. The drain, one end of capacitor C2, the drain of PMOS transistor M5, the gate of PMOS transistor M6, the gate of NMOS transistor M7; the source of NMOS transistor M4 is grounded; the other end of capacitor C2 is grounded; the source of PMOS transistor M5 Connect to the power supply VCC, the gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M6 and the drain of the NMOS transistor M7, and the input terminal of the inverter; the source of the PMOS transistor M6 is connected to the power supply VCC; the source of the NMOS transistor M7 is grounded; The output terminal VCC_Good of the inverter is used as the output of the level monitoring module. It only uses 4 PMOS tubes, 3 NMOS tubes and two capacitors to realize the level monitoring. Compared with the traditional level monitoring, the present invention uses fewer delay units and makes the overall area smaller.

In the level monitoring module of the present invention, the NMOS tube M1 is a large-sized device with a width-to-length ratio of 10, and the PMOS tube M2 is an inverse ratio. The aspect ratio is 100 times; the width-to-length ratio of PMOS transistor M3 is 10 for large-scale devices, and the width-to-length ratio of NMOS transistor M4 is 1/20. 200 times. The PMOS transistor M2 and the NMOS transistor M4 are inverse ratio transistors whose length is longer than the width, so that the leakage in the subthreshold region of the PMOS transistor M2 and the NMOS transistor M4 is very small, reducing the power consumption of the entire module. At the same time, when the power supply VCC is less than the turn-on threshold of the NMOS transistor and the turn-on threshold of the PMOS transistor, the capacitor C1 makes the voltage of the node NOD1 the voltage value of the power supply VCC, and the capacitor C2 makes the voltage value of the node NOD2 the ground; the power supply VCC is greater than the turn-on threshold of the NMOS transistor and the PMOS transistor. When one of the turn-on thresholds of the transistor is used, since the NMOS and the PMOS cannot be turned on at the same time, there is only leakage in the sub-threshold region, so no large current will be generated; when the power supply VCC is greater than the turn-on threshold of the NMOS transistor and the turn-on threshold of the PMOS transistor, and When it is less than the sum of the turn-on threshold of the NMOS transistor and the turn-on threshold of the PMOS transistor, since the size of the NMOS transistor M1 is much larger than that of the PMOS transistor M2, the NOD1 voltage is close to the turn-on threshold of the NMOS transistor; since the gate-source voltage of the PMOS transistor M3 is smaller than the turn-on threshold of the PMOS transistor threshold, the PMOS transistor M3 is cut off, and the NMOS transistor M4 keeps the voltage of the node NOD2 at ground. The final level monitoring module output VCC_Good is low level; when the power supply VCC is equal to the sum of the turn-on threshold of the NMOS transistor and the turn-on threshold of the PMOS transistor, the voltage of node NOD1 is approximately the turn-on threshold of the NMOS transistor, and the gate-source voltage of the PMOS transistor M3 is the threshold of the PMOS transistor. The turn-on threshold initiates conduction. Since the size of PMOS transistor M3 is much larger than that of NMOS transistor M4, the voltage of node NOD2 is instantly pulled up to the voltage value of power supply VCC by M3, and the output VCC_Good of the level monitoring module changes from low level to high level; When the sum of the threshold and the turn-on threshold of the PMOS transistor, the node NOD1 voltage is always the turn-on threshold of the NMOS transistor, the PMOS transistor M3 is always on, the node NOD2 voltage is always the power supply VCC voltage, and the level monitoring module outputs VCC_Good as a high level.

The delay deburring circuit of the present invention is shown in Figure 3, comprising: AND gate AND31, inverter INV31, inverter INV32, inverter INV33, inverter INV34, capacitor C31, capacitor C32, capacitor C33 And NAND gate NAND31;

One input terminal of the AND gate AND31 is VCC_Good connected to the output VCC_Good of the level monitoring module, and the other input terminal is connected to the output of the error detection and redundant output control module ER_RST, wherein the delay deburring circuit of the first power-on redundant module Connect the output OUT1 of the error detection and redundant output control module, the delay deburring circuit of the second power-on redundant module, connect the output OUT2 of the error detection and redundant output control module, and the delay of the third power-on redundant module The deburring circuit is connected to the output OUT3 of the error detection and redundant output control module; the output terminal of the AND gate AND31 is connected to the input terminal of the inverter INV31, and simultaneously connected to an input terminal of the NAND gate NAND31 and one end of the capacitor C31; the output terminal of the capacitor C31 The other end is connected to the power supply VCC; the output end of the inverter INV31 is connected to one end of the capacitor C32 and the input end of the inverter INV32; the other end of the capacitor C32 is grounded; the output end of the inverter INV32 is connected to the input of the inverter INV33 end; the output end of the inverter INV33 is connected to the input end of the inverter INV34; the output end of the inverter INV34 is connected to one end of the capacitor C33 while connecting the other input end of the NAND gate NAND31; the other end of the capacitor C33 is connected to Power supply VCC; the output terminal Power_Good of the NAND gate NAND31 is used as the output of the delay deburring circuit.

When the power-on redundant module does not have a single event effect, the error detection received by the ER_RST input terminal of the delay deburring circuit and the output of the redundant output control module is high level, when the power-on redundant module has a single event When the effect occurs, the output of the error detection and redundant output control module received by the ER_RST input terminal of the delay deburring circuit becomes low level, and the delay deburring circuit transmits the low level signal to the internal storage unit status monitoring module.

The internal storage unit state monitoring module of the present invention is as shown in Figure 4, comprises: inverter INV41, inverter INV42, ..., inverter INV4n, storage unit SRAM41, storage unit SRAM42, ..., storage unit SRAM4n, NMOS tube M41, NMOS tube M42, NMOS tube..., NMOS tube M4n, OR gate OR4n; n is a positive integer, n is greater than or equal to 3, and the specific value can be adjusted according to the actual circuit needs;

The input terminal of the inverter INV41 is connected to the output terminal Power_Good of the delay deburring circuit, and is simultaneously connected to the input terminal of the inverter INV42 (the connection relationship between the inverter INV43 and the inverter INV4n-1 is the same as that of the inverter INV42 ), the input terminal of the inverter INV4n, the R input terminal of the storage unit SRAM41, the R input terminal of the storage unit SRAM42 (the connection mode from the storage unit SRAM43 to the storage unit SRAM4n-1 is the same as that of the storage unit SRAM42), the storage unit SRAM4n R input terminal, gate of NMOS transistor M41, gate of NMOS transistor M42 (the connection relationship between NMOS transistor M43 and NMOS transistor M4n-1 is the same as that of NMOS transistor M42), gate of NMOS transistor M4n; output of inverter INV41 end is connected to the RN input end of the storage unit SRAM41; the output end of the inverter INV42 is connected to the RN input end of the storage unit SRAM42; the output end of the inverter INV4n is connected to the RN input end of the storage unit SRAM4n; the Z of the storage unit SRAM41 The output terminal is connected to the first input terminal of the OR gate OR4n; the ZN output terminal of the storage unit SRAM41 is connected to the drain of the NMOS transistor M41; the Z output terminal of the storage unit SRAM42 is connected to the second input terminal of the OR gate OR4n; the storage unit SRAM42 The ZN output terminal of the storage unit SRAM4n is connected to the drain of the NMOS transistor M42; the Z output terminal of the storage unit SRAM4n is connected to the nth input terminal of the OR gate OR4n; the ZN output terminal of the storage unit SRAM4n is connected to the drain of the NMOS transistor M4n; the NMOS transistor M41 The source of the NMOS transistor M42 is grounded; the source of the NMOS transistor M4n is grounded; the POR_Latch output of the OR gate OR4n is connected to the WL of the storage unit SRAM41, the WL input of the storage unit SRAM42, and the WL input of the storage unit SRAM4n Terminal, at the same time as the output of the internal storage unit status monitoring module.

When Power_Good is high, the storage unit SRAM41, the storage unit SRAM42 (the state change from the storage unit SRAM43 to the storage unit SRAM4n-1 is the same as the storage unit SRAM42), the storage unit SRAM4n is in the state of writing high level, and the input of the OR gate OR4n is High level, its output POR_Latch is high. When Power_Good changes from high to low, the storage unit SRAM41, storage unit SRAM42, and storage unit SRAM4n are written into a low level. After the writing is completed, the inputs of the OR gate OR4n all change to a low level, and the output POR_Latch of the OR gate OR4n changes to is low. Through the writing process of the storage unit SRAM41, the storage unit SRAM42, and the storage unit SRAM4n, it is ensured that the voltage value of the power supply VCC is in the interval where these types of storage units can be written smoothly, and various storage units are guaranteed to be

The digital auxiliary delay module of the present invention is shown in Figure 5, comprising: AND gate AND51, oscillator OSC, register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, Register FF59;

One input terminal of AND gate AND51 is the output of ER_RST connection error detection and redundant output control module, wherein the delay deburring circuit of the first power-on redundant module is connected with output OUT1 of the error detection and redundant output control module, the second The delay deburring circuit connection error detection of the power-on redundant module and the output OUT2 of the redundant output control module are connected, and the delay deburring circuit connection error detection of the third power-on redundant module is connected to the output OUT3 of the redundant output control module ; The output terminal of the AND gate AND51 is connected to the R input terminal of the register register FF51, and is connected to the control input terminal of the oscillator OSC at the same time; the R input terminal of the register FF52 is POR_Latch, which accepts the output POR_Latch of the internal storage unit status monitoring module, and is connected to the register FF53 at the same time The R input terminal of register FF54, the R input terminal of register FF55, the R input terminal of register FF56, the R input terminal of register FF57, the R input terminal of register FF58, the R input terminal of register FF59; the oscillator OSC The output terminal of register FF51 is connected to the clock input terminal of register FF51; the QN output terminal of register FF51 is connected to the D input terminal of register FF51; the Q output terminal of register FF51 is connected to the clock input terminal of register FF52; the QN output terminal of register FF52 is connected to the register FF52 D input; the Q output of register FF51 is connected to the clock input of register FF53; the QN output of register FF53 is connected to the D input of register FF53; the Q output of register FF53 is connected to the clock input of register FF54; the QN of register FF54 The output terminal is connected to the D input terminal of register FF54; the Q output terminal of register FF54 is connected to the clock input terminal of register FF55; the QN output terminal of register FF55 is connected to the D input terminal of register FF55; the Q output terminal of register FF55 is connected to the clock input terminal of register FF56 terminal; the QN output terminal of register FF56 is connected to the D input terminal of register FF56; the Q output terminal of register FF56 is connected to the clock input terminal of register FF57; the QN output terminal of register FF57 is connected to the D input terminal of register FF57; the Q output terminal of register FF57 Connect the clock input terminal of register FF58; the QN output terminal of register FF58 is connected to the D input terminal of register FF58; the Q output terminal of register FF58 is connected to the clock input terminal of register FF59; the D input terminal of register FF59 is connected to the power supply VCC; The Q output terminal is connected to the other input terminal of the AND gate AND51 and at the same time serves as the output POR_Good of the digital auxiliary delay module.

When no error occurs in the power-on redundant module, one input terminal of the AND gate AND51 is connected to ER_RST and the value of the output of the redundant output control module is high, and the output of the AND gate AND51 and the value of POR_Good at the other output terminal The same; when the output POR_Latch of the internal storage unit status monitoring module is high, the R input terminal of register FF59 is high, the output POR_Good of register FF59 is low, the oscillator OSC oscillates, and the R input terminal of register FF51 is low to count normally, but the register The R input terminals of FF52, register FF53, register FF54, register FF55, register FF56, register FF57, and register FF58 are all high and are in the clearing state; when the output POR_Latch of the internal storage unit status monitoring module is low, the register FF52, register The R input terminals of FF53, register FF54, register FF55, register FF56, register FF57, and register FF58 are low and are in a normal writable state. With the oscillator OSC oscillating, the register FF51, register FF52, register FF53, register FF54, The register FF55, register FF56, register FF57, register FF58, and register FF59 counters start counting. When the counter is full, the output POR_Good of the register FF59 changes from low to high, and the output POR_Good of the digital auxiliary delay module changes from low to high. The POR_OUT signal turns off the oscillator OSC.

When a single event effect occurs in the power-on redundant module and an error output occurs, one input terminal of AND gate AND51 is connected to ER_RST for error detection and redundant output control. The output value of the module is low, the value of AND51 is low, and the oscillator OSC oscillates , the R input terminal of register FF51 is low and can count normally, the R input terminal of register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, and register FF58 is low, and it is in a normal writable state. The register OSC oscillates, and the register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, and register FF59 start counting. When the counter is full, the output POR_Good of register FF59 changes from low to low. is high, the output POR_Good of the digital auxiliary delay module changes from low to high, and the POR_OUT signal turns off the oscillator OSC. The output of the error detection and redundant output control module resets the digital auxiliary delay module, so that the output of the power-on redundant module becomes high again, and eliminates the influence of the generated single event reversal and avoids its accumulation.

The error detection and redundant output control module of the present invention is shown in Figure 6, comprising: XOR gate XOR61, XOR gate XOR62, XOR gate XOR63, NAND gate NAND61, NAND gate NAND62, NAND gate NAND63 ;

An input terminal POR_Good1 of the exclusive OR gate XOR61 is connected to the output of the digital auxiliary delay module of the first power-on redundant module, and is connected to an input terminal of the exclusive OR gate XOR62 at the same time; the other input terminal POR_Good2 of the exclusive OR gate XOR62 is connected to the second The output of the digital auxiliary delay module of the power-on redundant module is connected to an input terminal of the exclusive OR gate XOR63 at the same time; the other input terminal POR_Good3 of the exclusive OR gate XOR63 is connected to the digital auxiliary delay module of the third power-on redundant module Output, connect another input end of XOR gate XOR61 at the same time; The output end of XOR gate XOR61 connects an input end of NAND gate NAND61 and connects an input end of NAND gate NAND63 at the same time; The output end of XOR gate XOR62 connects and One input end of the NOT gate NAND62 is connected with the other input end of the NAND gate NAND61 simultaneously; The output end of the XOR gate XOR63 is connected with the other input end of the NAND gate NAND63 while connecting the other input end of the NAND gate NAND62; The output terminal of the gate NAND61 is used as the output terminal OUT1 of the error detection and redundant output control module; the output terminal of the NAND gate NAND62 is used as the output terminal OUT2 of the error detection and redundant output control module; the output terminal of the NAND gate NAND63 is used as the error detection And the output terminal OUT3 of the redundant output control module.

The truth table of the error detection and redundant output control module of the present invention is shown in the following table 1. From the table, it can be seen that the three inputs of the error detection and redundant output control module will receive the POR_Good1 signal and the POR_Good2 signal respectively. , POR_Good3 signal for comparison, if the POR_Good1 signal, POR_Good2 signal, POR_Good3 signal are the same, then the three outputs OUT1, OUT2 and OUT3 of the error detection and redundant output control module are high level; if the POR_Good1 signal and POR_Good2 signal and POR_Good3 If the signals are different, OUT1 is low level, and OUT2 and OUT3 are high level; if the POR_Good2 signal is different from the POR_Good1 signal and POR_Good3 signal, then OUT2 is low level, and OUT1 and OUT3 are high level; if the POR_Good3 signal is different from the POR_Good1 signal Different from the POR_Good2 signal, OUT3 is low level, OUT1 and OUT2 are high level; the error detection and redundant output control module can detect the error of any one of the three channels through three XOR gates and three AND gates , by connecting the output of the module to the power-on redundant module, the power-on redundant module can be reset to clear the accumulation of single event effects; the output of the power-on redundant module can be cut off by connecting to the controllable output buffer to avoid A wrong output affects the output of the entire power-on reset circuit.

Table 1 Truth table of error detection and redundant output control module

The comparison between the single particle experimental results of the power-on reset circuit of the present invention and the single particle experimental results of the original power-on reset circuit is shown in Figure 7, the abscissa in the figure is LET, that is, linear energy transfer; the ordinate is crosssection , that is, the flip section; the small black squares represent the single-particle experimental results of the power-on reset circuit before reinforcement, and the thick curve is the Weibull curve fitted according to the experimental results. From the curve calculation, the flip threshold of the power-on reset circuit can be obtained LETTH is 3.07MeV.cm2/mg, and the saturation cross section is 2.13E-6cm2/device; the small black triangle represents the single particle experiment result of the power-on reset circuit of the present invention, because no single particle occurs under the condition of low LET value Error, so the number of flips is zero when the LET is lower than 22MeV.cm2/mg, only 1 error occurs at 22MeV.cm2/mg, 2 errors occur at 37MeV.cm2/mg, and 79MeV.cm2/mg An error occurs once, and the number of errors is too small to fit the Weibull curve. The flipping threshold LETTH of the power-on reset circuit of the present invention can be obtained directly from the number of errors, which is between 13MeV.cm2/mg and 22MeV.cm2/mg, which is 4.23 to 7.16 times that of the original circuit, and its saturation cross section is 2E-7cm2/device, which is 10 times that of the original power-on reset circuit, and the reinforcement effect is remarkable.

In summary, the present invention detects the power-on redundant module that has a single event effect error through the error detection and redundant output control module, and clears the accumulation of single event effect by resetting the power-on redundant module; The controllable output buffer can cut off the output of the power-on redundant module, so as to prevent the wrong output from affecting the output of the whole power-on reset circuit, thereby obtaining a remarkable reinforcement effect of single event effect.

Claims (7)

1. A power-on reset circuit that is applicable to the single-particle reinforcement of SRAM type FPGA for aerospace, is characterized in that: comprise power supply VCC, three identical power-on redundant modules, error detection and redundant output control module and three Controllable output buffer; three identical power-on redundant modules, namely the first power-on redundant module, the second power-on redundant module, and the third power-on redundant module; the three controllable output buffers are respectively are the first controllable output buffer, the second controllable output buffer, and the third controllable output buffer; Each power-on redundant module includes a level monitoring module, a delay deburring circuit, an internal storage unit status monitoring module, and a digital auxiliary delay module; The power supply supplies power to the level monitoring module, and the level monitoring module detects the voltage value of the power supply in real time. When the voltage value of the power supply is greater than or equal to the set upper threshold voltage Vthr, the level monitoring module outputs a high level signal and sends it to the delay In the glitch circuit, the high level signal ends the reset signal. When the voltage value of the power supply is lower than the set upper threshold voltage Vthr, the level monitoring module outputs a low level signal and sends it to the delay deburring circuit; The delay deburring circuit receives the high-level signal or low-level signal sent by the level monitoring module, and judges that when the feedback from the error detection and redundant output control module is a high-level signal, at the same time when it receives the high-level signal from the level monitoring module When the single pulse width of the high-level signal or low-level signal is less than or equal to the set pulse width, the single pulse is filtered out as a glitch, and a smooth high-level signal or a smooth low-level signal is sent to the internal storage Unit state monitoring module; when judging that the feedback from the error detection and redundant output control module is a low-level signal, when the pulse in the low-level signal fed back by the error detection and redundant output control module is less than or equal to the set pulse width, The single pulse is filtered out as a glitch, and the smooth low-level signal is sent to the internal storage unit status monitoring module; An internal storage unit status monitoring module, including multiple storage units; The internal storage unit status monitoring module, when receiving the smooth low-level signal sent by the delay deburring circuit, locks multiple storage units in the internal storage unit status monitoring module, that is, stops writing data to the storage unit, and at the same time Output high-level signals to the digital auxiliary delay module; the internal storage unit status monitoring module, when receiving the smooth high-level signal sent by the delay deburring circuit, writes to multiple storage units in the internal storage unit status monitoring module Enter the value opposite to the value stored in the storage unit, and then lock multiple storage units, that is, stop writing data to the storage unit, and output a low level signal to the digital auxiliary delay module at the same time; The digital auxiliary delay module includes multiple registers and an oscillator; The digital auxiliary delay module receives the high-level signal or low-level signal sent by the internal storage unit status monitoring module, and when the high-level signal is received from the internal storage unit status monitoring module, the error detection and redundant output control module When the feedback is high level, multiple registers in the digital auxiliary delay module are locked, that is, the value stored in the register remains unchanged, and a low level signal is output, that is, the output of the digital auxiliary delay module is a low level signal; When a high level signal is received from the internal storage unit status monitoring module and the feedback from the error detection and redundant output control module is low level, or when a low level signal is received from the internal storage unit status monitoring module and the error detection And when the feedback from the redundant output control module is high level, or when a low level signal is received from the internal storage unit status monitoring module and the feedback from the error detection and redundant output control module is low level, the oscillator starts to oscillate and output The clock signal, the register counts once after each oscillation, and when the register is full, it outputs a high level, that is, the output of the digital auxiliary delay module is a high level signal; The output of the first power-on redundant module is recorded as POR_Good1 signal, the second power-on redundant module POR_Good2 signal, the third power-on redundant module POR_Good3 signal; the output of the first power-on redundant module is recorded as POR_Good1 signal, Both the POR_Good2 signal of the second power-on redundant module and the POR_Good3 signal of the third power-on redundant module are sent to the error detection and redundant output control module; the output of the first power-on redundant module is recorded as the POR_Good1 signal and sent to the first control output buffer; record the output of the second power-on redundant module as POR_Good2 signal and send it to the second controllable output buffer; record the output of the third power-on redundant module as POR_Good3 signal and send it to the third controllable output buffer; The error detection and redundant output control module has three inputs and three outputs, the three outputs are OUT1, OUT2 and OUT3, and the output of OUT1 is fed back to the delay deburring circuit of the first power-on redundant module and the digital auxiliary delay module And sent to the first controllable output buffer, the output of OUT2 is fed back to the delay and deburring circuit of the second power-on redundant module, and the digital auxiliary delay module is sent to the second controllable output buffer, and the output of OUT3 is fed back to the second The delay deburring circuit of the three-power-on redundant module and the digital auxiliary delay module are sent to the third controllable output buffer; The three inputs of the error detection and redundant output control module compare the received POR_Good1 signal, POR_Good2 signal, and POR_Good3 signal respectively. If the POR_Good1 signal, POR_Good2 signal, and POR_Good3 signal are all the same, the three inputs of the error detection and redundant output control module Each output OUT1, OUT2 and OUT3 are high level; if POR_Good1 signal is different from POR_Good2 signal and POR_Good3 signal, then OUT1 is low level, OUT2 and OUT3 are high level; if POR_Good2 signal is different from POR_Good1 signal and POR_Good3 signal, Then OUT2 is low level, OUT1 and OUT3 are high level; if the POR_Good3 signal is different from the POR_Good1 signal and POR_Good2 signal, then OUT3 is low level, and OUT1 and OUT2 are high level; When the first controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good1 signal of the first power-on redundant module after inversion; when the first controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the first controllable output buffer does not output the signal; When the second controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good2 signal of the second power-on redundant module after inversion; when the second controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the second controllable output buffer does not output the signal; When the third controllable output buffer receives the output signal of the error detection and redundant output control module as a high level, it outputs the output POR_Good3 signal of the third power-on redundant module after inversion; when the third controllable The output buffer, when receiving the output signal of the error detection and redundant output control module is low level, the third controllable output buffer does not output the signal. 2. A kind of power-on reset circuit suitable for single particle reinforcement of aerospace SRAM type FPGA according to claim 1, characterized in that: said level monitoring module comprises: PMOS transistor M2, PMOS transistor M3, PMOS transistor M5, NMOS tube M1, NMOS tube M4, NMOS tube M7, capacitor C1, capacitor C2, inverter; The gate of the PMOS transistor M2 is grounded, the source of the PMOS transistor M2 is connected to the power supply VCC, and the drain of the PMOS transistor M2 is simultaneously connected to the gate and drain of the NMOS transistor M1, one end of the capacitor C1, and the gate of the PMOS transistor M3; The source of M1 is grounded; The other end of the capacitor C1 is connected to the power supply VCC, the gate of the NMOS transistor M4 is connected to the power supply VCC, the source of the PMOS transistor M3 is connected to the power supply VCC, the drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M4, one end of the capacitor C2, and the PMOS transistor The drain of M5, the gate of PMOS transistor M6, and the gate of NMOS transistor M7; the source of NMOS transistor M4 is grounded; the other end of capacitor C2 is grounded; the source of PMOS transistor M5 is connected to the power supply VCC, and the gate of PMOS transistor M5 Connect the drain of the PMOS transistor M6 to the drain of the NMOS transistor M7 and the input terminal of the inverter; the source of the PMOS transistor M6 is connected to the power supply VCC; the source of the NMOS transistor M7 is grounded; the output terminal VCC_Good of the inverter is used as the level Monitor the output of the module. 3. A kind of power-on reset circuit suitable for single particle reinforcement of aerospace SRAM type FPGA according to claim 1, characterized in that: said delay deburring circuit comprises: AND gate AND31, inverter INV31, Inverter INV32, inverter INV33, inverter INV34, capacitor C31, capacitor C32, capacitor C33 and NAND gate NAND31; One input terminal of the AND gate AND31 is VCC_Good connected to the output VCC_Good of the level monitoring module, and the other input terminal is connected to the output of the error detection and redundant output control module ER_RST, wherein the delay deburring circuit of the first power-on redundant module Connect the output OUT1 of the error detection and redundant output control module, the delay deburring circuit of the second power-on redundant module, connect the output OUT2 of the error detection and redundant output control module, and the delay of the third power-on redundant module The deburring circuit is connected to the output OUT3 of the error detection and redundant output control module; the output terminal of the AND gate AND31 is connected to the input terminal of the inverter INV31, and simultaneously connected to an input terminal of the NAND gate NAND31 and one end of the capacitor C31; the output terminal of the capacitor C31 The other end is connected to the power supply VCC; the output end of the inverter INV31 is connected to one end of the capacitor C32 and the input end of the inverter INV32; the other end of the capacitor C32 is grounded; the output end of the inverter INV32 is connected to the input of the inverter INV33 end; the output end of the inverter INV33 is connected to the input end of the inverter INV34; the output end of the inverter INV34 is connected to one end of the capacitor C33 while connecting the other input end of the NAND gate NAND31; the other end of the capacitor C33 is connected to Power supply VCC; the output terminal Power_Good of the NAND gate NAND31 is used as the output of the delay deburring circuit. 4. A kind of power-on reset circuit suitable for single particle reinforcement of aerospace SRAM type FPGA according to claim 1, characterized in that: the internal storage unit state monitoring module includes: inverter INV41, inverter INV42, ..., inverter INV4n, storage unit SRAM41, storage unit SRAM42, ..., storage unit SRAM4n, NMOS transistor M41, NMOS transistor M42, ..., NMOS transistor M4n, or gate OR4n; The input end of the inverter INV41 is connected to the output end Power_Good of the delay deburring circuit, and simultaneously connected to the input end of the inverter INV42, the input end of the inverter INV4n, the R input end of the storage unit SRAM41, and the R input end of the storage unit SRAM42. R input terminal, the R input terminal of the storage unit SRAM4n, the grid of the NMOS transistor M41, the grid of the NMOS transistor M42, and the grid of the NMOS transistor M4n; the output terminal of the inverter INV41 is connected to the RN input terminal of the storage unit SRAM41; The output end of the inverter INV42 is connected to the RN input end of the storage unit SRAM42; the output end of the inverter INV4n is connected to the RN input end of the storage unit SRAM4n; the Z output end of the storage unit SRAM41 is connected to the first input of the OR gate OR4n end; the ZN output end of the storage unit SRAM41 is connected to the drain of the NMOS transistor M41; the Z output end of the storage unit SRAM42 is connected to the second input end of the OR gate OR4n; the ZN output end of the storage unit SRAM42 is connected to the drain of the NMOS transistor M42 The Z output terminal of the storage unit SRAM4n is connected to the nth input terminal of the OR gate OR4n; the ZN output terminal of the storage unit SRAM4n is connected to the drain of the NMOS transistor M4n; the source of the NMOS transistor M41 is grounded; the source of the NMOS transistor M42 ground; the source of the NMOS tube M4n is grounded; the POR_Latch output of the OR gate OR4n is connected to the WL of the storage unit SRAM41, the WL input of the storage unit SRAM42, and the WL input of the storage unit SRAM4n, and at the same time as the internal storage unit status monitoring module output. 5. A kind of power-on reset circuit suitable for single particle reinforcement of aerospace SRAM type FPGA according to claim 1, characterized in that: said digital auxiliary delay module comprises: AND gate AND51, oscillator OSC, register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, register FF59; One input terminal of AND gate AND51 is the output of ER_RST connection error detection and redundant output control module, wherein the delay deburring circuit of the first power-on redundant module is connected with output OUT1 of the error detection and redundant output control module, the second The delay deburring circuit connection error detection of the power-on redundant module and the output OUT2 of the redundant output control module are connected, and the delay deburring circuit connection error detection of the third power-on redundant module is connected to the output OUT3 of the redundant output control module ; The output terminal of the AND gate AND51 is connected to the R input terminal of the register FF51, and is connected to the control input terminal of the oscillator OSC at the same time; the R input terminal of the register FF52 is POR_Latch, which accepts the output POR_Latch of the internal storage unit status monitoring module, and is connected to the register FF53 at the same time R input terminal, R input terminal of register FF54, R input terminal of register FF55, R input terminal of register FF56, R input terminal of register FF57, R input terminal of register FF58, R input terminal of register FF59; oscillator OSC The output terminal is connected to the clock input terminal of register FF51; the QN output terminal of register FF51 is connected to the D input terminal of register FF51; the Q output terminal of register FF51 is connected to the clock input terminal of register FF52; the QN output terminal of register FF52 is connected to the D terminal of register FF52 Input terminal; the Q output terminal of register FF51 is connected to the clock input terminal of register FF53; the QN output terminal of register FF53 is connected to the D input terminal of register FF53; the Q output terminal of register FF53 is connected to the clock input terminal of register FF54; the QN output terminal of register FF54 The terminal is connected to the D input terminal of register FF54; the Q output terminal of register FF54 is connected to the clock input terminal of register FF55; the QN output terminal of register FF55 is connected to the D input terminal of register FF55; the Q output terminal of register FF55 is connected to the clock input terminal of register FF56 ; The QN output of register FF56 is connected to the D input of register FF56; the Q output of register FF56 is connected to the clock input of register FF57; the QN output of register FF57 is connected to the D input of register FF57; the Q output of register FF57 is connected to The clock input terminal of register FF58; the QN output terminal of register FF58 is connected to the D input terminal of register FF58; the Q output terminal of register FF58 is connected to the clock input terminal of register FF59; the D input terminal of register FF59 is connected to the power supply VCC; The output end is connected to the other input end of the AND gate AND51 and at the same time serves as the output POR_Good of the digital auxiliary delay module. 6. A kind of power-on reset circuit applicable to the single particle reinforcement of aerospace SRAM type FPGA according to claim 1, characterized in that: the error detection and redundant output control module comprises: exclusive OR gate XOR61, exclusive OR gate XOR62, XOR gate XOR63, NAND gate NAND61, NAND gate NAND62, NAND gate NAND63; An input terminal POR_Good1 of the exclusive OR gate XOR61 is connected to the output of the digital auxiliary delay module of the first power-on redundant module, and is connected to an input terminal of the exclusive OR gate XOR62 at the same time; the other input terminal POR_Good2 of the exclusive OR gate XOR62 is connected to the second The output of the digital auxiliary delay module of the power-on redundant module is connected to an input terminal of the exclusive OR gate XOR63 at the same time; the other input terminal POR_Good3 of the exclusive OR gate XOR63 is connected to the digital auxiliary delay module of the third power-on redundant module Output, connect another input end of XOR gate XOR61 at the same time; The output end of XOR gate XOR61 connects an input end of NAND gate NAND61 and connects an input end of NAND gate NAND63 at the same time; The output end of XOR gate XOR62 connects and One input end of the NOT gate NAND62 is connected with the other input end of the NAND gate NAND61 simultaneously; The output end of the XOR gate XOR63 is connected with the other input end of the NAND gate NAND63 while connecting the other input end of the NAND gate NAND62; The output terminal of the gate NAND61 is used as the output terminal OUT1 of the error detection and redundant output control module; the output terminal of the NAND gate NAND62 is used as the output terminal OUT2 of the error detection and redundant output control module; the output terminal of the NAND gate NAND63 is used as the error detection And the output terminal OUT3 of the redundant output control module. 7. A kind of power-on reset circuit suitable for single particle reinforcement of aerospace SRAM type FPGA according to claim 2, characterized in that: the NMOS transistor M1 in the level monitoring module is a large-size device, and the large-size The width-to-length ratio of the device is 10; the PMOS tube M2 is an inverted tube, and the width-to-length ratio of the inverted tube is 1/10; the width-to-length ratio of the NMOS tube M1 is 100 times the width-to-length ratio of the PMOS tube M2; the PMOS tube is M3 in large size device, the large-size device has a width-to-length ratio of 10; the NMOS transistor M4 is an inverse ratio tube, and the inverse ratio tube has a width-to-length ratio of 1/20; the width-to-length ratio of the PMOS transistor M3 is 200 times the width-to-length ratio of the NMOS transistor M4.