CN105471301A - Auxiliary capacitor centralized half-bridge/full-bridge series-parallel MMC automatic voltage-equalizing topology based on equality constraint - Google Patents

Abstract

The invention provides an auxiliary capacitance centralized half-bridge/full-bridge hybrid MMC self-voltage equalizing topology based on equality constraints. In the half-bridge/full-bridge hybrid MMC self-balancing topology, the half-bridge/full-bridge hybrid MMC model is electrically connected with the self-balancing auxiliary circuit through the auxiliary switch in the auxiliary circuit, and the auxiliary switch is closed. The two components are based on the equation Constrained auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-balancing topology, the auxiliary switch is turned on, and the topology is equivalent to a half-bridge/full-bridge hybrid MMC topology. The 6<i>K</i> mechanical switches in the auxiliary switches can be omitted without emphasizing the difference of the two topologies. The half-bridge/full-bridge hybrid MMC self-balancing topology has DC fault clamping capability, does not rely on special voltage equalizing control, and can spontaneously realize the equalization of sub-module capacitor voltages on the basis of completing DC-AC energy conversion , and at the same time, the trigger frequency and capacitance of the sub-module can be correspondingly reduced to realize the fundamental frequency modulation of the MMC.

Description

Auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-balancing topology based on equality constraints

technical field

The invention relates to the field of flexible power transmission, in particular to an auxiliary capacitance centralized half-bridge/full-bridge hybrid MMC self-equalizing topology based on equality constraints.

Background technique

Modular multilevel converter (MMC) is the development direction of DC transmission technology in the future. MMC uses sub-module (SM) cascading to construct converter valves, which avoids the direct series connection of a large number of devices and reduces the impact on devices. Consistency requirements, while easy to expand and redundant configuration. As the number of levels increases, the output waveform is close to sinusoidal, which can effectively avoid the defects of low-level VSC-HVDC.

The half-bridge/full-bridge hybrid MMC is composed of half-bridge and full-bridge sub-modules. The half-bridge sub-module has a simple structure, low cost, and low operating loss. The full-bridge sub-module has DC fault clamping capability.

Unlike two-level and three-level VSCs, the DC side voltage of MMC is not supported by a large capacitor, but is supported by a series of independent suspension sub-module capacitors in series. In order to ensure the waveform quality of the voltage output on the AC side and to ensure that each power semiconductor device in the module bears the same stress, and to better support the DC voltage and reduce interphase circulation, it is necessary to ensure the periodic flow of the sub-module capacitor voltage in the bridge arm power is in a dynamically stable state.

The sorting voltage equalization algorithm based on capacitor voltage sorting is currently the mainstream idea to solve the problem of capacitor voltage equalization in MMC neutron modules, but it is also constantly exposing some of its inherent defects. First of all, the realization of the sorting function must rely on the millisecond-level sampling of the capacitor voltage, which requires a large number of sensors and fiber optic channels to cooperate; secondly, when the number of sub-modules increases, the calculation amount of the capacitor voltage sorting increases rapidly, which is a challenge for the hardware design of the controller. In addition, the implementation of the sorting voltage equalization algorithm has high requirements on the switching frequency of sub-modules, which are closely related to the voltage equalizing effect. In practice, it may not be possible due to the limitation of the voltage equalizing effect. If the trigger frequency of the sub-module is not increased, the loss of the converter will increase.

The document "ADC-LinkVoltageSelf-BalanceMethodforaDiode-ClampedModularMultilevelConverterWithMinimumNumberofVoltageSensors" proposes an idea of relying on clamping diodes and transformers to achieve MMC sub-module capacitor voltage balance. However, the design of this scheme destroys the modular characteristics of the sub-modules to a certain extent, and the capacitive energy exchange channel of the sub-modules is also limited to the phase, which fails to make full use of the existing structure of the MMC, and the introduction of three transformers complicates the control strategy. At the same time, it will also bring a large transformation cost.

Contents of the invention

In view of the above problems, the object of the present invention is to propose an economical, modular, half-bridge/full-bridge that does not depend on the voltage equalization algorithm, can correspondingly reduce the sub-module trigger frequency and capacitance value, and has DC fault clamping capability Hybrid MMC self-equalizing topology.

The specific constitution of the present invention is as follows.

Auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-balancing topology based on equality constraints, including a half-bridge MMC model composed of three phases A, B, and C. Each bridge arm of the three phases A, B, and C is respectively It is composed of K half-bridge sub-modules, N - K full-bridge sub-modules and 1 bridge arm reactor in series; including 6 N auxiliary switches (6 K mechanical switches, 6 N -6 K IGBT modules) , 6 N + 5 clamping diodes, 2 auxiliary capacitors, and a self-leveling auxiliary circuit composed of 2 auxiliary IGBT modules.

The above-mentioned auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-voltage equalization topology based on equality constraints, the first sub-module of the upper bridge arm of phase A, the negative pole of the sub-module capacitor is downward and the second sub-module of the upper bridge arm of phase A The middle points of the IGBT modules of the two sub-modules are connected, and the mid-points of the IGBT modules of the sub-modules are connected upwardly to the positive pole of the DC bus; the i -th sub-module of the upper bridge arm of phase A, where the value of i is 2 to K -1, its sub-module The negative pole of the capacitor is downwardly connected to the midpoint of the i +1 submodule IGBT module of the upper bridge arm of phase A, and the midpoint of the IGBT module of the submodule is upwardly connected to the negative pole of the capacitor of the i -1th submodule of the upper bridge arm of phase A; The K -th half-bridge sub-module of the upper bridge arm of phase A, the negative pole of the sub-module capacitor is connected downward to the middle point of an IGBT module of the K +1th sub-module of the upper bridge arm of phase A, and the mid-point of the IGBT module of the sub-module is upward It is connected to the negative electrode of the capacitor of the K -1th sub-module of the upper bridge arm of phase A; the j -th sub-module of the upper bridge arm of phase A, where the value of j is K +2～ N -1, and its sub-module is in an IGBT module The point is downwardly connected to the middle point of an IGBT module of the j + 1st sub-module of the upper bridge arm of phase A, and the midpoint of the other IGBT module is connected upward to the midpoint of an IGBT module of the j -1th sub-module of the upper bridge arm of phase A ; The Nth sub-module of the upper bridge arm of phase A, the middle point of one IGBT module of its sub-module is connected downwards with the midpoint of the IGBT module of the first sub-module of the lower bridge arm of phase A through two bridge arm reactors L ₀ , and the other The midpoint of the IGBT module is upwardly connected to the midpoint of an IGBT module of the N -1th sub-module of the upper bridge arm of the A phase; the i -th submodule of the lower bridge arm of the A-phase, where the value of i is 2 to K The negative electrode of the sub-module capacitor is downwardly connected to the midpoint of the i +1 submodule IGBT module of the lower bridge arm of phase A, and the midpoint of its IGBT module is upwardly connected to the negative electrode of the i -1th submodule capacitor of the lower bridge arm of phase A; The Kth sub-module of the lower bridge arm, the negative pole of the sub-module capacitor is connected downwards to the middle point of an IGBT module of the K +1th sub-module of the lower bridge arm of the A phase, and the midpoint of the IGBT module of the sub-module is connected upwards to the lower bridge of the A phase The K -1th sub-module of the arm is connected to the negative pole of the capacitor; the j -th sub-module of the bridge arm under the A-phase, where the value of j is K +2 to N -1, and the midpoint of one IGBT module of the sub-module is downward and the A-phase is downward The j +1th sub-module of the bridge arm is connected to the midpoint of one IGBT module, and the midpoint of the other IGBT module is connected upward to the midpoint of the j -1th submodule of the lower bridge arm of the A phase; the midpoint of the IGBT module of the lower bridge arm of the A phase is N The midpoint of one IGBT module of the three submodules is downwardly connected to the negative pole of the DC bus, and the midpoint of the other IGBT module is upwardly connected to the midpoint of one IGBT module of the N -1th submodule of the lower bridge arm of phase A. In the first sub-module of the upper bridge arm of phase B, the positive pole of the sub-module capacitor is connected upward to the positive pole of the DC bus, and the midpoint of the IGBT module of the sub-module is connected downward to the positive pole of the second sub-module capacitor of the upper bridge arm of phase B; B The i -th sub-module of the upper bridge arm of the phase, where the value of i is 2 to K -1, the positive pole of the sub-module capacitor is connected upwards to the midpoint of the i -1 sub-module IGBT module of the upper bridge arm of the B phase, and its sub-module The midpoint of the IGBT module of the module is connected downwards with the positive pole of the i +1 submodule capacitor of the upper bridge arm of the B phase; the Kth submodule of the upper bridge arm of the B phase is connected upward with the positive pole of the submodule capacitor of the upper bridge arm of the B phase K -1 sub-modules are connected to the midpoint of the IGBT module, and the midpoint of the IGBT module of the submodule is connected downward to the midpoint of the K +1th submodule of the upper bridge arm of the B phase; the jth submodule of the upper bridge arm of the B phase module, where the value of j is K +2 ~ N -1, and the midpoint of one IGBT module of its submodule is connected upwardly with the j -1th submodule of the upper bridge arm of phase B. The point downward is connected to the middle point of an IGBT module of the j +1th sub-module of the upper bridge arm of the B phase; the Nth sub-module of the upper bridge arm of the B-phase, and the midpoint of an IGBT module of its sub-module is upwardly connected to the Nth sub-module of the upper bridge arm of the B phase -1 sub-module One IGBT module is connected to the middle point, and the other IGBT module is connected to the positive pole of the first sub-module capacitor of the lower bridge arm of the B phase through the two bridge arm reactors L ₀ downward; the lower bridge arm of the B phase The i -th sub-module of , where the value of i is 2 to K -1, the positive pole of the sub-module capacitor is connected upwards to the midpoint of the i -1th sub-module IGBT module of the lower bridge arm of the B phase, and the sub-module IGBT module The point is connected downward to the i +1th submodule capacitor positive pole of the lower bridge arm of phase B; the Kth submodule of the lower bridge arm of phase B is connected to the positive pole of the submodule capacitor of the lower bridge arm of phase B upwards to the K -1th submodule of the lower bridge arm of phase B The midpoint of the IGBT module is connected, and the midpoint of the submodule IGBT module is connected downward to the midpoint of an IGBT module of the K +1th submodule of the lower bridge arm of the B phase; the jth submodule of the lower bridge arm of the B phase, where j is taken as The value is K +2 ~ N -1, the midpoint of one IGBT module of its sub-module is connected upward to the j -1th submodule of the lower bridge arm of phase B. The midpoint of one IGBT module is connected downward, and the midpoint of the other IGBT module is downwardly connected to the B-phase The j +1th sub-module of the lower bridge arm is connected to the middle point of an IGBT module; the Nth sub-module of the lower bridge arm of the B-phase, the midpoint of one IGBT module of its sub-module is upward and the N -1th sub-module of the lower bridge arm of the B-phase is an IGBT The midpoints of the modules are connected, and the midpoint of the other IGBT module is connected downward with the negative pole of the DC bus. The connection mode of the upper and lower bridge arm submodules of phase C is the same as that of phase A or B.

In the self-balancing auxiliary circuit, the positive pole of the first auxiliary capacitor is connected to the negative pole of the auxiliary IGBT module, connected to the clamping diode and merged into the positive pole of the DC bus; the negative pole of the second auxiliary capacitor is connected to the positive pole of the auxiliary IGBT module, connected to the clamping diode and merged into the negative pole of the DC bus. Clamp diode, connect the capacitor of the first sub-module in the upper arm of phase A to the anode of the first auxiliary capacitor through the auxiliary switch; connect the capacitor of the i -th sub-module in the upper arm of phase A to the capacitor of the i +1 sub-module Positive pole, where the value of i is 1 to N -1; connect the Nth sub-module capacitor in the upper bridge arm of phase A to the positive pole of the first sub-module capacitor in the lower bridge arm of phase A through the auxiliary switch; connect the lower bridge of phase A through the auxiliary switch The i -th sub-module capacitor in the arm is connected to the positive electrode of the i + 1-th sub-module capacitor in the lower bridge arm of phase A, where the value of i is 1 to N -1; the capacitor of the N -th sub-module in the lower bridge arm of phase A is connected to The positive terminal of the second auxiliary capacitor. Clamping diode, connect the capacitor of the first sub -module in the upper bridge arm of phase B to the cathode of the first auxiliary capacitor through the auxiliary switch; The negative pole of the capacitor, where the value of i is 1 to N -1; connect the Nth sub-module capacitor in the upper bridge arm of phase B to the negative pole of the first sub-module capacitor in the lower bridge arm of phase B through the auxiliary switch; connect B through the auxiliary switch The i -th sub-module capacitor in the lower bridge arm of the phase and the negative electrode of the i + 1-th sub-module capacitor in the lower bridge arm of the B-phase, where the value of i is 1 to N -1; the N -th sub-module in the lower bridge arm of the B-phase is connected through an auxiliary switch The first sub-module capacitor and the negative pole of the second auxiliary capacitor. The connection relationship of the C-phase clamping diode corresponds to the connection relationship of its sub-modules.

Description of drawings

The present invention will be further described below in conjunction with the accompanying drawings.

Fig. 1 is a structural schematic diagram of a half-bridge sub-module;

Fig. 2 is a schematic structural diagram of a full-bridge sub-module;

Figure 3 is the self-balancing topology of the half-bridge/full-bridge hybrid MMC with centralized auxiliary capacitors based on equality constraints.

detailed description

In order to further illustrate the performance and working principle of the present invention, the composition and working principle of the invention will be described in detail below in conjunction with the accompanying drawings. However, the half-bridge/full-bridge hybrid MMC self-equalizing topology based on this principle is not limited to Fig. 3 .

Referring to Figure 3, the self-equalizing topology of the auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC based on equality constraints, including the half-bridge/full-bridge hybrid MMC model composed of three phases A, B, and C, A, B , each bridge arm of C three-phase is composed of K half-bridge sub-modules, N - K full-bridge sub-modules and 1 bridge arm reactor in series; including 6 N auxiliary switches (6 K mechanical switches, 6 N -6 K IGBT modules), 6 N + 5 clamping diodes, 2 auxiliary capacitors, and a self-balancing auxiliary circuit composed of 2 auxiliary IGBT modules.

In the half-bridge/full-bridge hybrid MMC model, the first sub-module of the upper bridge arm of phase A, its sub-module capacitor C - _{au-_1} is negatively connected to the midpoint of the second sub-module IGBT module of the upper bridge arm of phase A. The midpoint of its sub-module IGBT module is connected upwards to the positive pole of the DC bus; the i -th sub-module of the upper bridge arm of phase A, where the value of i is 2 to K -1, and its sub-module capacitance C - _{au-_ i} The negative pole is connected downward to the midpoint of the i +1 submodule IGBT module of the upper bridge arm of phase A, and the midpoint of its submodule IGBT module is upwardly connected to the capacitor C _{-au-_} of the i -1th submodule of the upper bridge arm of phase A _{i -1} negative pole is connected; the Kth half-bridge sub-module of the upper bridge arm of phase A, its sub-module capacitance C _{- au-_ K} is negatively connected to the K +1th sub-module of the upper bridge arm of phase A with an IGBT module The midpoint is connected, and the midpoint of the submodule IGBT module is upwardly connected to the negative electrode of the K -1th submodule capacitor C - _{au-_ K -1} of the upper bridge arm of the A phase; the jth submodule of the upper bridge arm of the A phase, Among them, the value of j is K +2 ~ N -1, and the midpoint of one IGBT module of its submodule is connected downward with the j +1th submodule of the upper bridge arm of phase A. The midpoint of one IGBT module is connected with the midpoint of the other IGBT Connect upward to the middle point of an IGBT module of the j -1th submodule of the upper bridge arm of the A phase; the Nth submodule of the upper bridge arm of the A phase, and the midpoint of an IGBT module of the submodule goes downward through two bridge arm reactors L ₀ is connected to the middle point of the IGBT module of the first sub-module of the lower bridge arm of the A phase, and the middle point of the other IGBT module is connected upward to the middle point of the N -1th sub-module of the upper bridge arm of the A phase; The i -th sub-module of the bridge arm, where the value of i is 2 to K -1, the negative pole of the sub-module capacitor C - _{al-_ i} is in phase with the midpoint of the i +1 sub-module IGBT module of the lower bridge arm of the lower bridge arm of phase A. The midpoint of its IGBT module is upwardly connected to the cathode of the i -1 sub-module capacitor C- _{al-_ i -1} of the lower bridge arm of phase A; the K -th sub-module of the lower bridge arm of phase A has a sub-module capacitor C _{- al_ The negative pole of K} is connected downward to the middle point of an IGBT module of the K +1 sub-module of the lower bridge arm of phase A, and the mid-point of the IGBT module of its sub-module is upwardly connected to the capacitance C of the K -1 sub-module of the lower bridge arm of phase A - _{al -_ K- 1} Negative phase connection; the jth sub-module of the lower bridge arm of phase A, where the value of j is K +2 ~ N -1, and the midpoint of one IGBT module of the sub-module is downwards to the lower bridge arm of phase A j +1 sub-modules are connected to the midpoint of one IGBT module, and the midpoint of the other IGBT module is connected upward to the midpoint of the j - 1th submodule of the A-phase lower bridge arm; one IGBT module midpoint of the lower bridge arm of the A-phase The midpoint of the IGBT module is downwardly connected to the negative pole of the DC bus, and the midpoint of the other IGBT module is upwardly connected to the midpoint of an IGBT module of the N -1th sub-module of the lower bridge arm of phase A. The first sub-module of the upper bridge arm of phase B, the positive pole of the sub-module capacitor C _{- bu-_1} is connected upward to the positive pole of the DC bus, and the midpoint of the sub-module IGBT module is downwardly connected to the capacitor of the second sub-module of the upper bridge arm of phase B The positive pole of C _{-bu-_2} is connected to the positive pole; the i -th sub-module of the upper bridge arm of phase B, where the value of i is 2 to K -1, the sub-module capacitance C - _{bu-_ i} is positively connected to the upper bridge arm of phase B The midpoint of the I -1th sub-module IGBT module of the sub-module is connected downward, and the midpoint of the IGBT module of the sub-module is downwardly connected to the positive electrode of the i+1th sub-module capacitor C - _{bu-_ i +1} of the upper bridge arm of the B phase; B The Kth sub-module of the upper bridge arm of the phase, the positive pole of the sub-module capacitor C - _{bu-_ K} is connected to the middle point of the IGBT module of the K -1th sub-module of the upper bridge arm of the B-phase upward, and the midpoint of the IGBT module of the sub-module is towards The bottom is connected to the middle point of an IGBT module of the K +1th submodule of the upper bridge arm of the B phase; the jth submodule of the upper bridge arm of the B phase, where the value of j is K +2 to N -1, and one of its submodules The midpoint of the IGBT module is upwardly connected to the midpoint of an IGBT module of the j -1th submodule of the upper bridge arm of the B phase, and the midpoint of the other IGBT module is downwardly connected to the midpoint of an IGBT module of the j +1th submodule of the upper bridge arm of the B phase Phase connection; the Nth sub-module of the upper bridge arm of the B-phase, the midpoint of one IGBT module is connected upwards with the midpoint of one IGBT module of the N -1th sub-module of the upper bridge arm of the B-phase, and the midpoint of the other IGBT module is downwards through two A bridge arm reactor L ₀ is connected to the positive pole of the first sub-module capacitor C _{-bl-_1} of the lower bridge arm of the B-phase; the i -th sub-module of the lower bridge arm of the B-phase, where the value of i is 2 ~ K -1 , the positive pole of the sub-module capacitor C _{-bl_ i} is connected upwards with the middle point of the i -1th sub-module IGBT module of the B-phase lower bridge arm, and the midpoint of its sub-module IGBT module is downwardly connected with the i -th sub-module I+ of the lower bridge arm of the B-phase One sub-module capacitor C- _{bl-_ i +1} is connected to the positive pole; the K -th sub-module of the lower bridge arm of the B-phase, the positive pole of the sub-module capacitor C _{-bl_ K} is upwards and the K -1th sub-module IGBT of the lower bridge arm of the B-phase The midpoint of the module is connected, and the midpoint of the submodule IGBT module is connected downward to the midpoint of an IGBT module of the K +1th submodule of the lower bridge arm of the B phase; the jth submodule of the lower bridge arm of the B phase, where the value of j K +2～ N -1, the midpoint of one IGBT module connects upward with the midpoint of the j -1th sub-module of the lower bridge arm of phase B, and the midpoint of the other IGBT module downwardly connects with the lower bridge arm of phase B The j +1 sub-module IGBT is connected to the middle point of an IGBT module; the Nth sub-module of the lower bridge arm of the B phase, the midpoint of one IGBT module of its sub-module is upward and the N -1th sub-module of the lower bridge arm of the B phase is in an IGBT module The midpoint of the other IGBT module is connected downward with the negative pole of the DC bus. The connection mode of the sub-modules of the upper and lower bridge arms of phase C is the same as that of phase A.

In the self-balanced auxiliary circuit, the positive pole of the auxiliary capacitor C ₁ is connected to the auxiliary IGBT module T ₁ , the negative pole is connected to the clamping diode and merged into the positive pole of the DC bus; the negative pole of the auxiliary capacitor C ₂ is connected to the auxiliary IGBT module T ₂ , and the positive pole is connected to the clamping diode and merged into the DC bus. Bus negative pole. The clamping diode is connected to the anode of the first sub-module capacitor C _{-au-_1} in the upper bridge arm of phase A and the positive pole of the auxiliary capacitor C ₁ through the auxiliary switch K _{au_12} ; connected through the auxiliary switches K _{au_ i 2} and K _{au_( i +1) 2} The positive electrode of the i -th sub-module capacitor C _{-au-_ i} and the i +1-th sub-module capacitor C _{-au-_ i +1} in the upper bridge arm of phase A, where the value of i is 1 to K -1; through the auxiliary Switches K _{au_ K 2} , T _{au_ K +1} are connected to the positive electrode of the Kth sub-module capacitor C _{-au-_ K} and the K +1th sub-module capacitor C- _{au_ K +1} in the upper bridge arm of phase A; through the auxiliary switch T _{au_ j} , T _{au_ j +1} are connected to the positive electrode of the jth submodule capacitor C _{-au-_ j} and the j +1th submodule capacitor C _{-au-_ j +1} in the upper bridge arm of phase A, where the value of j is K +1～ N -1; through the auxiliary switch T _{au_ N} , K _{al_12} , connect the capacitor C - _{au_ N} of the Nth sub-module in the upper arm of the phase A to the anode of the capacitor C _{-al-_1} of the first sub-module in the lower arm of the A phase ; Connect the i -th sub-module capacitor C _{-al-_ i} and the i +1-th sub-module capacitor C _{-al-_ i +} in the lower bridge arm of phase A through the auxiliary switches K _{al_ i 2} , K _{al_( i +1) 2 1} , where the value of i is 1 to K -1; through the auxiliary switch K _{al_ K 2} , T _{al_ K +1} , connect the Kth sub-module capacitor C - _{al-_ K} in the lower bridge arm of phase A to the Kth +1 submodule capacitor C - _{al-_ K +1} positive pole; connect the jth submodule capacitor C _{-al_ j} in the lower bridge arm of phase A to the j +1th submodule through auxiliary switches T _{al_ j} , T _{al_} j +1 The positive pole of capacitor C _{-al-_ j +1} , where the value of j is K +1 ~ N -1; through the auxiliary switch T _{al_ N} , connect the capacitor C _{-al_ N} of the Nth sub-module in the lower bridge arm of phase A to the auxiliary _Capacitor C2 positive. The clamping diode is connected to the negative pole of the first sub-module capacitor C _{-bu-_1} in the upper bridge arm of phase B and the auxiliary capacitor C ₁ through the auxiliary switch K _{bu_12} ; it is connected through the auxiliary switches K _{bu_ i 2} and K _{bu_( i +1) 2} The capacitor C - bu-_ i of the i-th sub-module in the upper bridge arm of phase B and the negative electrode of the capacitor C _- bu - _{_ i +1} of the i +1 sub-module, where the value of i is 1 to K -1; through the auxiliary switch K _{bu_ K 2} , T _{bu_ K +1} are connected to the Kth sub-module capacitor C - _{bu-_ K} in the upper bridge arm of phase B and the K +1th sub-module capacitor C - _{bu-_ K +1} negative pole; through the auxiliary switch T _{bu_ j} , T _{bu_ j +1} are connected to the jth sub-module capacitor C - _{bu-_ j} in the upper bridge arm of phase B and the j +1th sub-module capacitor C - _{bu-_ j +1} negative pole, where the value of j is K +1～ N -1; through the auxiliary switch T _{bu_ N} , K _{bl_12} , connect the Nth sub-module capacitor C - _{bu-_ N} in the upper bridge arm of phase B to the first sub-module capacitor C - _{bl_1} in the lower bridge arm of phase B Negative pole; through the auxiliary switch K _{bl_ i 2} , K _{bl_( i +1) 2} , connect the i -th sub-module capacitor C - _{bl-_ i} and the i + 1-th sub-module capacitor C - _{bl-_ i} in the lower bridge arm of phase B ₊₁ negative pole, where the value of i is 1 to K -1; through the auxiliary switch K _{bl_ K 2} , T _{bl_ K +1} , connect the capacitor C of the Kth sub-module in the lower bridge arm of the B phase - _{bl_ K} to the Kth +1 The negative pole of the sub-module capacitor C - _{bl-_ K +1} is connected to the j -th sub-module capacitor C - _{bl-_ j} in the lower bridge arm of phase B and the j + 1-th sub-module through the auxiliary switches T _{bl_ j} and T _{bl_ j +1} Capacitor C - _{bl_ j +1} negative pole, where the value of j is K +1 ~ N -1; connect the Nth sub-module capacitor C _{-bl-_ N} in the lower bridge arm of phase B to the auxiliary capacitor through the auxiliary switch T _{bl_ N} C2 _negative pole. The connection relationship of the C-phase clamping diode is consistent with that of the A-phase.

Under normal circumstances, 6 N auxiliary switches K _{au_ i 2} , K _{al_ i 2 ,} K bu_ i 2 , K _{bl_ i 2} , K _{cu_ i 2} , K _{cl_ i 2} , T _{au_ j} , T al_ _j , T bu_ _j , T _{bl_ j} , T _{cu_ j} , T _{cl_ j are} normally closed, where the value of i is 1~ K , the value of j is K +1~ N , the first one of the upper bridge arm of phase A When the sub-module capacitor C - _{au-_1} is bypassed, the auxiliary IGBT module T ₁ is disconnected at this time, and the sub-module capacitor C _{-au-_1} and the auxiliary capacitor C ₁ are connected in parallel through the clamp diode; the i -th sub-module of the upper bridge arm of phase A When the capacitor C - _{au-_ i} is bypassed, the value of i is 2 ~ N , the sub-module capacitor C - _{au-_ i} and the sub-module capacitor C - _{au-_ i -1} are connected in parallel through the clamp diode; A phase When the first sub-module capacitor C - _{al_1} of the lower bridge arm is bypassed, the sub-module capacitor C - _{al-_1} is connected in parallel with the sub-module capacitor C- _{au-_ N} through the clamp diode and two bridge arm reactors L ₀ ; A When the i -th sub-module capacitor C - _{al_ i} of the lower bridge arm is bypassed, where the value of i is 2 to N , the sub-module capacitor C- _{al-_ i} and the sub-module capacitor C - _{al_ i -1} pass through the clamping diode Parallel connection; when the auxiliary IGBT module T ₂ is closed, the auxiliary capacitor C ₂ is connected in parallel with the sub-module capacitor C - _{al_ N} through the clamp diode.

Under normal circumstances, 6 N auxiliary switches K _{au_ i 2} , K _{al_ i 2 ,} K bu_ i 2 , K _{bl_ i 2} , K _{cu_ i 2} , K _{cl_ i 2} , T _{au_ j} , T al_ _j , T bu_ _j , T _{bl_ j} , T _{cu_ j} , T _{cl_ j are} normally closed, where the value of i is 1 to K and the value of j is K +1 to N. When the auxiliary IGBT module T ₁ is closed, The auxiliary capacitor C ₁ and the sub-module capacitor C - _{bu-_1} are connected in parallel through the clamping diode; when the i -th sub-module capacitor C - _{bu-_ i} of the upper bridge arm of phase B is bypassed, the value of i is 1 to N -1 , the sub-module capacitor C - _{bu-_ i} is connected in parallel with the sub-module capacitor C- _{bu-_ i +1} through the clamp diode; when the Nth sub-module capacitor C - _{bu_ N} of the upper bridge arm of phase B is bypassed, the sub-module capacitor C _{-bu-_ N} is connected in parallel with the sub-module capacitor C- _{bl-_1} through the clamping diode and two bridge arm reactors L ₀ ; when the i -th sub-module capacitor C - _{bl_ i} of the lower bridge arm of the B phase is bypassed, the value of i The value is 1 to N -1, the sub-module capacitor C _{-bl-_ i} and the sub-module capacitor C- _{bl_ i +1} are connected in parallel through the clamp diode; the Nth sub-module capacitor C - _{bl_ N} of the lower bridge arm of the B phase is bypassed , the sub-module capacitor C - _{bl - _N} and the auxiliary capacitor C- ₂ are connected in parallel through the clamping diode. The trigger signal of the above auxiliary IGBT module T1 is consistent with the "logic sum" of the trigger signals of the _first submodule of the upper bridge arm of the A and C phases _; the trigger signal of the auxiliary IGBT module T2 is consistent with that of the Nth submodule of the lower bridge arm of the B phase The trigger signals are consistent.

In the process of DC-AC energy conversion, each sub-module is switched on and bypassed alternately, and the auxiliary IGBT modules T ₁ and T ₂ are switched on and off alternately. Satisfy the following constraints:

It can be seen that in the dynamic process of the half-bridge/full-bridge hybrid MMC completing the DC-AC energy conversion, the following constraints are met:

The constraint conditions between C and B phases are consistent with those between A and B phases.

It can be seen from the above detailed description that the half-bridge/full-bridge hybrid MMC topology has the capability of sub-module capacitor voltage self-balancing.

Finally, it should be noted that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Claims (6)

1. Auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-balancing topology based on equality constraints, which is characterized in that it includes a half-bridge/full-bridge hybrid MMC model composed of three phases A, B, and C, A Each bridge arm of the three phases , B, and C is composed of K half-bridge sub-modules, N - K full-bridge sub-modules and 1 bridge arm reactor in series; including 6 N auxiliary switches (6 K mechanical switches , 6 N -6 K IGBT modules), 6N+5 clamping diodes, 2 auxiliary capacitors and 2 auxiliary IGBT modules constitute a self-balancing auxiliary circuit. 2. The auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-equalizing topology based on equality constraints according to claim 1, characterized in that: the first sub-module of the upper bridge arm of phase A has a sub-module capacitance C - The negative pole of _{au-_1} is connected downward to the midpoint of the second submodule IGBT module of the upper bridge arm of phase A, and the midpoint of its submodule IGBT module is connected upward to the positive pole of the DC bus; the i -th submodule of the upper bridge arm of phase A , where the value of i is 2 to K -1, the negative pole of the sub-module capacitor C - _{au-_ i} is connected downward to the midpoint of the I+1th sub-module IGBT module of the upper bridge arm of phase A, and the sub-module IGBT The midpoint of the module is upwardly connected to the cathode of the i -1 sub-module capacitor C _{-au-_ i -1} of the upper bridge arm of phase A; the K -th half-bridge sub-module of the upper bridge arm of phase A has a sub-module capacitor C _{- au-_ The negative pole of K} is connected downward with the middle point of an IGBT module of the K +1th sub-module of the upper bridge arm of phase A, and the midpoint of the IGBT module of its sub-module is upwardly connected with the capacitance of the K -1th sub-module of the upper bridge arm of phase A C - _{au-_ K -1} is connected to the negative pole; the jth sub-module of the upper bridge arm of phase A, where the value of j is K +2 ~ N -1, and the midpoint of one IGBT module of the sub-module is downward to phase A The j +1th sub-module of the upper bridge arm is connected to the midpoint of one IGBT module, and the midpoint of the other IGBT module is connected upward to the midpoint of the j -1th submodule of the upper bridge arm of phase A; the midpoint of an IGBT module is connected to the upper bridge arm of phase A In the Nth sub-module, the midpoint of one IGBT module of its submodule is connected downwardly with the midpoint of the first submodule IGBT module of the lower bridge arm of phase A through two bridge arm reactors L ₀ , and the midpoint of the other IGBT module is upwardly connected with The N -1th sub-module of the upper bridge arm of phase A is connected to the middle point of an IGBT module; the i -th sub-module of the lower bridge arm of phase A, where the value of i is 2 to K -1, its sub-module capacitance C - _{al -_ The negative pole of i} is downwardly connected to the midpoint of the IGBT module of the i +1 sub-module of the lower bridge arm of the A phase, and the midpoint of the IGBT module is upwardly connected to the capacitor C- _{al- _i} of the i -1 submodule of the lower bridge arm of the A phase _-1 negative pole is connected; the Kth sub-module of the lower bridge arm of phase A, its sub-module capacitor C _{- al_ K} negative pole is connected downwards with the middle point of an IGBT module of the K +1th sub-module of the lower bridge arm of phase A, and its The midpoint of the sub-module IGBT module is upwardly connected to the cathode of the K -1th sub-module capacitor C- _{al-_ K- 1} of the lower bridge arm of the A phase; the jth sub-module of the lower bridge arm of the A-phase, where the value of j is K + 2～ N -1, the midpoint of one IGBT module of its sub-module is connected downwards with the j +1th submodule of the lower bridge arm of phase A. j - 1 sub-module is connected to the midpoint of one IGBT module; the midpoint of the Nth submodule of the lower bridge arm of phase A is connected downward to the negative pole of the DC bus, and the midpoint of the other IGBT module is upwardly connected to the negative pole of the lower bridge arm of phase A. The N -1th sub-module is connected to the middle point of an IGBT module; the first sub-module of the upper bridge arm of the B phase, the positive pole of the sub-module capacitor C _{- bu-_1} is connected upward to the positive pole of the DC bus, and the midpoint of the sub-module IGBT module Connect downward to the positive electrode of the second sub-module capacitor C _{-bu-_2} of the upper bridge arm of phase B; the i -th sub-module of the upper bridge arm of phase B, where the value of i is 2 to K -1, its sub-module capacitance C - _{bu-_ The positive pole of i} is connected upwards with the middle point of the IGBT module of the i -1th sub-module of the upper bridge arm of the B phase, and the midpoint of the IGBT module of its sub-module is downwardly connected with the i +1th submodule of the upper bridge arm of the B phase The capacitor C - _{bu-_ i +1} is connected to the positive pole; the Kth submodule of the upper bridge arm of the B phase, its submodule capacitor C - _{bu-_ K} is positively connected to the K -1th submodule IGBT of the upper bridge arm of the B phase The midpoint of the module is connected, and the midpoint of the submodule IGBT module is connected downward to the midpoint of an IGBT module of the K +1th submodule of the upper bridge arm of the B phase; the jth submodule of the upper bridge arm of the B phase, where j is taken as The value is K +2 ~ N -1, the midpoint of one IGBT module of its sub-module is connected upwardly with the midpoint of the j -1th submodule of the upper bridge arm of phase B, and the midpoint of the other IGBT module is downwardly connected with the midpoint of the B-phase The j +1th sub-module of the upper bridge arm is connected to the midpoint of an IGBT module; the Nth submodule of the upper bridge arm of the B-phase, the midpoint of one IGBT module is upwards and the N -1th sub-module of the upper bridge arm of the B-phase is in an IGBT module The middle point of the other IGBT module is connected to the positive pole of the first sub-module capacitor C -bl _{-_1} of the lower bridge arm of the B phase through the two bridge arm reactors L ₀ downward; sub-module, wherein the value of i is 2 ~ K -1, the positive pole of the sub-module capacitor C _{-bl_ i} is connected upwardly with the middle point of the I -1th sub-module IGBT module of the lower bridge arm of the B phase, and the sub-module IGBT module The midpoint is downwardly connected to the i +1th submodule capacitor C- _{bl-_ i +1} positive pole of the lower bridge arm of the B phase; the Kth submodule of the lower bridge arm of the B phase is connected to the positive pole of the submodule capacitor C _{-bl_ K} Connect upward to the midpoint of the IGBT module of the K -1 submodule of the lower bridge arm of the B phase, and connect downward to the midpoint of the IGBT module of the K +1 submodule of the lower bridge arm of the B phase; B The jth sub-module of the lower bridge arm of the phase B, where the value of j is K +2 ~ N -1, and the midpoint of one IGBT module is connected upward to the midpoint of an IGBT module of the j -1th submodule of the lower bridge arm of the B phase, The midpoint of the other IGBT module is downwardly connected to the midpoint of the j +1th sub-module IGBT of the lower bridge arm of the B phase; the midpoint of the Nth submodule of the lower bridge arm of the B phase is upwardly connected to the midpoint of the IGBT module of the B phase The N -1th sub-module of the lower bridge arm of the phase C is connected to the midpoint of one IGBT module, and the midpoint of the other IGBT module is connected downward to the negative pole of the DC bus; the connection of the upper and lower bridge arm submodules of the C phase The connection method can be consistent with A or B; due to the existence of the full-bridge sub-module, it is not necessary to configure thyristors between the upper and lower output lines of the half-bridge sub-module; Mechanical switches K _{au_ i 1} , K _{al_ i 1 ,} K bu_ i 1 , K _{bl_ i 1} , K _{cu_ i 1} , K _{cl_ i 1} , K _{au_ j} , K _{al _j} , K _{bu_ j} are connected in parallel between the upper and lower output lines , K _{bl_ j} , K _{cu_ j} , K _{cl_ j} , where the value of i is 1~ K , and the value of j is K +1~ N ; the three-phase status of A, B, and C formed by the above-mentioned connection relationship is consistent, and the three phases Other topologies after phase rotation symmetry are within the scope of rights. 3. The auxiliary capacitor centralized half-bridge/full bridge hybrid MMC self-equalizing topology based on equality constraints according to right ₁ , characterized in that: in the self-equalizing auxiliary circuit, the positive pole of the auxiliary capacitor C1 is connected to the auxiliary IGBT module T ₁ , the negative pole is connected to the clamping diode and merged into the positive pole of the DC bus; the negative pole of the auxiliary capacitor C ₂ is connected to the auxiliary IGBT module T ₂ , and the positive pole is connected to the clamping diode and merged into the negative pole of the DC bus; the clamping diode is connected to the A phase through the auxiliary switch K _{au_12} The first sub-module capacitor C _{-au-_1} in the bridge arm is connected to the positive pole of the auxiliary capacitor C ₁ ; through the auxiliary switch K au_ i ₂ , K _{au_( i +1) 2} , connect the capacitor C _{- au-_ i} and the positive electrode of the i +1th sub-module capacitor C _{-au-_ i +1} , where the value of i is 1 to K -1; connect A through the auxiliary switch K _{au_ K 2} , T _{au_ K +1} The positive pole of the Kth sub-module capacitor C _{-au-_ K} and the K +1th submodule capacitor C- _{au_ K +1} in the upper bridge arm of the phase; connect the upper bridge arm of the A phase through the auxiliary switches T _{au_ j} and T _{au_ j +1} The positive electrode of the jth submodule capacitor C _{-au-_ j} and the j +1th submodule capacitor C _{-au-_ j +1} , where the value of j is K +1 ~ N -1; through the auxiliary switch T _{au_ N} and K _{al_12} are connected to the Nth sub-module capacitor C - _{au_ N} in the upper bridge arm of phase A and the positive pole of the first sub-module capacitor C _{-al-_1} in the lower bridge arm of phase A; through auxiliary switches K _{al_ i 2} , K _{al_ ( i +1) 2} Connect the i -th sub-module capacitor C _{-al-_ i} in the lower bridge arm of phase A to the anode of the i +1-th sub-module capacitor C _{-al-_ i +1} , where the value of i is 1～ K -1; through the auxiliary switch K _{al_ K 2} , T _{al_ K +1} , connect the Kth sub-module capacitor C - _{al-_ K} and the K +1th sub-module capacitor C - _{al-_ K +1} in the lower bridge arm of phase A Positive pole; connect the positive pole of the jth sub-module capacitor C _{-al_ j} and the j +1th sub-module capacitor C _{-al-_ j +1} in the lower bridge arm of phase A through the auxiliary switches T _{al_ j} and T _{al_} j +1, where The value of j is K +1 ~ N -1; the auxiliary switch T _{al_ N} is connected to the Nth sub-module capacitor C _{-al_ N} in the lower bridge arm of phase A and the positive pole of the auxiliary capacitor C ₂ ; the clamping diode is connected through the auxiliary switch K _{bu_12} is connected to the first sub-module capacitor C _{-bu-_1} in the upper bridge arm of phase B and the negative pole of auxiliary capacitor C ₁ ; through the auxiliary switch K _{bu_ i 2} , K _{bu_( i +1) 2} is connected to the i -th sub-module in the upper bridge arm of phase B The first sub-module capacitance C - _{bu-_ i} and the i +1th sub-module capacitance C - _{bu-_ i +1} negative pole, where the value of i is 1 to K -1; through the auxiliary switch K _{bu_ K 2} , T _{bu_ K +1} connect the Kth sub-module capacitor C - _{bu-_ K} in the upper bridge arm of phase B to the Kth +1 sub-module capacitor C - _{bu-_ K +1} negative pole; through auxiliary switches T _{bu_ j} , T _{bu_ j +1} connect the jth sub-module capacitor C - _{bu-_ j} in the upper bridge arm of phase B to the jth +1 The negative pole of each sub-module capacitor C - _{bu-_ j +1} , where the value of j is K +1 to N -1; through the auxiliary switch T _{bu_ N} , K _{bl_12} , connect the Nth sub-module capacitor C - _{bu -} _N and the first sub-module capacitor C in the lower bridge arm of phase B - _{bl_1} negative pole; through the auxiliary switch K _{bl_ i 2} , K _{bl_( i +1) 2} connect the capacitor C of the i -th sub-module in the lower bridge arm of phase B - _{bl-_ i} and the i +1th sub-module capacitor C - _{bl-_ i +1} negative pole, where the value of i is 1 to K -1; connect to B through the auxiliary switch K _{bl_ K 2} , T _{bl_ K +1} The Kth sub-module capacitor C - _{bl_ K} and the K +1th sub-module capacitor C - _{bl-_ K +1} negative pole in the lower bridge arm of the phase; connect the lower bridge arm of the B phase through the auxiliary switches T _{bl_ j} , T _{bl_ j +1} The j -th sub-module capacitor C - _{bl-_ j} and the j +1-th sub-module capacitor C - _{bl_ j +1} negative pole, where the value of j is K +1 ~ N -1; connected to B through the auxiliary switch T _{bl_ N} The Nth sub-module capacitor C _{- bl-_N} in the lower bridge arm of the phase and the negative pole of the auxiliary capacitor C ₂ ; the connection relationship of the C-phase clamping diode corresponds to the connection relationship of its sub-module; the above-mentioned A, B, C three-phase 6 N auxiliary switches K _{au_ i 2} , K _{al_ i 2 ,} K bu_ i 2 , K _{bl_ i 2} , K _{cu_ i 2} , K _{cl_ i 2} , T _{au_ j} , T al_ _j , T _{bu_ j} , T _{bl_ j} , T _{cu_ j} , T _{cl_ j} , where the value of i is 1~ K , the value of j is K +1~ N , 6 N + 5 clamping diodes, 2 auxiliary capacitors C ₁ , C ₂ and 2 Auxiliary IGBT modules T ₁ and T ₂ jointly constitute a self-equalizing auxiliary circuit. 4. The auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-equalizing topology based on equality constraints according to claim 1, characterized in that: under normal conditions, 6 N auxiliary switches K in the self-equalizing auxiliary circuit _{au_ i 2} , K _{al_ i 2 ,} K bu_ i 2 , K _{bl_ i 2} , K _{cu_ i 2} , K _{cl_ i 2} , T _{au_ j} , T al_ _j , T bu_ _j , T _{bl_ j} , T _{cu_ j} , T _{cl_ j} is normally closed, where the value of i is 1~ K , and the value of j is K +1~ N ; in case of a fault, 6 N -6 K auxiliary switches T _{au_ j} , T al_ _j , T _{bu_ j} , T _{bl_ j} , T _{cu_ j} , T _{cl_ j} are disconnected, and the value of j is K +1~ N ; under normal circumstances, when the capacitor C - _{au-_1} of the first sub-module of the upper bridge arm of phase A is bypassed, At this time, the auxiliary IGBT module T ₁ is disconnected, and the sub-module capacitor C _{-au-_1} and the auxiliary capacitor C ₁ are connected in parallel through the clamp diode; when the i -th sub-module capacitor C - _{au-_ i} of the upper bridge arm of phase A is bypassed, where The value of i is 2～ N , the sub-module capacitance C - _{au-_ i} and the sub-module capacitance C - _{au-_ i -1} are connected in parallel through the clamp diode; the first sub-module capacitance C - _{al_1} of the lower bridge arm of phase A When bypassing, the sub-module capacitor C - _{al-_1} is connected in parallel with the sub-module capacitor C- _{au-_ N} through the clamping diode and two bridge arm reactors L ₀ ; the i -th sub-module capacitor C - _{al_} When _i is bypassed, where the value of i is 2 to N , the sub-module capacitor C- _{al-_ i} and the sub-module capacitor C - _{al_ i -1} are connected in parallel through the clamp diode; when the auxiliary IGBT module T ₂ is closed, the auxiliary capacitor C ₂ is connected in parallel with the sub-module capacitor C - _{al_ N} through the clamp diode; when the auxiliary IGBT module T ₁ is closed, the auxiliary capacitor C ₁ and the sub-module capacitor C - _{bu-_1} are connected in parallel through the clamp diode; When a sub-module capacitor C - _{bu-_ i} is bypassed, where the value of i is 1 to N -1, the sub-module capacitor C - _{bu-_ i} and the sub-module capacitor C- _{bu-_ i +1} pass through the clamping diode Parallel connection; when the Nth sub-module capacitor C - _{bu_ N} of the upper bridge arm of phase B is bypassed, the sub-module capacitor C _{-bu-_ N} passes through the clamp diode, two bridge arm reactors L ₀ and the sub-module capacitor C- _{bl- _1} in parallel; when the i -th sub-module capacitor C - _{bl_ i} of the lower bridge arm of phase B is bypassed, where the value of i is 1 to N -1, the sub-module capacitor C _{-bl-_ i} and the sub-module capacitor C- _{bl_ i +1} is connected in parallel through the clamping diode; the capacitor of the Nth sub-module of the lower bridge arm of phase B is C - _{bl_ N} When bypassing, the sub-module capacitor C - _{bl-_ N} and the auxiliary capacitor C- ₂ are connected in parallel through the clamp diode; the trigger signal of the auxiliary IGBT module T ₁ is the same as the trigger signal of the first sub-module of the upper bridge arm of phase A and C The "logic sum" is consistent _; the trigger signal of the auxiliary IGBT module T2 is consistent with the trigger signal of the Nth sub-module of the lower bridge arm of the B phase; T ₁ and T ₂ are turned on and off alternately, and the capacitor voltage of the upper and lower bridge arm sub-modules of phase A satisfies the following constraints under the action of the clamp diode, U _{C 1} ≥ U _{C -au_1} ≥ U _{C -au_2} …≥ U _{C - au_ N} ≥ U _{C -al_1} ≥ U _{C -al_2} …≥ U _{C -al_ N} ≥ U _{C 2} ; under the action of the clamping diode, the capacitor voltage of the upper and lower bridge arm sub-modules of phase B satisfies the following constraints, U _{C 1} ≤ U _{C -bu_1} ≤ U _{C -bu_2} …≤ U _{C -bu_ N} ≤ U _{C -bl_1} ≤ U _{C -bl_2} …≤ U _{C -bl_ N} ≤ U _{C 2} In the bridge hybrid MMC self-balancing topology, during the dynamic process, the auxiliary capacitor C ₁ can be used as the capacitor with the highest voltage of phase A and the capacitor with the lowest voltage of phase B; the auxiliary capacitor C ₂ can be used as the capacitor with the lowest voltage of phase A , and can be used as the capacitor with the highest phase B voltage; relying on two equation constraints, max( U _{C a-} )=min( U _{C b} -), min( U _{C a} )=max( U _{C b} ), A , 4 N sub-module capacitors in the upper and lower bridge arms of phase B, C _{au_ i} , C al_ _i , C _{bu_ i} , C _{bl_ i} , where the value of i is 1 to N , and the voltage of the auxiliary capacitors C ₁ and C ₂ is at In the self-balancing state, topology A and B phases have the ability to self-balance the capacitance voltage of sub-modules; if the composition of phase C in the topology is consistent with that of phase A, the constraints of the capacitor voltage between phases C and B are the same as the constraints of the capacitor voltage between phases A and B The conditions are the same; if the configuration of phase C in the topology is consistent with that of phase B, then the constraint conditions of the capacitor voltage between A and C phases are consistent with the constraints of the capacitor voltage between A and B, and the topology has the self-balancing capability of the sub-module capacitor voltage; On the basis of clamping diodes realizing single-phase flow of capacitive energy between adjacent sub-modules in a phase, relying on the equation constraints between auxiliary capacitor voltages max ( U _{C a -} ) = min ( U _{C b} - ), min ( U _{C a} )=max( U _{C b} ), or max( U _{C a-} )=min( U _{C c} ), min( U _{C a} )=max( U _{C c} ), or max( U _{C c} )=min( U C c ) _{C b} -), min( U _{C c} )=max( U _{C b} ), realizing the interphase flow of capacitive energy to form a circulation path of capacitive energy, and then keeping the interphase sub-module capacitive voltage stable is the protection content of this right. 5. The auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-voltage equalizing topology based on equality constraints according to claim 1, characterized in that: auxiliary capacitors C ₁ and C ₂ are used as capacitor energy exchange between A and B phases The channel is also used as the channel for the energy exchange of capacitors between phases B and C; the function of the auxiliary capacitor is concentrated in the topology to reduce the consumption of devices in the self-balancing auxiliary circuit; the function of the auxiliary capacitor C ₁ is concentrated, and the function of the auxiliary capacitor C ₂ Not centralized; the function of the auxiliary capacitor C ₁ is not centralized, and the topology of the function of the auxiliary capacitor C ₂ is concentrated within the scope of rights. 6. The auxiliary capacitor centralized half-bridge/full-bridge hybrid MMC self-leveling topology based on equality constraints according to claim 1, characterized in that: the auxiliary capacitor centralized half-bridge/full-bridge hybrids based on equation constraints The MMC self-balancing topology can not only be directly applied to the field of flexible DC transmission as a multi-level voltage source converter, but also can be used to form a static synchronous compensator (STATCOM), a unified power quality conditioner (UPQC), and a unified power flow controller. (UPFC) and other devices are used in the field of flexible AC power transmission; other applications that indirectly use the topology and ideas of the invention are within the scope of rights.