CN105428407B - A kind of IGBT device and forming method thereof - Google Patents

Abstract

The present application provides an IGBT device, including: a semiconductor structure, the semiconductor structure includes a drift region, a well region, and an emission region, the top surface of the emission region is higher than the upper surface of the semiconductor structure, and the bottom surface is in contact with the semiconductor structure. The distance between the upper surface of the structure is 0-1 μm; the emitter located between the emission regions on both sides of the well region and electrically connected to the emission region, the gate region located on both sides of the emitter, and the gate region It has a stepped portion and a horizontal portion, the stepped portion and the horizontal portion are integrally structured, the horizontal portion of the gate region covers the well region and the drift region of the emitter region facing away from the emitter, the step partially covering at least part of the top surface of the emitting region. This structure avoids the impact of the "bird's beak" structure at the end of the gate region on the threshold voltage of the device, and at the same time, shortens the path of the off current in the well region, reduces loss, and avoids the latch-up effect to the greatest extent.

Description

A kind of IGBT device and its forming method

technical field

The present application relates to the technical field of semiconductors, in particular to an IGBT device and a forming method thereof.

Background technique

Insulated Gate Bipolar Transistor (IGBT for short) is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), and has a MOSFET Due to the high input impedance of the device and the low turn-on voltage drop of the power transistor (ie giant transistor, GTR for short), it is widely used in various fields.

The structure of the IGBT device in the prior art is shown in Figure 1, and a collector region 101, a buffer zone 102, a drift region 103, and a well located in the drift region and whose upper surface is flush with the upper surface of the drift region are sequentially arranged from bottom to top. region 104, the emitter 105 located in the upper surface of the well region, the emitter region 106 located in the well region and in contact with both sides of the emitter respectively, the gate covering the well region and partially covering the emitter region Region 107, wherein the gate region includes a gate and a gate oxide layer wrapped around the gate.

However, in the IGBT device with this structure, the gate oxide layer at the end of the gate region near the emitter region tends to form a "bird's beak" structure. Figure 2 is an enlarged view of the structure within the dotted line box in Figure 1, wherein 105 is the emitter part, 107 is the gate region part, and the part drawn by the dotted line circle is the "bird's beak" structure formed by the gate oxide layer. However, if the "bird's beak" structure at the end of the gate region is in contact with the well region 104 below the gate region, it will affect the threshold voltage of the device.

In order to prevent the "bird's beak" structure at the end of the gate region from affecting the threshold voltage of the device, the gate region of the "bird's beak" part is usually isolated from the well region by means of the emitter region. However, this method requires the upper surface of the emitter to completely contact the gate region of the "bird's beak", so that the lateral distance of the emitter is large, resulting in a long path for the off current to bypass the emitter (as shown in Figure 1 and Figure 3 dotted arrow), the loss is large, and it is easy to cause latch-up effect.

Contents of the invention

In order to solve the above technical problems, the embodiment of the present application provides an IGBT device and its formation method, which avoids the influence of the "bird's beak" structure at the end of the gate region on the threshold voltage of the device, and at the same time shortens the path of the turn-off current in the well region , reducing the loss and avoiding the latch-up effect to the greatest extent.

In order to solve the above problems, the embodiments of the present invention provide the following technical solutions:

An IGBT device comprising:

A semiconductor structure, the semiconductor structure includes a drift region whose upper surface is flush with the upper surface of the semiconductor structure, a well region located in the upper surface of the drift region, and located on both sides of the well region, and the top surface is high an emission region on the upper surface of the semiconductor structure, the distance between the bottom surface of the emission region and the upper surface of the semiconductor structure is 0-1 μm;

an emitter, the emitter is located between the emitter regions on both sides of the well region, and the emitter is electrically connected to the emitter region;

A gate region, the gate region is located on both sides of the emitter, the gate region has a stepped portion and a horizontal portion, the stepped portion and the horizontal portion are integrally structured, and the horizontal portion of the gate region covers the emitter The well region and the drift region on the side facing away from the emitter, and the step part covers at least part of the top surface of the emitter region.

Preferably, the included angle between the side of the stepped portion of the gate region and the horizontal portion of the gate region is 45°˜135°.

Preferably, the semiconductor structure further includes an outer well region located in the upper surface of the drift region, and the outer well region surrounds the sides and the lower surface of the well region;

The conductivity type of the outer well region is the same as that of the drift region, and the impurity doping concentration of the outer well region is greater than the impurity doping concentration of the drift region.

Preferably, the semiconductor structure further includes an inner well region located between the emitter regions on both sides of the well region, and an inner well region whose upper surface is flush with the upper surface of the well region, and the lateral direction of the inner well region having a length greater than the lateral length of the emitter;

The conductivity type of the inner well region is the same as that of the well region, and the impurity doping concentration of the inner well region is greater than the impurity doping concentration of the well region.

Preferably, the inner well region between the emitter regions has a groove structure, and the emitter is located in the groove structure.

A method for forming an IGBT device, comprising:

providing a semiconductor structure, the upper layer of the semiconductor structure being a drift region;

forming a raised portion in the upper surface of the drift region;

A gate area is formed on both sides of the raised portion, the gate area has a stepped portion and a horizontal portion, the stepped portion and the horizontal portion are integrated, and the horizontal portion of the gate area covers the side surface of the raised portion The drift region, the step part covers part of the top surface of the raised part, and the stepped parts on both sides of the raised part are not connected on the top surface of the raised part;

Doping the top surface of the protrusion with the first conductivity type to form a well region, the lateral length of the well region is greater than the lateral length of the protrusion;

Doping the top surface of the protrusion with a second conductivity type, the doping depth of the doping of the second conductivity type is different from the height of the protrusion in the range of -1 to 1 μm;

Etching the portion of the raised portion not covered by the gate region to form an emission region;

Emitter electrodes are formed between the emitter regions, and the emitter electrodes are electrically connected to the emitter regions.

Preferably, the cross section of the raised portion is an isosceles trapezoid.

Preferably, the angle between the hypotenuse and the base of the isosceles trapezoid is 45°-135°.

Preferably, after forming the raised portion and before forming the gate region, the method further includes:

Doping the upper surface of the semiconductor structure with the second conductivity type to form an outer well region, the lateral length of the outer well region is greater than the lateral length of the well region.

Preferably, after forming the gate region and before forming the well region, the method further includes:

Doping the top surface of the protrusion with the second conductivity type to form an outer well region, the lateral length of the outer well region is greater than the lateral length of the well region.

Preferably, after forming the emitter region and before forming the emitter, the method further includes:

Doping the top surface of the protrusion with the first conductivity type to form an inner well region, the lateral length of the inner well region is greater than the lateral length of the emitter and smaller than the lateral length of the protrusion.

Preferably, the etching depth of the raised portion is greater than or equal to the height of the raised portion, and less than the sum of the height of the raised portion and the doping depth of the well region.

Preferably, the etching depth of the raised portion is greater than the height of the raised portion, and smaller than the sum of the height of the raised portion and the doping depth of the inner well region.

Preferably, the formation of a raised portion on the upper surface of the drift region includes:

Etching the upper surface of the drift region to form a raised portion on the upper surface of the drift region.

Compared with prior art, the beneficial effect of the present invention is:

In the IGBT device of the present invention, the top surface of the emitter region is higher than the upper surface of the semiconductor structure, thereby raising the end of the gate region covering one side of the emitter region, so that the end point of the stepped portion of the gate region is the gate region the end of. The end point of the stepped part of the gate region is located on the top surface of the emission region, which can be separated from the well region, thereby avoiding the influence of the "bird's beak" structure at the end of the gate region on the threshold voltage of the device. At the same time, since the path of the off current in the well region surrounds the edge of the emitter region, the distance between the bottom surface of the emitter region and the upper surface of the semiconductor structure is 0-1 μm, thereby shortening the path of the off current in the well region, The loss is reduced, and the latch-up effect is avoided to the greatest extent.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 to 3 are schematic cross-sectional structure diagrams of IGBT devices in the prior art;

Fig. 4 is a schematic cross-sectional structure diagram of an IGBT device provided by Embodiment 1 of the present invention;

5 to 6 are schematic cross-sectional structure diagrams of the IGBT device provided by Embodiment 2 of the present invention;

FIG. 7 is a flow chart of a method for forming an IGBT device provided by Embodiment 3 of the present invention;

8 to 19 are schematic cross-sectional structure diagrams of IGBT devices provided by Embodiment 3 of the present invention;

20 to 21 are schematic cross-sectional structure diagrams of the IGBT device of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

As mentioned in the background art, in an IGBT device with an existing structure, the gate oxide layer at the end of the gate region near the emitter region tends to form a "bird's beak" structure. Figure 2 is an enlarged view of the structure within the dotted line box in Figure 1, wherein 105 is the emitter part, 107 is the gate region part, and the part drawn by the dotted line circle is the "bird's beak" structure formed by the gate oxide layer. However, if the "bird's beak" structure at the end of the gate region is in contact with the well region 104 below the gate region, it will affect the threshold voltage of the device.

In order to prevent the "bird's beak" structure at the end of the gate region from affecting the threshold voltage of the device, the gate region of the "bird's beak" part is usually isolated from the well region by means of the emitter region. However, this method requires the upper surface of the emitter to completely contact the gate region of the "bird's beak", so that the lateral distance of the emitter is large, resulting in a long path for the off current to bypass the emitter (as shown in Figure 1 and Figure 3 dotted arrow), the loss is large, and it is easy to cause latch-up effect.

In view of this, the present invention provides an IGBT device, comprising: a semiconductor structure, the semiconductor structure includes a drift region whose upper surface is flush with the upper surface of the semiconductor structure, and a well region located in the upper surface of the drift region , and an emitter region located on both sides of the well region and whose top surface is higher than the upper surface of the semiconductor structure, the distance between the bottom surface of the emitter region and the upper surface of the semiconductor structure is 0-1 μm; the emitter, The emitter is located between the emitter regions on both sides of the well region, and the emitter is electrically connected to the emitter region; the gate region is located on both sides of the emitter, and the gate region has steps part and a horizontal part, the step part and the horizontal part are integrally structured, the horizontal part of the gate region covers the well region and the drift region on the side of the emitter region facing away from the emitter, and the step part covers at least part of the top surface of the emission region.

In the IGBT device of the present invention, the top surface of the emitter region is higher than the upper surface of the semiconductor structure, thereby raising the end of the gate region covering one side of the emitter region, so that the end point of the stepped portion of the gate region is the gate region the end of. The end point of the stepped part of the gate region is located on the top surface of the emission region, which can be separated from the well region, thereby avoiding the influence of the "bird's beak" structure at the end of the gate region on the threshold voltage of the device. At the same time, since the path of the off current in the well region surrounds the edge of the emitter region, the distance between the bottom surface of the emitter region and the upper surface of the semiconductor structure is 0-1 μm, thereby shortening the path of the off current in the well region, The loss is reduced, and the latch-up effect is avoided to the greatest extent.

The above is the central idea of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention. rather than all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Embodiment one

This embodiment provides an IGBT device. Please refer to FIG. 4. FIG. 4 is a schematic cross-sectional structure diagram of an IGBT device according to an embodiment of the present invention, including:

A semiconductor structure, the semiconductor structure comprising a drift region 201 whose upper surface is flush with the upper surface of the semiconductor structure, a well region 202 located in the upper surface of the drift region, and located on both sides of the well region, and top The emission region 203 whose surface is higher than the upper surface of the semiconductor structure; the distance between the bottom surface of the emission region 203 and the upper surface of the semiconductor structure is 0-1 μm;

An emitter 204, the emitter is located between the emitter regions 203 on both sides of the well region, and the emitter is electrically connected to the emitter region;

Gate region, the gate region is located on both sides of the emitter, the gate region has a stepped portion 206 and a horizontal portion 207, the stepped portion and the horizontal portion are integrally structured, and the horizontal portion of the gate region covers the emitter The well region and the drift region on the side facing away from the emitter, and the step part covers at least part of the top surface of the emitter region.

Wherein, the semiconductor structure may be a silicon substrate or a silicon carbide substrate. In this embodiment, the semiconductor structure is a silicon substrate.

The drift region 201 has a second conductivity type, the well region 202 has a first conductivity type, and the emitter region 203 has a second conductivity type.

The first conductivity type may be N-type or P-type, the second conductivity type may be P-type or N-type, and polarities of the first conductivity type and the second conductivity type are opposite. That is, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type. In an embodiment of the present invention, the first conductivity type is P-type, and the second conductivity type is N-type. Wherein, the N-type ions include phosphorus ions, arsenic ions, antimony ions, etc., and the P-type ions include boron ions, etc.

In this embodiment, the drift region 201 is located in the epitaxial layer on the upper surface of the semiconductor structure, and the upper surface of the drift region is flush with the upper surface of the semiconductor structure.

The material of the drift region 201 is single crystal silicon doped with N-type impurities, such as doped with phosphorus; the well region 202 is located in the upper surface of the drift region, and the material of the well region 202 is doped with P type impurity of single crystal silicon, for example doped with boron; The upper surface is connected, the distance between the bottom surface of the emission region and the upper surface of the semiconductor structure is 0-1 μm, and the bottom surface of the emission region 203 may be 0-1 μm higher than the upper surface of the semiconductor structure, or 0-1 μm lower than the upper surface of the semiconductor structure, the material of the emitter region 203 is N-type doped single crystal silicon, for example doped with arsenic and phosphorus.

The emitter 204 is a metal electrode, which can be formed by sputtering or depositing metal materials. The emitter is located between the emission regions on both sides of the well region, and is in direct contact with the emission region to form an electrical connection.

The gate region is located on both sides of the emitter, the gate region has a stepped portion 206 and a horizontal portion 207, the stepped portion and the horizontal portion are integrally structured, and the horizontal portion of the gate region covers the emitter region facing away from For the well region and the drift region on the side of the emitter, the step part covers at least part of the top surface of the emitter region.

Wherein, the gate region includes a gate and a gate oxide layer surrounding the gate. Specifically, the gate oxide layer on the lower side of the gate can be silicon oxide, which can be formed by thermal oxidation. The gate can be polysilicon, and the gate can be formed by deposition. The gate oxide layer wrapping the upper side of the gate may be silicon oxide, and may be formed by performing thermal oxidation on the gate.

In the IGBT device of this embodiment, the top surface of the emitter region is higher than the upper surface of the semiconductor structure, thereby raising the end of the gate region covering the emitter region side, so that the end point of the stepped portion of the gate region is the gate region. end of the area. The end point of the stepped part of the gate region is located on the top surface of the emission region, so that it can be separated from the well region, and the influence of the "bird's beak" structure at the end of the gate region on the threshold voltage of the device is avoided.

At the same time, since the path of the off current in the well region surrounds the edge of the emitter region, the distance between the bottom surface of the emitter region and the upper surface of the semiconductor structure is 0-1 μm, thereby shortening the path of the off current in the well region, The loss is reduced, and the latch-up effect is avoided to the greatest extent.

In addition, in the existing technology, in order to avoid the uneven thickness of the gate oxide layer at the tip of the "bird's beak" from affecting the threshold voltage, the lateral diffusion distance of the emission region needs to be long enough, and in order to shorten the path of the off current as much as possible, the emission region needs to be The lateral diffusion distance should be as short as possible. Therefore, it is necessary to precisely control the lateral diffusion distance of the emission area, which makes the process control of this part difficult and reduces the degree of freedom in the design of the emission area.

However, in this embodiment, since the above-mentioned contradiction is resolved, the forming process of the device of this embodiment is simpler, and the difficulty of control is greatly reduced.

Embodiment two

This embodiment provides an IGBT device, please refer to FIG. 5 , which is a schematic cross-sectional structure diagram of an IGBT device according to an embodiment of the present invention.

In this embodiment, the IGBT device includes:

A semiconductor structure, the semiconductor structure comprising a drift region 301 whose upper surface is flush with the upper surface of the semiconductor structure, a well region 302 located in the upper surface of the drift region, and located on both sides of the well region, and the The well region is connected, and the top surface is higher than the emission region 303 of the upper surface of the semiconductor structure, and the distance between the bottom surface of the emission region and the upper surface of the semiconductor structure is 0-1 μm;

In this embodiment, the drift region 301 is an N- region, the well region 302 is a P well, and the emission region 303 is an N+ region.

Emitter 304, the emitter 304 is located between the emission regions 303 on both sides of the well region, the emitter is electrically connected to the emission region;

A gate region located on both sides of the emitter, the gate region has a stepped portion 306 and a horizontal portion 307, the stepped portion and the horizontal portion are integrally structured, and the horizontal portion of the gate region covers the back of the emitter region Towards the well region and the drift region on the side of the emitter, the step part covers at least part of the top surface of the emitter region 303 .

In order to further shorten the path of the turn-off current in the well region, in this embodiment, as shown in FIG. 45°-135°, so as to further shorten the path of the off current in the well region under the premise of ensuring the cross-sectional area of the emission region, thereby reducing loss and avoiding the latch-up effect to the greatest extent.

In this embodiment, in the IGBT device, the semiconductor structure further includes an outer well region 308 located in the upper surface of the drift region, and the outer well region 308 surrounds the side surfaces and the lower surface of the well region; The conductivity type of the outer well region is the same as that of the drift region, and the impurity doping concentration of the outer well region is greater than the impurity doping concentration of the drift region.

Specifically, as shown in FIG. 5, the outer well region 308 is an N well, and the outer well region can be used as a carrier storage layer. According to the principle of carrier balance, the carrier storage layer will prevent and store The holes emitted in the P+ substrate in the region can significantly reduce the on-state voltage drop, and because the holes are very close to the emitter, once they are turned off, they are quickly drawn away, so there is almost no effect on the turn-off speed influences. Therefore, the structure can achieve lower loss than the traditional IGBT, and achieve a better compromise between the on-state voltage drop and the turn-off loss.

In this embodiment, in the IGBT device, the semiconductor structure further includes an inner well located in the well region between the emitter regions on both sides of the well region, and the upper surface of which is flush with the upper surface of the well region Region 309, the lateral length of the inner well region is greater than the lateral length of the emitter; the conductivity type of the inner well region is the same as that of the well region, and the impurity doping concentration of the inner well region is greater than the The impurity doping concentration of the well region.

Specifically, as shown in FIG. 5, the inner well region 309 is a P+ region, and the doping concentration of the P+ region is higher than that of the P well 302. Since the ohmic contact characteristics of the P+ region are better than those of the P well, good electrical contact can be formed. and, the on-resistance doped in the P+ region 309 is smaller than the on-resistance doped in the P well, and the voltage drop of the current on the P+ region will be lower when it is turned off, so that the turn-off loss can be lower and more resistant to latch-up lock-in effect.

Moreover, in order to further shorten the path of the off current in the well region, in this embodiment, the inner well region between the emitter regions is a groove structure, and the emitter is located in the groove structure.

Specifically, etching may be performed between the emitting regions to form a groove structure, and an emitter electrode is formed in the groove structure.

It should be noted that during the etching process, a part of the inner well region should be reserved to maintain its corresponding function.

Due to the groove structure between the two emission regions, as shown by the dotted arrow in Figure 5, the path of the off current in the well region can be shortened, thereby further reducing losses and avoiding the latch-up effect to the greatest extent. .

In this embodiment, a buffer zone 310 , a collector region 311 and a collector electrode 312 are sequentially disposed below the drift region 301 of the semiconductor structure.

In this embodiment, because in the IGBT device of the present invention, the top surface of the emitter region is higher than the upper surface of the semiconductor structure, thereby raising the end of the gate region covering one side of the emitter region, so that the gate region steps The ends of the sections are the ends of the gate regions. The end point of the stepped part of the gate region is located on the top surface of the emission region, which can be separated from the well region, thereby avoiding the influence of the "bird's beak" structure at the end of the gate region on the threshold voltage of the device.

At the same time, since the path of the off current in the well region surrounds the edge of the emitter region, the distance between the bottom surface of the emitter region and the upper surface of the semiconductor structure is 0-1 μm, thereby shortening the path of the off current in the well region, The loss is reduced, and the latch-up effect is avoided to the greatest extent. In addition, in the existing technology, in order to avoid the uneven thickness of the gate oxide layer at the tip of the "bird's beak" from affecting the threshold voltage, the lateral diffusion distance of the emission region needs to be long enough, and in order to shorten the path of the off current as much as possible, the emission region needs to be The lateral diffusion distance should be as short as possible. Therefore, the lateral diffusion distance of the emission area needs to be precise, which makes the process control of this part difficult and reduces the degree of freedom in the design of the emission area. However, in this embodiment, since the above-mentioned contradiction is resolved, the forming process of the device of this embodiment is simpler, and the difficulty of control is greatly reduced.

Embodiment Three

This embodiment provides a method for forming an IGBT device, as shown in FIG. 7 , which is a flow chart of the method for forming an IGBT device in this embodiment, including:

Step 101: providing a semiconductor structure, the upper layer of the semiconductor structure serves as a drift region;

Step 102: forming a raised portion on the upper surface of the drift region;

Step 103: forming a gate region on both sides of the raised portion, the gate region has a stepped portion and a horizontal portion, the stepped portion and the horizontal portion are integrated, and the horizontal portion of the gate region covers the raised portion In the drift area on the side of the raised part, the step part covers part of the top surface of the raised part, and the stepped parts on both sides of the raised part are not connected on the top surface of the raised part;

Step 104: Doping the top surface of the protrusion with the first conductivity type to form a well region, the lateral length of the well region is greater than the lateral length of the protrusion;

Step 105: Doping the top surface of the protrusion with a second conductivity type, where the difference between the doping depth of the second conductivity type and the height of the protrusion is -1-1 μm;

Step 106: Etching the portion of the raised portion not covered by the gate region to form an emission region;

Step 107: Form an emitter between the emission regions, and the emitter is electrically connected to the emission region.

8 to 19 show schematic cross-sectional structures of IGBT devices according to embodiments of the present invention.

Step 101 is executed, as shown in FIG. 8 , a semiconductor structure is provided, and the upper layer of the semiconductor structure serves as a drift region 401 .

The semiconductor structure may be a silicon substrate or a silicon carbide substrate. In this embodiment, the semiconductor structure is a silicon substrate.

Specifically, the semiconductor structure is a silicon substrate with the second conductivity type. In this embodiment, the semiconductor structure is a silicon substrate with N-type impurities. Specifically, the impurity concentration of the N-type substrate is 5e12˜5e15 cm ⁻³ .

Execute step 102, forming a raised portion on the upper surface of the drift region;

Specifically, as shown in FIG. 9 , etching is performed on the drift region to form a raised portion. In this step, the etching depth is 0.1-3 μm.

In this embodiment, an etching inclination angle of 45° to 135° can be set during the etching process, so that the raised portion is an isosceles trapezoid, and the angle α between the hypotenuse and the base of the isosceles trapezoid is 45° ~135°, thus making the off-current path shorter.

Executing step 103, forming a gate region on both sides of the protrusion, the gate region has a stepped portion and a horizontal portion, the stepped portion and the horizontal portion are integrated, and the horizontal portion of the gate region covers the In the drift area on the side of the raised part, the step part covers part of the top surface of the raised part, and the stepped parts on both sides of the raised part are not connected on the top surface of the raised part.

Since the raised portion formed in step 102 is an isosceles trapezoid, and the angle α between the hypotenuse and the base of the isosceles trapezoid is 45°-135°, therefore, the side of the stepped portion of the gate region formed here is The included angle of the horizontal portion is also 45°-135°. Through this setting, the path of the off current in the well region can be further shortened, thereby reducing loss and avoiding the latch-up effect to the greatest extent.

Specifically, this step can be divided into the following steps:

Step 1031 , forming a gate oxide layer on the semiconductor structure.

Specifically, as shown in FIG. 10 , a thermal oxidation process is performed on the upper surface of the semiconductor structure to form a gate oxide layer 402 . The gate oxide layer is silicon oxide with a thickness of 50 nm˜150 nm.

Step 1032, forming a gate on the gate oxide layer.

Specifically, as shown in FIG. 11 , polysilicon is deposited on the gate oxide layer to form a gate 403 with a thickness of 0.2-2 μm. During deposition, the impurity doping concentration of the polysilicon is controlled to be 1e17˜1e21 cm ⁻³ , the doping type is N-type doping, and the impurity may be phosphorus.

Step 1033 , etching the gate on the top surface of the raised portion to form an opening on the top surface of the raised portion.

Specifically, as shown in FIG. 12 , since the opening 404 is formed on the top surface of the raised portion, the stepped portions of the gate regions on both sides of the raised portion are not connected on the top surface of the raised portion.

Step 1034, forming a gate oxide layer wrapping the upper side of the gate.

Specifically, thermal oxidation is performed to wrap the gate oxide layer on the upper side of the gate. The gate oxide layer is silicon oxide.

In this embodiment, as shown in FIG. 13 , a gate region 405 is finally formed. It can be seen that the gate region 405 is on both sides of the protrusion, and the gate region has a stepped portion and a horizontal portion. The step part and the horizontal part are integrated, the horizontal part of the gate region covers the drift area on the side of the raised part, the step part covers part of the top surface of the raised part, and the two sides of the raised part The stepped parts are not connected on the top surface of the raised part.

Execute step 104, doping the top surface of the protrusion with the first conductivity type to form a well region, the lateral length of the well region is greater than the lateral length of the protrusion.

Specifically, doping the opening portion 404 on the top layer of the protrusion with the first conductivity type to form a well region 406 .

Specifically, as shown in FIG. 14 , in this embodiment, the first conductivity type is P-type, and a P-type impurity is implanted into the opening portion of the top layer of the protrusion to push the impurity, thereby forming a well region 406 , that is, the P well.

In this embodiment, the P-type impurity is boron, the implantation energy is 10-200keV, and the dose is 5e11-1e15cm ^-2 . When impurity ions are propelled, the propelling temperature is 800-1200° C. and the time is 50-800 min.

In other embodiments of the present invention, considering the principle of saving process steps, the advancing step in this application can be combined with step 1034, that is, after step 1033 is executed, step 104 is performed, and during the advancing process of step 104, Oxygen is introduced to form a gate oxide layer wrapping the upper side of the gate. Afterwards, the oxide layer formed in the opening part is removed through an etching process.

Executing step 105, performing second conductivity type doping on the top surface of the raised portion, where the doping depth of the second conductive type doping is equal to the height of the raised portion;

Specifically, as shown in FIG. 15 , the top surface of the protrusion is doped with a second conductivity type, and the doping depth of the doping of the second conductivity type is equal to the height of the protrusion.

In this embodiment, the doping of the second conductivity type is N-type doping, and phosphorus impurities are implanted on the top surface of the protrusion, with an implantation energy of 10-200 keV and a dose of 1e12-5e16 cm ⁻² . Afterwards, carry out impurity propelling, the propelling temperature is 800-1200° C., and the time is 10-100 min.

Step 106 is executed to etch the portion of the raised portion not covered by the gate region to form an emission region.

Specifically, as shown in FIG. 16 , in this step, the portion of the raised portion not covered by the gate region is etched to form an emission region 407 .

Wherein, the etching depth of the etching is greater than or equal to the height of the raised portion. In this embodiment, the etching depth is greater than the height of the raised portion, so that the bottom surface of the emitter subsequently formed between the emitter regions is lower than the upper surface of the well region, so that the off current reaches the emitter Pole paths are shorter.

After step 106 is executed, in this embodiment, it may also include:

Step 200: Doping the top surface of the protrusion with the first conductivity type to form an inner well region, the lateral length of the inner well region is greater than the lateral length of the emitter and smaller than the lateral length of the protrusion.

Specifically, as shown in FIG. 17 , the first conductivity type is P type, and the implanted impurity may be boron. The injection energy is 10-200keV, and the dose is 1e12-5e16cm ^-2 . The advancing temperature is 800～1200℃, and the time is 50～800min.

Perform P-type doping in the inner well region to form an inner well region 408 with an impurity doping concentration greater than that of the well region, that is, a P+ region, and the lateral length of the inner well region is greater than that of the opening at the top of the raised portion. The transverse length is less than the transverse length of the raised portion. Since the ohmic contact characteristic of the P+ region is better than that of the well region 406 (P well), good electrical contact can be formed; and the on-resistance of the doping of the P+ region 408 is smaller than that of the doping of the P well. The voltage drop of the current on the P+ region will be lower, which can make the turn-off loss lower and more resistant to latch-up.

Step 107 is executed to form an emitter between the emission regions, and the emitter is electrically connected to the emission region.

Specifically, as shown in FIG. 18 , an emitter is formed on the well region between the emitter regions, and metal is deposited on the well region between the emitter regions through a deposition process, thereby forming an emitter 409 .

It should be noted that, in this embodiment, as shown in FIG. 19 , the process of forming the buffer zone 410, the collector region 411 and the collector electrode 412 should also be included, and the process can be specifically as follows:

Step 108 , doping the lower surface of the semiconductor with the second conductivity type to form a buffer zone 410 .

Specifically, N-type doping is performed on the lower surface of the semiconductor, and the implanted impurity is phosphorus. The injection energy is 10-200keV, the dose is 1e12-5e16cm ^-2 , the propelling temperature is 800-1200°C, and the time is 50-800min.

Step 109 , doping the lower surface of the semiconductor with the first conductivity type to form a collector region 411 .

Specifically, P-type doping is performed on the lower surface of the semiconductor, the impurity is boron, the implantation energy is 10-200keV, the dose is 1e12-5e16cm ^-2 , the advancing temperature is 800-1200°C, and the time is 50-800min.

Step 110 , metal deposition is performed on the lower surface of the semiconductor to form the collector electrode 412 .

Considering the principle of saving process steps, this step can be combined with step 107. Specifically, when step 107 needs to be performed, this step is skipped, until this step, metal deposition is performed to form an emitter and a collector.

In addition, in other embodiments of the present invention, the method may also perform doping of the second conductivity type on the upper surface of the semiconductor structure after step 102 or step 1033 to form an outer well region. Specifically, in this embodiment In the example, an N-well implantation region of N-type impurities is formed by ion implantation, thereby further improving the electrical performance of the device.

Wherein, the outer well region formed in step 102 is shown as region 501 in FIG. 20 , and the outer well region formed after step 1033 is shown as region 601 in FIG. 21 .

By adding an outer well region in the well region and the N-drift region, it can be used as a carrier storage layer. According to the principle of carrier balance, the carrier storage layer will prevent and store the charge from the collector region P+ substrate The emitted holes significantly reduce the on-state voltage drop, and because the holes are very close to the emitter, once they are turned off, they are quickly drawn away, so they have little effect on the turn-off speed. Therefore, the structure can achieve lower loss than the traditional IGBT, and achieve a better compromise between the on-state voltage drop and the turn-off loss.

In the IGBT device of this embodiment, the top surface of the emitter region is higher than the upper surface of the semiconductor structure, thereby raising the end of the gate region covering the emitter region side, so that the end point of the stepped portion of the gate region is the gate region. end of the area. The end point of the stepped part of the gate region is located on the top surface of the emission region, so that it can be separated from the well region, and the influence of the "bird's beak" structure at the end of the gate region on the threshold voltage of the device is avoided. At the same time, since the path of the off current in the well region surrounds the edge of the emitter region, the distance between the bottom surface of the emitter region and the upper surface of the semiconductor structure is 0-1 μm, thereby shortening the path of the off current in the well region , reducing the loss and avoiding the latch-up effect to the greatest extent.

Moreover, in this embodiment, the well region is advanced on the top surface of the protrusion. Compared with the existing manufacturing process, under the same impurity implantation dose, the P-type impurity doping under the gate oxide in this embodiment The impurity concentration will be slightly higher (because the impurity does not need to diffuse into the etched silicon area), so in order to ensure the same threshold voltage, it is necessary to reduce the P well implant dose, thereby forming a shorter well diffusion distance. The shorter the diffusion distance of the well region can shorten the conductive channel, thereby reducing the channel resistance, reducing the conduction voltage drop, and reducing the conduction loss.

It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same and similar parts in each embodiment, refer to each other, that is, Can. As for the device-type embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for related parts, please refer to part of the description of the method embodiments.

Finally, it should also be noted that in this text, relational terms such as first and second etc. are only used to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations, any such actual relationship or order exists. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

For the convenience of description, when describing the above devices, functions are divided into various units and described separately. Of course, when implementing the present invention, the functions of each unit can be implemented in one or more pieces of software and/or hardware.

The technical solution provided by this application has been introduced in detail above, and specific examples have been used in this paper to illustrate the principle and implementation of this application. The description of the above embodiments is only used to help understand the method and core idea of this application; At the same time, for those skilled in the art, based on the idea of this application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the application.

Claims (14)

1. A kind of IGBT device, is characterized in that, comprises: A semiconductor structure, the semiconductor structure includes a drift region whose upper surface is flush with the upper surface of the semiconductor structure, a well region located in the upper surface of the drift region, and located on both sides of the well region, and the top surface is high an emission region on the upper surface of the semiconductor structure, the distance between the bottom surface of the emission region and the upper surface of the semiconductor structure is 0-1 μm; an emitter, the emitter is located between the emitter regions on both sides of the well region, and the emitter is electrically connected to the emitter region; A gate region, the gate region is located on both sides of the emitter, the gate region has a stepped portion and a horizontal portion, the stepped portion and the horizontal portion are integrally structured, and the horizontal portion of the gate region covers the emitter The well region and the drift region on the side facing away from the emitter, and the step part covers at least part of the top surface of the emitter region. 2 . The device according to claim 1 , wherein an included angle between the side of the stepped portion of the gate region and the horizontal portion of the gate region is 45°˜135°. 3. The device according to claim 2, wherein the semiconductor structure further comprises an outer well region located in the upper surface of the drift region, and the outer well region surrounds the sides and the lower surface of the well region ; The conductivity type of the outer well region is the same as that of the drift region, and the impurity doping concentration of the outer well region is greater than the impurity doping concentration of the drift region. 4. The device according to claim 2, wherein the semiconductor structure further comprises a well region between the emission regions on both sides of the well region, and the upper surface is flush with the upper surface of the well region an inner well region, the lateral length of the inner well region is greater than the lateral length of the emitter; The conductivity type of the inner well region is the same as that of the well region, and the impurity doping concentration of the inner well region is greater than the impurity doping concentration of the well region. 5. The device according to claim 4, wherein the inner well region between the emitter regions has a groove structure, and the emitter is located in the groove structure. 6. A method for forming an IGBT device, comprising: providing a semiconductor structure, the upper layer of the semiconductor structure being a drift region; forming a raised portion in the upper surface of the drift region; A gate area is formed on both sides of the raised portion, the gate area has a stepped portion and a horizontal portion, the stepped portion and the horizontal portion are integrated, and the horizontal portion of the gate area covers the side surface of the raised portion The drift region, the step part covers part of the top surface of the raised part, and the stepped parts on both sides of the raised part are not connected on the top surface of the raised part; Doping the top surface of the protrusion with the first conductivity type to form a well region, the lateral length of the well region is greater than the lateral length of the protrusion; Doping the top surface of the protrusion with a second conductivity type, the doping depth of the doping of the second conductivity type is different from the height of the protrusion in the range of -1 to 1 μm; Etching the portion of the raised portion not covered by the gate region to form an emission region; Emitter electrodes are formed between the emitter regions, and the emitter electrodes are electrically connected to the emitter regions. 7. The method according to claim 6, characterized in that the cross-section of the raised portion is an isosceles trapezoid. 8. The method according to claim 7, wherein the angle between the hypotenuse and the base of the isosceles trapezoid is 45°-135°. 9. The method according to claim 8, further comprising: after forming the raised portion and before forming the gate region: Doping the upper surface of the semiconductor structure with the second conductivity type to form an outer well region, the lateral length of the outer well region is greater than the lateral length of the well region. 10. The method according to claim 8, further comprising: after forming the gate region and before forming the well region: Doping the top surface of the protrusion with the second conductivity type to form an outer well region, the lateral length of the outer well region is greater than the lateral length of the well region. 11. The method according to claim 8, further comprising: after forming the emitter region and before forming the emitter: Doping the top surface of the protrusion with the first conductivity type to form an inner well region, the lateral length of the inner well region is greater than the lateral length of the emitter and smaller than the lateral length of the protrusion. 12. The method according to claim 8, characterized in that, the etching depth of the raised portion is greater than or equal to the height of the raised portion, and less than the height of the raised portion and the well The sum of the doping depths of the regions. 13. The method according to claim 11, wherein the etching depth of the raised portion is greater than the height of the raised portion, and smaller than the height of the raised portion and the depth of the inner well. The sum of the doping depths of the regions. 14. The method according to claim 6, wherein the forming a raised portion on the upper surface of the drift region comprises: Etching the upper surface of the drift region to form a raised portion on the upper surface of the drift region.