CN105374820B - Semiconductor structure - Google Patents

Abstract

The present invention discloses a semiconductor structure for reducing contact resistance, which at least includes a substrate, a buried word line, an isolation layer, a polysilicon spacer and a contact window plug. The substrate has a plurality of trenches. The buried word line is located in the trench, wherein the top surface of the buried word line is lower than the surface of the substrate by a first distance. The isolation layer is located on the buried word line and its top surface is lower than the surface of the substrate by a second distance. The polysilicon spacer is located on the side wall of the trench on the isolation layer to directly contact the substrate. The contact window plug can increase the contact area with the substrate through the polysilicon spacer, thereby reducing the resistance between the substrate and the contact window plug. The present invention can increase the contact area between the substrate and the contact window plug, thereby reducing the contact resistance between the two.

Description

semiconductor structure

technical field

The invention relates to a semiconductor structure, and in particular to a semiconductor structure with reduced contact resistance.

Background technique

With the development of components into the nanometer generation, DRAMs face more and more difficulties. For example, as the contact area decreases, the current of the components gradually decreases. The problem is exacerbated especially when the position of the capacitor contact window is shifted slightly, reducing the contact area with the active area (AA) of the device.

The current improvement method is to adopt a linear contact window structure; that is, the capacitor contact window is changed to a linear structure to increase the contact area. However, in this way, an additional storage node structure is required to connect the line contact structure, and because more conductive materials need to be removed during the chemical mechanical polishing (CMP) manufacturing process during the manufacture of the line contact structure, it is easy to damage to peripheral components.

Contents of the invention

The invention provides a semiconductor structure, which can reduce the resistance between the substrate and the contact window plug, and avoid the problems caused by the linear contact window structure.

The semiconductor structure of the present invention at least includes a substrate having several channels, buried word lines in the channels, isolation layers located in the buried word lines, polysilicon spacers, and contact plugs, wherein one of the channels There is a substrate exposed in between. The top surface of the buried word line is lower than the surface of the substrate by a first distance, and the top surface of the isolation layer is lower than the surface of the substrate by a second distance. The polysilicon spacer is located on the sidewall of the trench on the isolation layer to directly contact the substrate. The contact plugs are located on the substrate and electrically connected with the polysilicon spacers and the substrate respectively.

In an embodiment of the present invention, the contact plug includes a capacitor contact plug.

In an embodiment of the present invention, the above-mentioned second distance is smaller than the thickness of the isolation layer.

In an embodiment of the present invention, the thickness of each polysilicon spacer is between 5 nm˜15 nm.

In an embodiment of the present invention, the above-mentioned semiconductor structure may further include an insulating layer between the substrate and the buried word line.

In an embodiment of the present invention, the above-mentioned semiconductor structure may further include a metal silicide layer located on the surface of the polysilicon spacer and in direct contact with the contact plug. The metal silicide layer includes a cobalt silicide layer, a nickel silicide layer or a titanium silicide layer.

In an embodiment of the present invention, the above-mentioned semiconductor structure may further include a bit line on the substrate and straddling the buried word line.

In an embodiment of the present invention, the above-mentioned semiconductor structure may further include a metal silicide layer on the surface of the bit line, wherein the metal silicide layer includes a cobalt silicide layer, a nickel silicide layer or a titanium silicide layer.

Based on the above, the structure of the present invention increases the contact area between the contact plug and the substrate through the polysilicon spacer (and the metal silicide layer), so the resistance between the substrate and the contact plug can be reduced, and the array element can be maintained. current flow. In addition, the present invention uses a hole-type contact window, so it does not face the problems of the current linear-type contact window.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a schematic cross-sectional view of a semiconductor structure according to a first embodiment of the present invention.

FIG. 1B is a schematic cross-sectional view of a semiconductor structure according to a second embodiment of the present invention.

2A to 2E are cross-sectional views of a manufacturing process of a semiconductor structure according to a third embodiment of the present invention.

3A to 3C are cross-sectional views of a manufacturing process of a semiconductor structure according to a fourth embodiment of the present invention.

FIG. 4A is a schematic top view of the semiconductor structure of FIG. 3A .

FIG. 4B is a schematic top view of the semiconductor structure of FIG. 3C .

Wherein, the reference signs are explained as follows:

100, 200: Substrate

100a, 200a, 220a: surface

102, 216: Embedded word lines

102a, 104a, 218a: top surface

104, 218: isolation layer

106, 220: polysilicon spacer

108, 226, 310: contact window plug

110, 208: channel

112, 230: area

114, 212: barrier layer

116, 222, 306: dielectric layer

118: insulation layer

120, 206a: hard mask

122, 202: Trench isolation structure

124, 304: metal silicide layer

204: High-density plasma oxide layer

206b: Polysilicon mask

210: silicon oxide layer

214, 300: metal layer

224, 308: contact window hole

228: Contact area

302: Silicon nitride capping layer

400: bit line

CA: contact area

d1: first distance

d2: second distance

t1, t2: Thickness

Detailed ways

FIG. 1A is a schematic cross-sectional view of a semiconductor structure according to a first embodiment of the present invention.

Referring to FIG. 1A, the semiconductor structure of this embodiment at least includes a substrate 100, a buried word line 102, an isolation layer 104 located on the buried word line 102, a polysilicon spacer 106, and a contact plug 108. The isolation Layer 104 is, for example, SiN. There are a plurality of channels 110 in the substrate 100, and regions 112 between the channels 110 are exposed. The buried word line 102 is located in the trench 110 , and its top surface 102 a is lower than the surface 100 a of the substrate 100 by a first distance d1 , such as between 80 nm˜100 nm. In addition, a barrier layer 114 such as Ti/TiN may be disposed between the buried word line 102 and the channel 110 . The isolation layer 104 is also located in the trench 110 , and the top surface 104 a of the isolation layer 104 is lower than the surface 100 a of the substrate 100 by a second distance d2 , such as between 30 nm˜40 nm. In one embodiment, the second distance d2 is smaller than the thickness t1 of the isolation layer 104 , but the invention is not limited thereto. As for the polysilicon spacer 106 , the sidewall of the trench 110 is located on the isolation layer 104 to directly contact the contact plug 108 . In another embodiment, the thickness t2 of the polysilicon spacer 106 is, for example, about 5 nm˜15 nm, but the invention is not limited thereto. The contact plug 108 is located on the substrate 100 and is electrically connected to the polysilicon spacer 106 and the region 112 of the substrate respectively, and the contact plug 108 is generally located in the dielectric layer 116 . In addition, an insulating layer 118 may be disposed between the substrate 100 and each buried word line 102 to reduce interference between the buried word lines 102 . On the substrate 100 between the trenches 110, a hard mask 120 can be provided, which is an etching mask (mask) used when making the trenches 110, and can be reserved as a part of the semiconductor structure, but the present invention does not It is limited thereto; that is, the layer of hard mask 120 can also be removed after forming the polysilicon spacer 106 . Also, the hard mask 120 is, for example, a SiN layer.

In FIG. 1A, there is a trench isolation structure 122 between two buried word lines 102 to separate the substrate 100 into at least two active regions, but the present invention is not limited thereto; in other words, Other isolation structures or no isolation structures may be provided in the substrate 100 .

In one embodiment, if the above semiconductor structure is applied to a dynamic random access memory, the contact plug 108 may be a capacitor contact plug.

1B is a schematic cross-sectional view of a semiconductor structure according to the second embodiment of the present invention, wherein the same reference numerals as those in the first embodiment are used to denote the same or similar components.

Please refer to FIG. 1B. In addition to the substrate 100, the buried word line 102, the isolation layer 104, the polysilicon spacer 106, and the contact plug 108, the semiconductor structure in this embodiment also has a layer located on the surface 106a of the polysilicon spacer 106. The metal silicide layer 124 is in direct contact with the contact plug 108 . Wherein, the metal silicide layer 124 such as cobalt silicide layer, nickel silicide layer or titanium silicide layer can further reduce the contact resistance between the region 112 of the substrate and the contact plug 108 .

Regarding the manufacture of the structure of the present invention, the following manufacturing process can be referred to, but the present invention is not limited thereto.

2A to 2E are cross-sectional views of a manufacturing process of a semiconductor structure according to a third embodiment of the present invention.

Referring to FIG. 2A , a trench isolation structure 202 defining an active region is fabricated in a substrate 200 , and a high-density plasma oxide layer 204 can be disposed on the trench isolation structure 202 . Then, a plurality of trenches 208 are etched in the substrate 200 by using the hard mask 206 a and the polysilicon mask 206 b thereon as an etching mask. The hard mask 206a is, for example, a SiN layer. Next, a silicon oxide layer 210 can be formed on the surface of the trench 208 by using a manufacturing process such as in-situ steam generation (ISSG), and the silicon oxide layer 210 can also be formed on the surface of the polysilicon mask 206b.

Then, referring to FIG. 2B , a barrier layer 212 and a metal layer 214 are sequentially formed in the trench 208 , wherein the barrier layer 212 is such as Ti/TiN, and the metal layer 214 is such as tungsten (W). Next, etch back the barrier layer 212 and the metal layer 214 to obtain the buried word line 216 .

Afterwards, referring to FIG. 2C , an isolation layer 218 is deposited in the trench 208 using such as atomic layer deposition (ALD) technology, and then the polysilicon mask 206b in FIG. 2B is used as an etching mask to etch back the isolation layer 218 until its top The surface 218 a is lower than the surface 200 a of the substrate 200 (for example, in the range of 30 nm˜40 nm), and the isolation layer 218 is, for example, SiN. Then, the polysilicon mask 206b in FIG. 2B is removed, and then the silicon oxide layer 210 exposed above the isolation layer 218 is removed by means of wet dip.

Next, referring to FIG. 2D , a polysilicon layer (not shown) is deposited, the thickness of which can be controlled between 1/10-1/3 of the diameter D of the channel 208 (for example, in the range of 5nm-15nm), so as to facilitate A spacer is subsequently formed. Then, a manufacturing process such as reactive ion etching (RIE) is performed on the polysilicon layer to form a polysilicon spacer 220 on the sidewall of the trench 208 on the isolation layer 218 .

Then, referring to FIG. 2E , after the subsequent semiconductor manufacturing process (such as making gates or bit lines, etc.), a dielectric layer 222 is deposited on the substrate 200, and then the dielectric layer 222 and a part of the hard mask 206a are formed. The contact window opening 224. Subsequently, a contact plug 226 is formed in the contact hole 224 for direct contact between the polysilicon spacer 220 and the substrate 200 . Because of the existence of the polysilicon spacer 220 , the contact region 228 between the contact plug 226 and the substrate 200 will increase the area of the polysilicon spacer 220 , thereby reducing the contact resistance therebetween.

3A to 3C are cross-sectional views of the manufacturing process of a semiconductor structure according to the fourth embodiment of the present invention, and this embodiment is continued from FIG. 2D, so some components are the same as those of the third embodiment.

Please refer to FIG. 3A , after forming the polysilicon spacer 220 , other semiconductor structures can be fabricated first, such as the bit line 400 in FIG. SiC cap layer (cap layer) 302, wherein the above metal layer 300 is eg cobalt layer, nickel layer or titanium layer.

Then, referring to FIG. 3B, the first rapid thermal processing (RTP) manufacturing process is performed to form a metal silicide layer 304 (such as CoSix, NiSix, TiSix, etc.) on the surface 220a of the polysilicon spacer 220, and at this time the bit line ( A metal silicide layer is also formed on the surface of 400) in FIG. 4A and FIG. 4B. Afterwards, the silicon nitride capping layer 302 and the remaining metal layer 300 are completely removed.

Next, please refer to FIG. 3C , a second rapid thermal processing (RTP) manufacturing process may be performed to reduce the resistance value. Then, a dielectric layer 306 is deposited on the substrate 200, and then a contact hole 308 is formed through the dielectric layer 306 and part of the hard mask 206a, and then a contact plug 310 is formed in the contact hole 308 for the metal silicide layer. 304 , the polysilicon spacer 220 is in direct contact with the substrate 200 . As seen from the top view of FIG. 4B , the contact plug 310 can pass through the polysilicon spacer 220 to increase the contact area CA with the substrate 200 .

To sum up, the present invention increases the contact area between the substrate and the contact plug through the polysilicon spacer, thereby reducing the contact resistance between the two. Therefore, when the present invention is applied to a device such as a dynamic random access memory, there is no need to make additional storage node structures to connect the substrate and the linear contact structure, and it can avoid more CMP manufacturing process separation required by the linear contact structure. In the process of making the linear contact structure into individual contact windows, it is possible to cause damage to peripheral components. In addition, the present invention can also form a metal silicide layer capable of lowering resistance on the surface of the polysilicon spacer.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. a kind of semiconductor structure, including：

One substrate has most raceway grooves；

Most embedded type word lines, position is in the raceway groove of the substrate, and the top surface of the embedded type word line is less than described One first distance of surface of substrate；

Most separation layers, are located in the raceway groove on the embedded type word line, and the top surface of the separation layer is less than One second distance of surface of the substrate；

Most polysilicon clearance walls, the side wall of the raceway groove of the position on the separation layer, to be in direct contact with the substrate； And

Most contact window plugs, position on the substrate and respectively with the polysilicon clearance wall and the electrical property of substrate phase Even.

2. semiconductor structure as described in claim 1, wherein the contact window plug includes capacitor contact window plug.

3. semiconductor structure as described in claim 1, wherein the second distance is less than the thickness of the separation layer.

4. semiconductor structure as described in claim 1, wherein the thickness of each polysilicon clearance wall 5nm~15nm it Between.

5. semiconductor structure as described in claim 1 further includes an insulating layer, it is located at the substrate and each flush type Between wordline.

6. semiconductor structure as described in claim 1 further includes most metal silicide layers, is located at the polysilicon The surface of clearance wall, and be in direct contact with the contact window plug.

7. semiconductor structure as claimed in claim 6, wherein the metal silicide layer include silicon cobalt substrate, nickel silicide layer or Titanium silicide layer.

8. semiconductor structure as described in claim 1 further includes most bit lines, position is buried on the substrate and across described Enter formula wordline.

9. semiconductor structure as claimed in claim 8 further includes most metal silicide layers, is located at the bit line Surface.

10. semiconductor structure as claimed in claim 9, wherein the metal silicide layer includes silicon cobalt substrate, nickel silicide layer Or titanium silicide layer.