CN105374681A - Transistor and manufacturing method thereof - Google Patents
Transistor and manufacturing method thereof Download PDFInfo
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- CN105374681A CN105374681A CN201410431678.5A CN201410431678A CN105374681A CN 105374681 A CN105374681 A CN 105374681A CN 201410431678 A CN201410431678 A CN 201410431678A CN 105374681 A CN105374681 A CN 105374681A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 123
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- 230000004888 barrier function Effects 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 57
- 238000009413 insulation Methods 0.000 claims description 58
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 49
- 238000005516 engineering process Methods 0.000 claims description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 26
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- 239000000377 silicon dioxide Substances 0.000 claims description 21
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- 238000002347 injection Methods 0.000 claims description 12
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- 238000005468 ion implantation Methods 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 description 15
- 230000000694 effects Effects 0.000 description 15
- 150000002500 ions Chemical class 0.000 description 15
- -1 boron ion Chemical class 0.000 description 13
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 6
- 238000010276 construction Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
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- 230000005669 field effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
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- 230000007423 decrease Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
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- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a transistor and a manufacturing method thereof. The manufacturing method of the transistor comprises the steps of providing a semiconductor substrate; forming a mask stack structure on the semiconductor substrate; forming a first groove in the semiconductor substrate on the two sides of the mask stack structure; forming an insulating barrier layer on the sidewall of the first groove; filling a stress liner layer inside the first groove; forming a dielectric layer on the stress liner layer and enabling the upper surface of the dielectric layer surface to be in flush with the upper surface of the mask stack structure; removing the mask stack structure and forming a second groove exposed out of the semiconductor substrate; forming a semiconductor layer at the bottom of the second groove; forming a gate structure on the semiconductor layer; and filling the second groove with the gate structure. Based on the above method, the performances of formed transistors are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of transistor and forming method thereof.
Background technology
The principal element affecting field-effect transistor performance is the mobility of charge carrier.In scene effect transistor, the decline of carrier mobility not only can reduce the switch speed of transistor, but also resistance difference when holding and close can be made to reduce.Therefore, in the development of complementary metal oxide semiconductor field effect transistor (CMOS), effectively improve carrier mobility and always be one of emphasis that transistor arrangement designs.
Conventionally, by P-type mos field-effect transistor (PMOS) and N-type mos field effect transistor (NMOS) separately process in cmos device manufacturing technology, such as, compression material is adopted in the manufacture method of PMOS device, and in nmos device, adopt tensile stress material, to apply suitable stress to channel region, thus improve the mobility of charge carrier.Wherein, embedded germanium silicon (SiGe) technology (being also called eSiGe technology) becomes one of major technique of PMOS stress engineering because it can apply suitable compression to channel region to improve the mobility in hole.Usually, the embedded germanium silicon introduced stress technology forming germanium silicon stressor layers in the source/drain region of PMOS transistor is adopted.
Please refer to Fig. 1, on a semiconductor substrate 100, after selective epitaxial method growth germanium silicon stressor layers 110, usually can carry out source and drain ion implantation technology (such as boron doping), for the source/drain region forming PMOS device.But, the boron ion mixed due to instantaneous enhanced diffustion effect, easily to channel region horizontal proliferation (as shown by the arrows in Figure 1, do not mark), the effective length of channel region is shortened, thus causes short-channel effect, and then the electric property of PMOS device is deteriorated.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, to improve the performance of transistor.
For solving the problem, the invention provides a kind of formation method of transistor, comprising:
Semiconductor substrate is provided;
Form mask stack stack structure on the semiconductor substrate;
The first groove is formed in the Semiconductor substrate of described mask stack stack structure both sides;
Insulation barrier is formed at the sidewall of described first groove;
Fully stress laying is filled in described first groove;
Described stress liner layer forms dielectric layer, described dielectric layer upper surface and described mask stack stack structure upper surface flush;
Remove described mask stack stack structure, until form the second groove exposing described Semiconductor substrate;
Semiconductor layer is formed at described second bottom portion of groove;
Described semiconductor layer forms grid structure, and described grid structure fills full described second groove.
Optionally, the material of described insulation barrier comprise silica and silicon nitride at least one of them.
Optionally, the thickness range of described insulation barrier is 5nm ~ 50nm.
Optionally, the thickness range of described semiconductor layer is 10nm ~ 100nm.
Optionally, adopt epitaxial growth method in described first groove, fill full described stress liner layer.
Optionally, epitaxial growth method is adopted to form described semiconductor layer at described second bottom portion of groove.
Optionally, the material of described dielectric layer is silica.
Optionally, described mask stack stack structure comprises the silicon oxide layer be positioned in described Semiconductor substrate and the silicon nitride layer be positioned on described silicon oxide layer.
Optionally, form described insulation barrier at the sidewall of described first groove to comprise:
Insulating barrier material layer is formed in the bottom of described first groove and sidewall;
Adopt anisotropic dry etch process to remove the described insulating barrier material layer being positioned at described first bottom portion of groove, remain described insulation barrier and be left described insulation barrier.
Optionally, after the described grid structure of formation, further comprising the steps of:
Remove described dielectric layer again to expose described stress liner layer;
Lightly doped drain injection technology is carried out to described stress liner layer;
After described lightly doped drain injection technology, form side wall in described grid structure both sides;
With described side wall for mask, source and drain ion implantation technology is carried out to described stress liner layer.
For solving the problem, present invention also offers a kind of transistor, comprising:
Semiconductor substrate;
Be positioned at the grid structure in described Semiconductor substrate;
Be positioned at the stress liner layer of described grid structure semiconductor substrates on two sides;
Also comprise:
Semiconductor layer between described Semiconductor substrate and described grid structure;
Semiconductor substrate below described semiconductor layer and the insulation barrier between described stress liner layer.
Optionally, the material of described insulation barrier comprise silica and silicon nitride at least one of them.
Optionally, the thickness range of described insulation barrier is 5nm ~ 50nm.
Optionally, the thickness range of described semiconductor layer is 10nm ~ 100nm.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, first form described mask stack stack structure on a semiconductor substrate, then in the Semiconductor substrate of described mask stack stack structure both sides, the first groove is formed, and form insulation barrier at the sidewall of groove, stress liner layer is adopted to fill full first groove afterwards, then now, insulation barrier can be blocked between the Semiconductor substrate below stress liner layer and described mask stack stack structure, follow-up by described mask stack stack structure removal, and form semiconductor layer on a semiconductor substrate, form grid structure on the semiconductor layer, counter stress laying carries out lightly doped drain injection technology and source and drain ion implantation technology again.In the transistor of final formation, insulation barrier is blocked in the stress liner layer side of the overwhelming majority, the ion that prevents from adulterating in stress liner layer (mainly by boron ion that source and drain ion implantation technology is adulterated) is diffused into channel region, prevent the generation of the problems such as short channel, improve the performance of transistor.
Further, the material of insulation barrier comprise silica and silicon nitride at least one of them.Silica and silicon nitride are as the material often used in semiconductor technology, and their good insulation preformance, and formation process is simply ripe, process costs is low.Therefore, when the Material selec-tion of insulation barrier is the material such as silica and silicon nitride, good insulation barrier effect can not only be played, and the effect that can reach Simplified flowsheet and reduce costs.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing transistor;
The structural representation that in the formation method of the transistor that Fig. 2 to Figure 16 provides for the embodiment of the present invention, each step is corresponding.
Embodiment
As described in background, in existing transistor, the Doped ions injected in source and drain ion implantation technology process is easily diffused into channel region, causes the hydraulic performance decline of transistor.
For this reason, the invention provides a kind of transistor and forming method thereof.Wherein, described transistor has the semiconductor layer be positioned in Semiconductor substrate, be positioned at the grid structure on semiconductor layer, be positioned at the stress liner layer of grid structure semiconductor substrates on two sides, there is in stress liner layer lightly-doped source drain region and heavily doped region, and described transistor also has the insulation barrier between Semiconductor substrate below semiconductor layer and stress liner layer, therefore, the foreign ion (such as boron ion) injected in heavily doped region is not easily diffused into channel region (channel region is arranged in the Semiconductor substrate of semiconductor layer and below thereof), therefore, the performance of described transistor improves.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of formation method of transistor, incorporated by reference to referring to figs. 2 to Figure 16.
Please refer to Fig. 2, Semiconductor substrate 200 is provided, and form mask stack stack structure (mark) on semiconductor substrate 200.
In the present embodiment, described mask stack stack structure comprises the silicon oxide layer 201 be positioned in Semiconductor substrate 200 and the silicon nitride layer 203 be positioned on silicon oxide layer 201.And described mask stack stack structure is mainly made up of silicon nitride layer 203, namely the thickness of silicon nitride layer 203 is much larger than the thickness of silicon oxide layer 201.In other embodiments of the invention, described mask stack stack structure also can be other laminated construction, the such as laminated construction etc. of silicon oxide layer 201 and photoresist layer.
In the present embodiment, the forming process of described mask stack stack structure can be: form silica material layer (not shown) on semiconductor substrate 200, described silica material layer forms silicon nitride material (not shown); Then in described silicon nitride material, form the photoresist layer (not shown) of patterning; Afterwards with described photoresist layer for mask, etch described silicon nitride material and silica material layer, the final silicon nitride layer 203 forming silicon oxide layer 201 shown in Fig. 2 and be positioned on silicon oxide layer 201.
In the present embodiment, Semiconductor substrate 200 is silicon substrate.In other embodiments of the invention, Semiconductor substrate 200 also can be germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or their laminated construction, or diamond substrate, or well known to a person skilled in the art other semiconductive material substrate.
Please refer to Fig. 3, in the Semiconductor substrate 200 of described mask stack stack structure both sides, form the first groove 205.
In the present embodiment, the process forming the first groove 205 can be: utilize described mask stack stack structure to be mask, adopts anisotropic dry etch process to etch the Semiconductor substrate 200 of described mask stack stack structure both sides, until form the first groove 205.Formed in the anisotropic dry etch process of the first groove 205, concrete processing step and process conditions are well known to those skilled in the art, and do not repeat them here.
Incorporated by reference to reference to figure 4 and Fig. 5, shown in Fig. 4, the sidewall of the first groove 205 forms insulation barrier 209 shown in Fig. 5.
Concrete, the forming process of insulation barrier 209 can be for: form the layer of insulating barrier material shown in Fig. 4 207 in the bottom of the first groove 205 and sidewall; Then anisotropic dry etch process can be adopted to remove the insulating barrier material layer 207 be positioned at bottom the first groove 205, until residue insulation barrier 209 is left insulation barrier 209 shown in Fig. 5.It should be noted that, the present embodiment eliminates the insulating barrier material layer 207 be positioned at bottom the first groove 205, therefore the Semiconductor substrate 200 bottom the first groove 205 is exposed again, is conducive to follow-up employing (selectivity) epitaxial growth method and forms stress liner layer.
The present embodiment defines insulation barrier 209 at the sidewall of the first groove 205.Different from the semi-conducting material such as silicon, germanium or SiGe, insulation barrier 209 itself has good insulation property, and therefore insulation barrier 209 pairs of conductive ions have good insulation barrier effect usually.Even and if partially conductive ion diffuse is inner to insulation barrier 209, also can not go out from insulation barrier 209 diffusion inside (and the semi-conducting materials such as aforementioned silicon, germanium or SiGe, when there being more conductive ion to be diffused into their inside, these conductive ions can be gone out from they diffusion inside).What visible employing insulation barrier 209 effectively can prevent the conductive ion of follow-up doping is diffused into channel region.
In the present embodiment, the material of insulation barrier 209 can comprise silica and silicon nitride at least one of them.Silica and silicon nitride are as the material often used in semiconductor technology, and their good insulation preformance, and formation process is simply ripe, process costs is low.Therefore, when the Material selec-tion of insulation barrier 209 is the material such as silica and silicon nitride, good insulation barrier effect can not only be played, and the effect that can reach Simplified flowsheet and reduce costs.
It should be noted that, the material no matter insulation barrier 209 specifically adopts is silica, silicon nitride or their laminated construction, its concrete formation process (i.e. the formation process of insulating barrier material layer 207 shown in above-mentioned Fig. 4) is well known to the skilled person, and does not repeat them here.
In the present embodiment, the thickness range of insulation barrier 209 is 5nm ~ 50nm.If the thickness of insulation barrier 209 is less than 5nm, then insulation barrier 209 effectively may cannot stop the diffusion of follow-up Doped ions because thickness is too thin, if and the thickness of insulation barrier 209 is greater than 50nm, defect and damage may be served to Semiconductor substrate 200 band, and cause unnecessary waste.Concrete, insulation barrier 209 can be silica structure or the silica structure of individual layer, also can be the laminated construction be made up of silica and silicon nitride, and can by they sandwich constructions of forming of overlap repeatedly.
Please refer to Fig. 6, in the first groove 205 shown in Fig. 5, fill fully stress laying 211.After first groove 205 fills fully stress laying 211, between the Semiconductor substrate 200 of insulation barrier 209 below stress liner layer 211 and described mask stack stack structure.
In the present embodiment, the transistor formed can be PMOS transistor, and therefore, the material of stress liner layer 211 can be germanium silicon, thus makes stress liner layer 211 can provide (compression) effect of stress accordingly to Semiconductor substrate 200.The method forming stress liner layer 211 can be epitaxial growth method, and epitaxial growth method can make the effect of stress of stress liner layer 211 act on Semiconductor substrate 200 better.
Mention before the present embodiment, insulation barrier 209 is formed by removing the insulating barrier material layer 207 (please refer to Fig. 4) be positioned at bottom the first groove 205, and the removal insulating barrier material layer 207 be positioned at bottom the first groove 205 also plays another effect, that is: expose the Semiconductor substrate 200 bottom the first groove 205.And after Semiconductor substrate 200 bottom the first groove 205 exposes, just in this step, the Semiconductor substrate 200 Epitaxial growth stress liner layer 211 of epitaxial growth method bottom the first groove 205 can be adopted, thus fill and expire the first groove 205.
Incorporated by reference to reference to figure 7 and Fig. 8, stress liner layer 211 forms dielectric layer 215 shown in Fig. 8, dielectric layer 215 upper surface and described mask stack stack structure upper surface flush.
Concrete, the forming process of dielectric layer 215 can be for: on stress liner layer 211 and described mask stack stack structure, form layer of dielectric material 213 shown in Fig. 7; Then chemical mechanical milling method can be adopted to remove the layer of dielectric material 213 being positioned at more than described mask stack stack structure upper surface, until remaining media material layer 213 retains become dielectric layer 215 shown in Fig. 8.
In the present embodiment, the material of dielectric layer 215 (i.e. layer of dielectric material 213) can be silica.Because described mask stack stack structure is mainly made up of silicon nitride layer 203, when the material of dielectric layer 215 is silica, the material of dielectric layer 215 is different from the main material of described mask stack stack structure, is conducive to the removal of follow-up described mask stack stack structure.
Please refer to Fig. 9, remove described mask stack stack structure shown in Fig. 8, until form the second groove 217 of exposing semiconductor substrate 200.
In the present embodiment, the concrete removal process of described mask stack stack structure can be, first etching removes silicon nitride layer 203, such as phosphoric acid solution etching can be adopted to remove silicon nitride layer 203 (now dielectric layer 215 is substantially unaffected), and etching stopping is on silicon oxide layer 201; Then residual silicon oxide layer 201 is removed (this step can lose certain media layer 215 in the same time), Semiconductor substrate 200 surface of etching stopping bottom the second formed groove 217.
Please continue to refer to Fig. 9, after formation second groove 217, the upper surface of stress liner layer 211, higher than Semiconductor substrate 200 upper surface exposed bottom the second groove 217, namely there is difference in height (mark) between two upper surfaces, and this difference in height is 10nm ~ 100nm usually.Meanwhile, this difference in height is basic equal with the thickness of silicon oxide layer 201.
Please refer to Figure 10, bottom the second groove 217, form semiconductor layer 219.
In the present embodiment, the channel region produced in the subsequent transistor course of work is mainly positioned at semiconductor layer 219 region, and described channel region can also be positioned at Semiconductor substrate 200 region below semiconductor layer 219 simultaneously.
In the present embodiment, epitaxial growth method can be adopted bottom the second groove 217 to form semiconductor layer 219, i.e. semiconductor layer 219 epitaxial growth from Semiconductor substrate 200 upper surface exposed bottom the second groove 217.Epitaxial growth method is adopted to have advantage: Semiconductor substrate 200 is directly from Semiconductor substrate 200 Epitaxial growth be positioned in the middle of stress liner layer 211, and this part Semiconductor substrate 200 is subject to the effect of stress of both sides stress liner layer 211, therefore therefore the semiconductor layer 219 of subsequent growth also can obtain corresponding effect of stress.In addition, when the side of semiconductor layer 219 contacts with both sides stress liner layer 211, because lattice does not mate, the stress liner layer 211 of both sides also directly can produce effect of stress to semiconductor layer 219, thus the mobility of charge carrier in raising channel region, and then improve the performance of transistor.
In the present embodiment, the thickness range of semiconductor layer 219 is 10nm ~ 100nm.If the thickness of semiconductor layer 219 is greater than 100nm, then to exceed the upper surface of both sides stress liner layer 211 more for semiconductor layer 219, and cause the effect of stress of stress liner layer 211 pairs of semiconductor layer 219 to weaken, stress liner layer 211 loses corresponding effect; And if the thickness of semiconductor layer 219 is less than 10nm, the side of semiconductor layer 219 and stress liner layer 211 contact area of both sides can be little, and same impact causes the effect of stress of stress liner layer 211 pairs of semiconductor layer 219.
Incorporated by reference to reference to Figure 11 and Figure 12, semiconductor layer 219 shown in Figure 11 forms grid structure shown in Figure 12, grid structure fills the second groove 217 shown in full Figure 10.Grid structure comprises gate dielectric layer 221 and grid layer 225.
Concrete, the forming process of grid structure can be for: bottom the second groove 217 shown in Figure 10, form gate dielectric layer 221, the material of gate dielectric layer 221 can be silica; Then adopt gate material layer 223 to fill full second groove 217, and gate material layer 223 cover the upper surface of dielectric layer 215 simultaneously; Afterwards, chemical mechanical milling method can be adopted to remove the gate material layer 223 being positioned at dielectric layer 215 upper surface, and remaining gate material layer 223 is left grid layer 225, and wherein the material of grid layer 225 can be polysilicon.
Please refer to Figure 13, remove dielectric layer 215 shown in Figure 12 again to expose stress liner layer 211.
In the present embodiment, hydrofluoric acid can be adopted to remove dielectric layer 215.
Please refer to Figure 14, counter stress laying 211 carries out light dope (source) and leaks injection technology (LDD), forms lightly-doped source drain region 227, can carry out annealing process to activate corresponding Doped ions after doping.
Lightly doped drain injection technology can make the impurity of injection be positioned at the position being close to edge, channel region, for source-drain area provides impurity concentration gradient, reduce the electric field between knot and channel region, the maximum field position in knot is separated with the maximum current path in raceway groove, can hot carrier be prevented.
In the present embodiment, the transistor formed can be PMOS transistor, and when counter stress laying 211 carries out lightly doped drain injection technology, the foreign ion injected can be boron ion (boron ion can be produced by boron simple substance or boron difluoride).
Please refer to Figure 15, after lightly doped drain injection technology, form side wall 229 in grid structure both sides.
In the present embodiment, the material of side wall 229 can be silicon nitride.
Please refer to Figure 16, with side wall 229 for mask, counter stress laying 211 carries out source and drain ion implantation technology, forms heavily doped region 231, can carry out annealing process to activate corresponding Doped ions after doping.
In the present embodiment, the transistor formed can be PMOS transistor, and when counter stress laying 211 carries out source and drain ion implantation technology, the foreign ion injected can be boron ion.
It should be noted that, the boron ion concentration that source and drain ion implantation technology is injected is larger, in the transistor that existing method is formed, the boron ion that this injection technology is injected easily is diffused into channel region, and the diffusion of boron ion is strong, and the boron ion in heavily doped region 231 is serious to the horizontal proliferation of channel region.But in the present embodiment, due to the existence of insulation barrier 209, it can prevent boron ion diffuse in heavily doped region 231 to channel region well, thus improves the quality of the PMOS transistor formed.
In the formation method of transistor provided by the present invention, first form described mask stack stack structure on semiconductor substrate 200, then in the Semiconductor substrate 200 of described mask stack stack structure both sides, the first groove 205 is formed, and form insulation barrier 209 at the sidewall of groove, stress liner layer 211 is adopted to fill full first groove 205 afterwards, then now, insulation barrier 209 can be blocked between the Semiconductor substrate 200 below stress liner layer 211 and described mask stack stack structure, follow-up by described mask stack stack structure removal, and form semiconductor layer 219 on semiconductor substrate 200, semiconductor layer 219 forms grid structure, counter stress laying 211 carries out lightly doped drain injection technology and source and drain ion implantation technology again.In the transistor of final formation, insulation barrier 209 is blocked in stress liner layer 211 side of the overwhelming majority, the ion of doping (mainly by boron ion that source and drain ion implantation technology is adulterated) is prevented in stress liner layer 211 to be diffused into channel region, prevent the generation of the problems such as short channel, improve the performance of transistor.
The embodiment of the present invention also provides a kind of transistor, and the formation method that described transistor can adopt previous embodiment to provide is formed, therefore, and can with reference to previous embodiment corresponding contents.
Concrete, please refer to Figure 16, described transistor comprises Semiconductor substrate 200, be positioned at the grid structure (grid layer 225 that described grid structure comprises gate dielectric layer 221 and is positioned on gate dielectric layer 221) in Semiconductor substrate 200, be positioned at the side wall 229 of grid both sides, be positioned at the stress liner layer 211 of grid structure semiconductor substrates on two sides 200, there is in stress liner layer 211 lightly-doped source drain region 227 and heavily doped region 231.Described transistor also comprises the semiconductor layer 219 between Semiconductor substrate 200 and grid structure, and Semiconductor substrate 200 below semiconductor layer 219 and the insulation barrier 209 between stress liner layer 211.
In the present embodiment, the material of insulation barrier 209 can comprise silica and silicon nitride at least one of them.The thickness range of insulation barrier 209 can be 5nm ~ 50nm.The thickness range of semiconductor layer 219 can be 10nm ~ 100nm.The selection reason of concrete above-mentioned material and thickness can with reference to previous embodiment corresponding contents.
In the transistor that the present embodiment provides, there is the semiconductor layer 219 be positioned in Semiconductor substrate 200, be positioned at the grid structure on semiconductor layer 219, be positioned at the stress liner layer 211 of grid structure semiconductor substrates on two sides 200, there is in stress liner layer 211 lightly-doped source drain region 227 and heavily doped region 231, and described transistor also has the insulation barrier 209 between Semiconductor substrate 200 below semiconductor layer 219 and stress liner layer 211, therefore, the foreign ion (such as boron ion) injected in heavily doped region 231 is not easily diffused into channel region (channel region is arranged in the Semiconductor substrate 200 of semiconductor layer 219 and below thereof), therefore, the performance of described transistor improves.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Form mask stack stack structure on the semiconductor substrate;
The first groove is formed in the Semiconductor substrate of described mask stack stack structure both sides;
Insulation barrier is formed at the sidewall of described first groove;
Fully stress laying is filled in described first groove;
Described stress liner layer forms dielectric layer, described dielectric layer upper surface and described mask stack stack structure upper surface flush;
Remove described mask stack stack structure, until form the second groove exposing described Semiconductor substrate;
Semiconductor layer is formed at described second bottom portion of groove;
Described semiconductor layer forms grid structure, and described grid structure fills full described second groove.
2. the formation method of transistor as claimed in claim 1, is characterized in that, the material of described insulation barrier comprise silica and silicon nitride at least one of them.
3. the formation method of transistor as claimed in claim 1 or 2, it is characterized in that, the thickness range of described insulation barrier is 5nm ~ 50nm.
4. the formation method of transistor as claimed in claim 1, it is characterized in that, the thickness range of described semiconductor layer is 10nm ~ 100nm.
5. the formation method of transistor as claimed in claim 1, is characterized in that, adopts epitaxial growth method in described first groove, fill full described stress liner layer.
6. the formation method of transistor as claimed in claim 1, is characterized in that, adopts epitaxial growth method to form described semiconductor layer at described second bottom portion of groove.
7. the formation method of transistor as claimed in claim 1, it is characterized in that, the material of described dielectric layer is silica.
8. the formation method of transistor as claimed in claim 1, is characterized in that, described mask stack stack structure comprises the silicon oxide layer be positioned in described Semiconductor substrate and the silicon nitride layer be positioned on described silicon oxide layer.
9. the formation method of transistor as claimed in claim 1, is characterized in that, form described insulation barrier comprise at the sidewall of described first groove:
Insulating barrier material layer is formed in the bottom of described first groove and sidewall;
Adopt anisotropic dry etch process to remove the described insulating barrier material layer being positioned at described first bottom portion of groove, remain described insulation barrier and be left described insulation barrier.
10. the formation method of transistor as claimed in claim 1, is characterized in that, after the described grid structure of formation, further comprising the steps of:
Remove described dielectric layer again to expose described stress liner layer;
Lightly doped drain injection technology is carried out to described stress liner layer;
After described lightly doped drain injection technology, form side wall in described grid structure both sides;
With described side wall for mask, source and drain ion implantation technology is carried out to described stress liner layer.
11. 1 kinds of transistors, comprising:
Semiconductor substrate;
Be positioned at the grid structure in described Semiconductor substrate;
Be positioned at the stress liner layer of described grid structure semiconductor substrates on two sides;
It is characterized in that, also comprise:
Semiconductor layer between described Semiconductor substrate and described grid structure;
Semiconductor substrate below described semiconductor layer and the insulation barrier between described stress liner layer.
12. transistors as claimed in claim 11, is characterized in that, the material of described insulation barrier comprise silica and silicon nitride at least one of them.
13. transistors as described in claim 11 or 12, it is characterized in that, the thickness range of described insulation barrier is 5nm ~ 50nm.
14. transistors as claimed in claim 11, is characterized in that, the thickness range of described semiconductor layer is 10nm ~ 100nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410431678.5A CN105374681A (en) | 2014-08-28 | 2014-08-28 | Transistor and manufacturing method thereof |
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| CN101924139A (en) * | 2010-06-25 | 2010-12-22 | 北京大学 | A kind of strained channel field effect transistor and its preparation method |
| CN103383962A (en) * | 2012-05-03 | 2013-11-06 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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| CN101924139A (en) * | 2010-06-25 | 2010-12-22 | 北京大学 | A kind of strained channel field effect transistor and its preparation method |
| CN103383962A (en) * | 2012-05-03 | 2013-11-06 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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