CN105357070A - FPGA-based ARINC818 bus analysis and test apparatus - Google Patents
FPGA-based ARINC818 bus analysis and test apparatus Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40026—Details regarding a bus guardian
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40117—Interconnection of audio or video/imaging devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/04—Processing captured monitoring data, e.g. for logfile generation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0811—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking connectivity
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Abstract
The invention belongs to the technical field of avionics, and specifically relates to an FPGA-based ARINC818 bus analysis and test apparatus; the analysis and test apparatus is mainly applied to an avionics digital video transmission system and capable of realizing simulation testing and debugging analysis on ARINC818 bus equipment. Compared with the prior art, the FPGA-based ARINC818 bus analysis and test apparatus has the following advantages: (1) the FPGA-based ARINC818 bus analysis and test apparatus can output FC (fiber channel) video stream meeting the ARINC818 standard according to an interface control protocol,and the FC video stream is used as a test source of ARINC818 bus receiving products; (2) the FPGA-based ARINC818 bus analysis and test apparatus can receive and store the ARINC818 video stream in the FC for realizing protocol conformity analysis on video transmission products of the ARINC818 bus interface; and (3) the FPGA-based ARINC818 bus analysis and test apparatus can realize the substantialization of main logics through protocol processing by the field-programmable gate array (FPGA). Therefore, the FPGA-based ARINC818 bus analysis and test apparatus has the characteristics of simple hardware, high integration level, low cost, high expandability and the like.
Description
Technical field
The invention belongs to avionics field, be specifically related to a kind of ARINC818 bus analysis based on FPGA and testing apparatus, it is mainly used in Aviation Digital Video transmission system, can realize the emulation testing to ARINC818 bus apparatus and Commissioning Analysis.
Background technology
ARINC818 is as Aviation Digital video bus (AvionicsDigitalVideoBus of new generation, ADVB) standard, formulate based on FC-AV (FibreChannel-AudioVideo) agreement, optical-fibre channel can be mapped in, inherit the advantages such as the high-resolution of FC-AV agreement, high reliability, low delay and electromagnetism interference performance are strong, meet the transmission demand of the real-time uncompressed video of air line high speed.
The auxiliary plan serious loss such as emulation testing, Commissioning Analysis, Support needed for the equipment development of current Domestic support ARINC818 standard, can only rely on complicated and Commercial fibers passage (FC) the protocal analysis equipment of redundancy of expensive foreign, function.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention: for agreement accordance and the reliability requirement of ARINC818 bus product, how realize the analysis and test function of ARINC818 bus based on FPGA technology, produce ARINC818 bus product for design and provide effective emulation testing, Commissioning Analysis instrument.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of ARINC818 bus analysis based on FPGA and method of testing, it is implemented based on ARINC818 bus analysis and testing apparatus, described device, for realizing the analysis and test function to ARINC818 bus, comprises the driving source function collection analysis function of ARINC818 bus and simulation being met to ARINC818 bus standard;
Specifically, described ARINC818 bus analysis and testing apparatus comprise: PCIe bus control module, encourage to inject and controls receive and dispatch and 8B/10B coding/decoding module and photoelectric conversion module with memory module, original parallel data memory module, protocol parameter injection module, excited data memory module, high speed serialization with status control module, ARINC818 framing module, ARINC818 frame parsing module, state, in conjunction with massive store unit realize to the collection analysis function of ARINC818 bus with simulate the driving source function meeting ARINC818 bus standard;
Wherein, the collection analysis function of described ARINC818 bus is injected by PCIe bus control module, excitation and status control module, high speed serialization are received and dispatched and 8B/10B coding/decoding module, ARINC818 frame parsing module, state control to realize with memory module, original parallel data memory module; Wherein, ARINC818 frame parsing module is the core of Data Analysis Services; State to control with memory module by Link Status register, gathers control register and form; Original parallel data memory module controls massive store unit and stores original parallel data, vessel head and frame head, load data respectively;
The FC driving source function that described simulation meets ARINC818 bus standard is injected by PCIe bus control module, excitation and receive and dispatch with status control module, protocol parameter injection module, excited data memory module, ARINC818 framing module, high speed serialization and 8B/10B coding/decoding module realizes; Wherein ARINC818 framing module is made up of synchronous control unit, data buffer storage FIFO, ARINC818 framing state machine as the core of protocol processes;
The described ARINC818 bus analysis based on FPGA and method of testing comprise following process:
(1) process realizing the collection analysis function of ARINC818 bus is as follows:
Step S1: the ARINC818 bus data be mapped in optical-fibre channel converts high-speed differential serial signal to by photoelectric conversion module, carries out unstringing with 8B/10B coding/decoding module and 8B/10B process of decoding obtains original parallel data flow through high speed serialization transmitting-receiving;
Step S2:ARINC818 frame parsing module processes original parallel data flow, from detection ARINC818 protocol frame SOF primitive, completes the parsing of frame head and vessel head, the recovery of load data, CRC check operation successively; State controls with memory module according to the real-time result of the instruction gathered in control register in conjunction with ARINC818 frame parsing module, the corresponding Link Status register of set also provides control command to ensure the effective analysis to ARINC818 bus failure situation, typical fault process comprises: 1. when 8B/10B decoding error being detected, 8B/10B decoding error position in set Link Status register the high speed serialization that resets transmitting-receiving and 8B/10B coding/decoding module, control original parallel data memory module simultaneously and stop stored record; 2. when link lock-out being detected, controlling original parallel data memory module and stopping record immediately, lose sync bit in set Link Status register and the ARINC818 frame parsing module that resets is waited for and again obtained link synchronization until next SOFi arrives; 3., when CRC check mistake being detected, crc error position in set Link Status register, controls the stored record that original parallel data memory module keeps original parallel data, vessel head and frame head data, not stored record load data; 4. when EOF mistake being detected, EOF error bit in a set Link Status register;
Step S3: excitation is injected and status control module realizes buffer memory Link Status register and gathers control register internal memory, the storage of original parallel data memory module Synchronization Control original parallel data, vessel head and frame head, load data;
Step S4: excitation injection is transferred to host computer respectively with status control module collection analysis function related register, each data block of original parallel data storage by PCIe bus control module, the state information gathered in host computer and analyze and initial data simultaneous display, and complete deposit in the form of a file;
(2) realize simulating the process meeting the FC driving source function of ARINC818 standard as follows:
Step T1: functional realiey process and ARINC818 bus collection analysis process contrary, the ARINC818 protocol parameter of host computer setting is transferred to excitation by PCIe bus control module and injects and status control module, the system configuration parameter needed for the function of analog stimulus source is extracted by protocol parameter injection module, the simulation load data that host computer is selected then directly are transferred in excited data memory module by PCIe bus control module, for ARINC818 framing module;
Step T2: synchronous control unit is according to the set point of ARINC818 protocol parameter, generate synchronous sequence control signal, ADVB frame head, vessel head and auxiliary data or the load data read from data buffer storage FIFO, the CRC check value that calculates in real time are combined between SOF, EOF and form complete ARINC818 data frame data stream by ARINC818 framing state machine successively;
Step T3:ARINC818 data frame data flows through high speed serialization transmitting-receiving and obtains high-speed differential serial signal with 8B/10B coding/decoding module, then is mapped in optical-fibre channel by photoelectric conversion module, and final realization meets the simulation of the FC driving source of ARINC818 standard.
(3) beneficial effect
Compared with prior art, advantage of the present invention is as follows:
(1) the present invention can export according to Interface Controller agreement the FC video flowing meeting ARINC818 standard, receives the test source of product as ARINC818 bus.
(2) the present invention can receive and store ARINC818 video flowing in FC, realizes the agreement accordance analysis of the transmission of video product to ARINC818 bus interface.
(3) the present invention utilizes field programmable gate array (FPGA) to realize the hypostazation of protocol processes main logic, has hardware simple, the features such as integrated level is high, and cost is low, and extensibility is strong.
Accompanying drawing explanation
Fig. 1 is overall logic function and specific implementation schematic diagram.
Fig. 2 is ARINC818 bus collection analysis principle schematic.
Fig. 3 is ARINC818 frame process of analysis schematic diagram.
Fig. 4 is ARINC818 bus exiting principle schematic diagram.
Fig. 5 is ARINC818 framing state machine diagram.
Embodiment
For making object of the present invention, content and advantage clearly, below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
For solving the problem of prior art, as Fig. 1-Fig. 5, the invention provides a kind of ARINC818 bus analysis based on FPGA and method of testing, it is implemented based on ARINC818 bus analysis and testing apparatus, described device adopts field programmable gate array (FPGA) in conjunction with power clock reseting logic, massive store unit, opto-electronic conversion logic etc., for realizing the analysis and test function to ARINC818 bus, comprise the driving source function collection analysis function of ARINC818 bus and simulation being met to ARINC818 bus standard;
Specifically, described ARINC818 bus analysis and testing apparatus comprise: PCIe bus control module, encourage to inject and controls receive and dispatch and 8B/10B coding/decoding module and photoelectric conversion module with memory module, original parallel data memory module, protocol parameter injection module, excited data memory module, high speed serialization with status control module, ARINC818 framing module, ARINC818 frame parsing module, state, in conjunction with massive store unit realize to the collection analysis function of ARINC818 bus with simulate the driving source function meeting ARINC818 bus standard;
Wherein, the collection analysis function of described ARINC818 bus is injected by PCIe bus control module, excitation and status control module, high speed serialization are received and dispatched and 8B/10B coding/decoding module, ARINC818 frame parsing module, state control to realize with memory module, original parallel data memory module; Wherein, ARINC818 frame parsing module is the core of Data Analysis Services; State to control with memory module by Link Status register, gathers control register and form; Original parallel data memory module controls massive store unit and stores original parallel data, vessel head and frame head, load data respectively;
The FC driving source function that described simulation meets ARINC818 bus standard is injected by PCIe bus control module, excitation and receive and dispatch with status control module, protocol parameter injection module, excited data memory module, ARINC818 framing module, high speed serialization and 8B/10B coding/decoding module realizes; Wherein ARINC818 framing module forms primarily of synchronous control unit, data buffer storage FIFO, ARINC818 framing state machine as the core of protocol processes;
As shown in Figure 1, the described ARINC818 bus analysis based on FPGA and method of testing comprise following process:
(1) process realizing the collection analysis function of ARINC818 bus is as follows:
Step S1: the ARINC818 bus data be mapped in optical-fibre channel converts high-speed differential serial signal to by photoelectric conversion module, carries out unstringing with 8B/10B coding/decoding module and 8B/10B process of decoding obtains original parallel data flow through high speed serialization transmitting-receiving;
Step S2: as shown in Figure 2, ARINC818 frame parsing module processes original parallel data flow, according to flow process shown in Fig. 3, from detection ARINC818 protocol frame SOF primitive, complete the operation such as recovery, CRC check of the parsing of frame head and vessel head, load data successively; State controls with memory module according to the real-time result of the instruction gathered in control register in conjunction with ARINC818 frame parsing module, the corresponding Link Status register of set also provides control command to ensure the effective analysis to ARINC818 bus failure situation, typical fault process comprises: 1. when 8B/10B decoding error being detected, 8B/10B decoding error position in set Link Status register the high speed serialization that resets transmitting-receiving and 8B/10B coding/decoding module, control original parallel data memory module simultaneously and stop stored record; 2. when link lock-out being detected, controlling original parallel data memory module and stopping record immediately, lose sync bit in set Link Status register and the ARINC818 frame parsing module that resets is waited for and again obtained link synchronization until next SOFi arrives; 3. when CRC check mistake being detected, crc error position in set Link Status register, control the stored record that original parallel data memory module keeps original parallel data, vessel head (ContainerHeader) and frame head (FrameHeader) data, not stored record load data; 4. when EOF mistake being detected, EOF error bit in a set Link Status register;
Step S3: excitation is injected and status control module realizes buffer memory Link Status register and gathers control register internal memory, the storage of original parallel data memory module Synchronization Control original parallel data, vessel head and frame head, load data;
Step S4: excitation injection is transferred to host computer respectively with status control module collection analysis function related register, each data block of original parallel data storage by PCIe bus control module, the state information gathered in host computer and analyze and initial data simultaneous display, and complete deposit in the form of a file;
(2) realize simulating the process meeting the FC driving source function of ARINC818 standard as follows:
Step T1: functional realiey process and ARINC818 bus collection analysis process contrary, the ARINC818 protocol parameter of host computer setting is transferred to excitation by PCIe bus control module and injects and status control module, the system configuration parameter needed for the function of analog stimulus source is extracted by protocol parameter injection module, the simulation load data (VideoData) that host computer is selected then directly are transferred in excited data memory module by PCIe bus control module, for ARINC818 framing module;
Step T2: synchronous control unit is according to the set point of ARINC818 protocol parameter, generate synchronous sequence control signal, according to as shown in Figure 5, ADVB frame head, vessel head and auxiliary data (AncillaryData) or the load data (VideoData) read from data buffer storage FIFO, the CRC check value that calculates in real time are combined between SOF, EOF and form complete ARINC818 data frame data stream by ARINC818 framing state machine successively;
Step T3:ARINC818 data frame data flows through high speed serialization transmitting-receiving and obtains high-speed differential serial signal with 8B/10B coding/decoding module, be mapped in optical-fibre channel (FC) by photoelectric conversion module again, final realization meets the simulation of the FC driving source of ARINC818 standard.
In sum, the present invention in instantiation with technical grade high-quality FPGA device for core, the corresponding power supply of periphery configure, clock, reset, opto-electronic conversion and massive store (DDR2) module, realize excitation and inject with state controls, ARINC818 framing, ARINC818 frame are resolved, high speed serialization is received and dispatched and the main functional modules such as 8B/10B encoding and decoding in FPGA inside; Meet the emulation testing to ARINC818 bus apparatus and Commissioning Analysis functional requirement, the advantages such as have integrated level high, cost is low, and extensibility is strong.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and distortion, these improve and distortion also should be considered as protection scope of the present invention.
Claims (1)
1. the ARINC818 bus analysis based on FPGA and method of testing, it is characterized in that, it is implemented based on ARINC818 bus analysis and testing apparatus, described device, for realizing the analysis and test function to ARINC818 bus, comprises the driving source function collection analysis function of ARINC818 bus and simulation being met to ARINC818 bus standard;
Specifically, described ARINC818 bus analysis and testing apparatus comprise: PCIe bus control module, encourage to inject and controls receive and dispatch and 8B/10B coding/decoding module and photoelectric conversion module with memory module, original parallel data memory module, protocol parameter injection module, excited data memory module, high speed serialization with status control module, ARINC818 framing module, ARINC818 frame parsing module, state, in conjunction with massive store unit realize to the collection analysis function of ARINC818 bus with simulate the driving source function meeting ARINC818 bus standard;
Wherein, the collection analysis function of described ARINC818 bus is injected by PCIe bus control module, excitation and status control module, high speed serialization are received and dispatched and 8B/10B coding/decoding module, ARINC818 frame parsing module, state control to realize with memory module, original parallel data memory module; Wherein, ARINC818 frame parsing module is the core of Data Analysis Services; State to control with memory module by Link Status register, gathers control register and form; Original parallel data memory module controls massive store unit and stores original parallel data, vessel head and frame head, load data respectively;
The FC driving source function that described simulation meets ARINC818 bus standard is injected by PCIe bus control module, excitation and receive and dispatch with status control module, protocol parameter injection module, excited data memory module, ARINC818 framing module, high speed serialization and 8B/10B coding/decoding module realizes; Wherein ARINC818 framing module is made up of synchronous control unit, data buffer storage FIFO, ARINC818 framing state machine as the core of protocol processes;
The described ARINC818 bus analysis based on FPGA and method of testing comprise following process:
(1) process realizing the collection analysis function of ARINC818 bus is as follows:
Step S1: the ARINC818 bus data be mapped in optical-fibre channel converts high-speed differential serial signal to by photoelectric conversion module, carries out unstringing with 8B/10B coding/decoding module and 8B/10B process of decoding obtains original parallel data flow through high speed serialization transmitting-receiving;
Step S2:ARINC818 frame parsing module processes original parallel data flow, from detection ARINC818 protocol frame SOF primitive, completes the parsing of frame head and vessel head, the recovery of load data, CRC check operation successively; State controls with memory module according to the real-time result of the instruction gathered in control register in conjunction with ARINC818 frame parsing module, the corresponding Link Status register of set also provides control command to ensure the effective analysis to ARINC818 bus failure situation, typical fault process comprises: 1. when 8B/10B decoding error being detected, 8B/10B decoding error position in set Link Status register the high speed serialization that resets transmitting-receiving and 8B/10B coding/decoding module, control original parallel data memory module simultaneously and stop stored record; 2. when link lock-out being detected, controlling original parallel data memory module and stopping record immediately, lose sync bit in set Link Status register and the ARINC818 frame parsing module that resets is waited for and again obtained link synchronization until next SOFi arrives; 3., when CRC check mistake being detected, crc error position in set Link Status register, controls the stored record that original parallel data memory module keeps original parallel data, vessel head and frame head data, not stored record load data; 4. when EOF mistake being detected, EOF error bit in a set Link Status register;
Step S3: excitation is injected and status control module realizes buffer memory Link Status register and gathers control register internal memory, the storage of original parallel data memory module Synchronization Control original parallel data, vessel head and frame head, load data;
Step S4: excitation injection is transferred to host computer respectively with status control module collection analysis function related register, each data block of original parallel data storage by PCIe bus control module, the state information gathered in host computer and analyze and initial data simultaneous display, and complete deposit in the form of a file;
(2) realize simulating the process meeting the FC driving source function of ARINC818 standard as follows:
Step T1: functional realiey process and ARINC818 bus collection analysis process contrary, the ARINC818 protocol parameter of host computer setting is transferred to excitation by PCIe bus control module and injects and status control module, the system configuration parameter needed for the function of analog stimulus source is extracted by protocol parameter injection module, the simulation load data that host computer is selected then directly are transferred in excited data memory module by PCIe bus control module, for ARINC818 framing module;
Step T2: synchronous control unit is according to the set point of ARINC818 protocol parameter, generate synchronous sequence control signal, ADVB frame head, vessel head and auxiliary data or the load data read from data buffer storage FIFO, the CRC check value that calculates in real time are combined between SOF, EOF and form complete ARINC818 data frame data stream by ARINC818 framing state machine successively;
Step T3:ARINC818 data frame data flows through high speed serialization transmitting-receiving and obtains high-speed differential serial signal with 8B/10B coding/decoding module, then is mapped in optical-fibre channel by photoelectric conversion module, and final realization meets the simulation of the FC driving source of ARINC818 standard.
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105634897A (en) * | 2016-03-30 | 2016-06-01 | 哈尔滨工业大学 | CAN bus protocol decoding IP (intellectual property) core applied to serial bus analysis instrument |
| CN106991027A (en) * | 2017-04-05 | 2017-07-28 | 中国科学院上海高等研究院 | Detector based on SERDES protocol verifications, functional verification system and method |
| CN107197232A (en) * | 2017-06-20 | 2017-09-22 | 中航华东光电（上海）有限公司 | ARINC818 aviation audio frequency and video bus data analyzers based on USB3.0 interfaces |
| CN107332747A (en) * | 2017-06-20 | 2017-11-07 | 中航华东光电（上海）有限公司 | Arinc818 aviation audio frequency and video bus data analyzers based on the interfaces of PCIExpress 2.0 |
| CN109040836A (en) * | 2018-07-05 | 2018-12-18 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of method and device for analyzing of ARINC818 protocol video stream |
| CN109302430A (en) * | 2018-12-09 | 2019-02-01 | 中国航空工业集团公司洛阳电光设备研究所 | A low-latency ARINC818 bus transceiver method |
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| CN110881027A (en) * | 2019-10-22 | 2020-03-13 | 中国航空工业集团公司洛阳电光设备研究所 | Video transmission system and conversion method of Camera Link-ARINC818 protocol |
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| CN115396254A (en) * | 2022-07-13 | 2022-11-25 | 陕西千山航空电子有限责任公司 | Multi-bus data management recording device |
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