CN105304691B - The method for being used to prepare the boundary layer of high-K dielectric layer - Google Patents
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Abstract
本发明提供了一种用于制备高K介质层的界面层的方法，包括：第一步骤：提供半导体硅衬底；第二步骤：对半导体硅衬底使用酸槽进行高K介质层沉积之前的前清洗；第三步骤：将原位水汽生成和闪光灯退火组合或快速热氧化和闪光灯退火组合用于在半导体硅衬底上生长界面层；第四步骤：在界面层上沉积高K介质层；第五步骤：在沉积高K介质层之后对半导体硅衬底执行高K后退火。
The invention provides a method for preparing an interface layer of a high-K dielectric layer, comprising: a first step: providing a semiconductor silicon substrate; a second step: using an acid bath on the semiconductor silicon substrate before depositing a high-K dielectric layer The pre-cleaning; the third step: the combination of in-situ water vapor generation and flash lamp annealing or the combination of rapid thermal oxidation and flash lamp annealing is used to grow the interfacial layer on the semiconductor silicon substrate; the fourth step: depositing a high-K dielectric layer on the interfacial layer ; Fifth step: performing high-K post-annealing on the semiconductor silicon substrate after depositing the high-K dielectric layer.
Description
技术领域technical field
本发明涉及半导体制造领域，更具体地说，本发明涉及一种用于制备高K(高介电常数)介质层的界面层的方法。The invention relates to the field of semiconductor manufacturing, more specifically, the invention relates to a method for preparing an interface layer of a high-K (high dielectric constant) dielectric layer.
背景技术Background technique
随着超大规模集成电路(VLSI)和特大规模集成电路(ULSI)的飞速发展，MOS器件的尺寸不断地减小。为增加器件的反应速度、提高驱动电流与存储电容的容量，器件中栅氧化层的厚度不断地降低。然而，随之而来的两个问题成为了阻碍集成电路进一步发展的重要因素：漏电和击穿。当栅氧化层的厚度低于由于量子隧道效应，载流子能流过这个超薄栅介质，并且载流子隧穿几率随着氧化层的厚度的减少按指数规律上升。当集成电路中MOSFET工作时，电荷流过器件导致在栅介质层和SiO2/Si界面产生缺陷，当临界缺陷密度达到时，栅介质层发生击穿，导致器件失效。当技术节点到45纳米以下，传统的SiON栅介质已经不能满足器件的漏电和击穿要求，不仅由于漏电过大导致器件无法正常工作，而且经时击穿(TDDB)不能满足可靠性要求。With the rapid development of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI), the size of MOS devices has been continuously reduced. In order to increase the response speed of the device, increase the driving current and the capacity of the storage capacitor, the thickness of the gate oxide layer in the device is continuously reduced. However, two subsequent problems have become important factors hindering the further development of integrated circuits: leakage and breakdown. When the gate oxide thickness is less than Due to the quantum tunneling effect, carriers can flow through this ultra-thin gate dielectric, and the probability of carrier tunneling increases exponentially with the reduction of the thickness of the oxide layer. When the MOSFET in the integrated circuit is working, the charge flows through the device and causes defects to be generated on the gate dielectric layer and the SiO 2 /Si interface. When the critical defect density reaches the critical defect density, the gate dielectric layer breaks down and causes the device to fail. When the technology node is below 45nm, the traditional SiON gate dielectric can no longer meet the leakage and breakdown requirements of the device. Not only does the device fail to work normally due to excessive leakage, but also the time-dependent breakdown (TDDB) cannot meet the reliability requirements.
由驱动电流和栅电容的公式可知，栅电容越大，驱动电流越大；而栅极介质层介电常数越大，栅电容越大。From the formula of drive current and gate capacitance, it can be seen that the greater the gate capacitance, the greater the drive current; and the greater the dielectric constant of the gate dielectric layer, the greater the gate capacitance.
ID～μ/Lg*Cox(VDD-VTH)2 I D ～μ/L g *C ox (V DD -V TH ) 2
Cox＝kA/dC ox = kA/d
其中ID为驱动电流，μ为载流子迁移率，Lg为栅极长度，Cox为栅电容，VDD为工作电压，VTH为阈值电压，k为栅极介质层介电常数，A为器件面积，d为栅极介质层厚度。Among them, ID is the driving current, μ is the carrier mobility, L g is the gate length, C ox is the gate capacitance, V DD is the operating voltage, V TH is the threshold voltage, k is the dielectric constant of the gate dielectric layer, A is the device area, and d is the thickness of the gate dielectric layer.
因此，需要一种替代的栅极介质层材料，不但要有够厚的实际厚度来降低漏电流密度和加强经时击穿(TDDB)可靠性要求，而且能提供高的栅极电容来增加驱动电流。为了达到上述目的，替代的栅极介质层材料所具有的介电常数需要高于传统的氮氧化硅(SiON)的介电常数。因此在45纳米技术节点以下，迫切需要采用新型的高K栅介质如Hf基、Zr或Al的氧化物来取代SiON。Therefore, there is a need for an alternative gate dielectric layer material that not only has a sufficiently thick practical thickness to reduce leakage current density and strengthen reliability requirements for time-dependent breakdown (TDDB), but also provides high gate capacitance to increase drive current. In order to achieve the above purpose, the dielectric constant of the alternative gate dielectric layer material needs to be higher than that of conventional silicon oxynitride (SiON). Therefore, below the 45nm technology node, it is urgent to use new high-K gate dielectrics such as Hf-based, Zr or Al oxides to replace SiON.
高K栅介质常用的制备流程为：1.高K前清洗；2.超薄SiO2或SiON层生长；3.高K介质层沉积；4.高K后退火(Post Anneal)。The common preparation process of high K gate dielectric is: 1. Cleaning before high K; 2. Growth of ultra-thin SiO2 or SiON layer; 3. Deposition of high K dielectric layer; 4. Post Anneal after high K.
由于高K栅介质材料主要以金属氧化物为主，在制备过程中必定有氧的存在，而氧与硅的反应会在高K介质层与硅衬底之间形成二氧化硅或硅化物的界面氧化层，由于该氧化层的存在使得氧化物等效厚度(EOT)的缩小变得困难。为了抑制该氧化层的生成，需要在高K介质层沉积之前生长一层高品质的超薄SiO2或SiON层。Since the high-K gate dielectric material is mainly metal oxide, there must be oxygen in the preparation process, and the reaction between oxygen and silicon will form silicon dioxide or silicide between the high-K dielectric layer and the silicon substrate. The interface oxide layer, due to the existence of the oxide layer, makes it difficult to reduce the equivalent oxide thickness (EOT). In order to suppress the formation of the oxide layer, it is necessary to grow a high-quality ultra-thin SiO 2 or SiON layer before the deposition of the high-K dielectric layer.
发明内容Contents of the invention
本发明所要解决的技术问题是针对现有技术中存在上述缺陷，提供一种用于制备高K介质层的界面层的方法，所制备的高K介质层的界面层更加致密，其能够抑制高K介质层与硅衬底之间形成的界面氧化层，从而使得氧化物等效厚度(EOT)的缩小变得容易。The technical problem to be solved by the present invention is to provide a method for preparing the interface layer of the high-K dielectric layer in view of the above-mentioned defects in the prior art. The interface layer of the prepared high-K dielectric layer is denser, which can suppress the The interface oxide layer formed between the K dielectric layer and the silicon substrate makes it easy to reduce the equivalent thickness of oxide (EOT).
为了实现上述技术目的，根据本发明，提供了一种用于制备高K介质层的界面层的方法，包括：In order to achieve the above technical purpose, according to the present invention, a method for preparing an interface layer of a high-K dielectric layer is provided, comprising:
第一步骤：提供半导体硅衬底；The first step: providing a semiconductor silicon substrate;
第二步骤：对半导体硅衬底使用酸槽进行高K介质层沉积之前的前清洗；The second step: use an acid bath to perform pre-cleaning before deposition of a high-K dielectric layer on the semiconductor silicon substrate;
第三步骤：将原位水汽生成和闪光灯退火组合或快速热氧化和闪光灯退火组合用于在半导体硅衬底上生长界面层；Third step: a combination of in situ water vapor generation and flash lamp annealing or a combination of rapid thermal oxidation and flash lamp annealing for growing an interfacial layer on a semiconductor silicon substrate;
第四步骤：在界面层上沉积高K介质层；The fourth step: depositing a high-K dielectric layer on the interface layer;
第五步骤：在沉积高K介质层之后对半导体硅衬底执行高K后退火。The fifth step: performing high-K post-annealing on the semiconductor silicon substrate after depositing the high-K dielectric layer.
优选地，第三步骤生长的界面层的厚度为例如 Preferably, the thickness of the interface layer grown in the third step is E.g
优选地，在第三步骤中，在原位水汽生成中，工艺温度为400～1000℃，工艺压力为0.5Torr～25Torr，工艺气体为H2/O2/N2的组合、H2/N2O/N2的组合、H2/O2/Ar的组合、H2/N2O/Ar的组合、H2/O2/He的组合或H2/N2O/He的组合，工艺气体的流量为1slm～50slm，其中H2/O2的比例小于33％，H2/N2O的比例小于16.5％。Preferably, in the third step, in the in-situ water vapor generation, the process temperature is 400-1000°C, the process pressure is 0.5 Torr-25 Torr, and the process gas is a combination of H 2 /O 2 /N 2 , H 2 /N 2 O/N 2 combination, H 2 /O 2 /Ar combination, H 2 /N 2 O/Ar combination, H 2 /O 2 /He combination or H 2 /N 2 O/He combination, The flow rate of the process gas is 1slm-50slm, wherein the ratio of H 2 /O 2 is less than 33%, and the ratio of H 2 /N 2 O is less than 16.5%.
优选地，在第三步骤中，在原位水汽生成中，还可以组合使用DPN氮掺杂和PNA退火工艺，其中原位水汽的工艺温度为400～1000℃，工艺气体为H2/O2/N2、H2/N2O/N2、H2/O2/Ar、H2/N2O/Ar、H2/O2/He或H2/N2O/He，流量为1slm～50slm，其中H2/O2的比例小于33％，H2/N2O的比例小于16.5％；氮掺杂DPN RF Power为500W～2000W，Duty Cycle为2％～20％，N2流量为25sccm～200sccm；PNA退火工艺温度为800～1100℃，工艺气体为O2或O2/N2，流量为1slm～50slm，其中O2的含量为0.2％～100％。Preferably, in the third step, in the in-situ water vapor generation, DPN nitrogen doping and PNA annealing process can also be used in combination, wherein the process temperature of the in-situ water vapor is 400-1000°C, and the process gas is H2/O2/N2 . The ratio of nitrogen-doped DPN RF Power is 500W~2000W, Duty Cycle is 2%~20%, N2 flow rate is 25sccm~200sccm; PNA annealing process temperature is 800~1100℃, process gas is O2 or O2/ N2, the flow rate is 1slm~50slm, and the content of O2 is 0.2%~100%.
优选地，在第三步骤中，在快速热氧化中，工艺温度为400～1000℃，工艺压力为0.05Torr至500Torr，工艺气体为O2/N2、N2O/N2、O2/Ar、N2O/Ar、O2/He或N2O/He，流量为1slm～50slm，其中O2的含量为0.5％～100％。Preferably, in the third step, in the rapid thermal oxidation, the process temperature is 400-1000° C., the process pressure is 0.05 Torr to 500 Torr, and the process gas is O2/N2, N2O/N2, O2/Ar, N2O/Ar, O2/He or N2O/He, the flow rate is 1slm-50slm, and the content of O2 is 0.5%-100%.
优选地，在第三步骤中，在闪光灯退火中，工艺温度为500～1200℃，工艺气体为O2、O2/N2的组合、O2/Ar的组合或O2/He的组合，工艺气体的流量为1slm～50slm，其中O2/N2、O2/Ar或O2/He中的O2的体积含量为0.2％～100％。Preferably, in the third step, in flash lamp annealing, the process temperature is 500-1200°C, and the process gas is O 2 , a combination of O 2 /N 2 , a combination of O 2 /Ar or a combination of O 2 /He, The flow rate of the process gas is 1 slm-50 slm, wherein the volume content of O 2 in O 2 /N 2 , O 2 /Ar or O 2 /He is 0.2%-100%.
优选地，在第三步骤中，先使用原位水汽生成ISSG生长SiO2薄膜，工艺温度为500℃，工艺压力为15Torr，工艺气体为H2/N2O/Ar，流量为0.1slm/9.9slm/30slm；然后执行闪光灯退火，工艺温度为1150℃，工艺气体为O2/Ar，流量为1slm/19slm。Preferably, in the third step, in-situ water vapor generation ISSG is first used to grow SiO 2 films, the process temperature is 500°C, the process pressure is 15 Torr, the process gas is H 2 /N 2 O/Ar, and the flow rate is 0.1slm/9.9 slm/30slm; then perform flash lamp annealing, the process temperature is 1150°C, the process gas is O 2 /Ar, and the flow rate is 1slm/19slm.
优选地，所述高K介质层为HfO2层、ZrO2层或Al2O3层。Preferably, the high-K dielectric layer is an HfO 2 layer, a ZrO 2 layer or an Al 2 O 3 layer.
优选地，所述高K介质层的厚度为例如 Preferably, the thickness of the high-K dielectric layer is E.g
优选地，第五步骤中的高K后退火的工艺条件为：工艺温度为500～900℃，例如800℃，工艺气体为N2，工艺气体的流量为10～30Slm，例如20Slm，工艺时间为0.2～5分钟，例如1分钟。Preferably, the process conditions of the high-K post-annealing in the fifth step are as follows: the process temperature is 500-900°C, such as 800°C, the process gas is N 2 , the flow rate of the process gas is 10-30Slm, such as 20Slm, and the process time is 0.2 to 5 minutes, such as 1 minute.
优选地，所述半导体硅衬底包括N阱、P阱和STI隔离结构。Preferably, the semiconductor silicon substrate includes an N well, a P well and an STI isolation structure.
优选地，所述方法用于45纳米以下高K介质层的界面层的制备。Preferably, the method is used for the preparation of the interface layer of the high-K dielectric layer below 45 nanometers.
附图说明Description of drawings
结合附图，并通过参考下面的详细描述，将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征，其中：A more complete understanding of the invention, and its accompanying advantages and features, will be more readily understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, in which:
图1示意性地示出了根据本发明优选实施例的用于制备高K介质层的界面层的方法的流程图。Fig. 1 schematically shows a flowchart of a method for preparing an interface layer of a high-K dielectric layer according to a preferred embodiment of the present invention.
需要说明的是，附图用于说明本发明，而非限制本发明。注意，表示结构的附图可能并非按比例绘制。并且，附图中，相同或者类似的元件标有相同或者类似的标号。It should be noted that the accompanying drawings are used to illustrate the present invention, but not to limit the present invention. Note that drawings showing structures may not be drawn to scale. And, in the drawings, the same or similar elements are marked with the same or similar symbols.
具体实施方式Detailed ways
为了使本发明的内容更加清楚和易懂，下面结合具体实施例和附图对本发明的内容进行详细描述。In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.
本发明将原位水汽生成ISSG和闪光灯退火(Flash Anneal)组合或快速热氧化和闪光灯退火组合用于界面层生长，制备超薄的SiO2或SiON层。该方法制备的界面层更加致密，可以有效地抑制后续高K介质层沉积和高K后退火形成的界面氧化层。In the present invention, the combination of in-situ water vapor generation ISSG and flash lamp annealing (Flash Anneal) or rapid thermal oxidation and flash lamp annealing is used for interfacial layer growth to prepare ultra-thin SiO 2 or SiON layers. The interface layer prepared by this method is denser, which can effectively suppress the interface oxide layer formed by subsequent high-K dielectric layer deposition and high-K post-annealing.
图1示意性地示出了根据本发明优选实施例的用于制备高K介质层的界面层的方法的流程图。Fig. 1 schematically shows a flowchart of a method for preparing an interface layer of a high-K dielectric layer according to a preferred embodiment of the present invention.
如图1所示，根据本发明优选实施例的用于制备高K介质层的界面层的方法包括：As shown in Figure 1, the method for preparing the interface layer of the high-K dielectric layer according to the preferred embodiment of the present invention includes:
第一步骤S1：提供半导体硅衬底；优选地，所述半导体硅衬底包括N阱、P阱和STI(浅沟槽)隔离结构。The first step S1: providing a semiconductor silicon substrate; preferably, the semiconductor silicon substrate includes an N well, a P well and an STI (Shallow Trench) isolation structure.
第二步骤S2：对半导体硅衬底使用酸槽进行高K介质层沉积之前的前清洗；The second step S2: using an acid bath to perform pre-cleaning before depositing a high-K dielectric layer on the semiconductor silicon substrate;
第三步骤S3：将原位水汽生成ISSG和闪光灯退火组合或快速热氧化和闪光灯退火组合用于在半导体硅衬底上生长界面层；The third step S3: the combination of in-situ water vapor generation ISSG and flash lamp annealing or the combination of rapid thermal oxidation and flash lamp annealing is used to grow an interfacial layer on the semiconductor silicon substrate;
优选地，第三步骤生长的界面层的厚度为例如 Preferably, the thickness of the interface layer grown in the third step is E.g
优选地，第三步骤S3的工艺条件为：在原位水汽生成中，工艺温度为400～1000℃，工艺压力为0.5Torr～25Torr，工艺气体为H2/O2/N2的组合、H2/N2O/N2的组合、H2/O2/Ar的组合、H2/N2O/Ar的组合、H2/O2/He的组合或H2/N2O/He的组合，工艺气体的流量为1slm～50slm，其中H2/O2的比例小于33％，H2/N2O的比例小于16.5％。而且，在原位水汽生成中，还可以组合使用DPN氮掺杂和PNA退火工艺，其中原位水汽的工艺温度为400～1000℃，工艺气体为H2/O2/N2、H2/N2O/N2、H2/O2/Ar、H2/N2O/Ar、H2/O2/He或H2/N2O/He，流量为1slm～50slm，其中H2/O2的比例小于33％，H2/N2O的比例小于16.5％；氮掺杂DPN RF Power为500W～2000W，Duty Cycle为2％～20％，N2流量为25sccm～200sccm；PNA退火工艺温度为800～1100℃，工艺气体为O2或O2/N2，流量为1slm～50slm，其中O2的含量为0.2％～100％。Preferably, the process conditions of the third step S3 are: in the in-situ water vapor generation, the process temperature is 400-1000°C, the process pressure is 0.5 Torr-25 Torr, and the process gas is a combination of H 2 /O 2 /N 2 , H Combination of 2 /N 2 O/N 2 , combination of H 2 /O 2 /Ar, combination of H 2 /N 2 O/Ar, combination of H 2 /O 2 /He or H 2 /N 2 O/He combination, the flow rate of the process gas is 1slm-50slm, wherein the ratio of H 2 /O 2 is less than 33%, and the ratio of H 2 /N 2 O is less than 16.5%. Moreover, in the in-situ water vapor generation, DPN nitrogen doping and PNA annealing process can also be used in combination, wherein the process temperature of in-situ water vapor is 400-1000 °C, and the process gas is H2/O2/N2, H2/N2O/N2, H2/O2/Ar, H2/N2O/Ar, H2/O2/He or H2/N2O/He, the flow rate is 1slm～50slm, in which the proportion of H2/O2 is less than 33%, and the proportion of H2/N2O is less than 16.5%; Nitrogen Doped DPN RF Power is 500W~2000W, Duty Cycle is 2%~20%, N2 flow rate is 25sccm~200sccm; PNA annealing process temperature is 800~1100℃, process gas is O2 or O2/N2, flow rate is 1slm~50slm , wherein the content of O2 is 0.2% to 100%.
在闪光灯退火中，工艺温度为500～1200℃，工艺气体为O2、O2/N2的组合、O2/Ar的组合或O2/He的组合，工艺气体的流量为1slm～50slm，其中O2/N2、O2/Ar或O2/He中的O2的体积含量为0.2％～100％。In flash lamp annealing, the process temperature is 500-1200°C, the process gas is O 2 , the combination of O 2 /N 2 , the combination of O 2 /Ar or the combination of O 2 /He, and the flow rate of the process gas is 1slm-50slm. Wherein the volume content of O 2 in O 2 /N 2 , O 2 /Ar or O 2 /He is 0.2%˜100%.
举例来说，在第三步骤S3中，先使用原位水汽生成ISSG生长SiO2薄膜，工艺温度为500℃，工艺压力为15Torr，工艺气体为H2/N2O/Ar，流量为0.1slm/9.9slm/30slm；然后执行闪光灯退火，工艺温度为1150℃，工艺气体为O2/Ar，流量为1slm/19slm。For example, in the third step S3, first use in-situ water vapor generation ISSG to grow SiO 2 film, the process temperature is 500°C, the process pressure is 15Torr, the process gas is H 2 /N 2 O/Ar, and the flow rate is 0.1slm /9.9slm/30slm; then perform flash lamp annealing, the process temperature is 1150°C, the process gas is O 2 /Ar, and the flow rate is 1slm/19slm.
第四步骤S4：在界面层上沉积高K介质层；优选地，所述高K介质层的厚度为例如优选地，所述高K介质层为HfO2层、ZrO2层或Al2O3层。The fourth step S4: depositing a high-K dielectric layer on the interface layer; preferably, the thickness of the high-K dielectric layer is E.g Preferably, the high-K dielectric layer is an HfO 2 layer, a ZrO 2 layer or an Al 2 O 3 layer.
第五步骤S5：在沉积高K介质层之后对半导体硅衬底执行高K后退火。Fifth step S5: perform high-K post-annealing on the semiconductor silicon substrate after depositing the high-K dielectric layer.
优选地，第五步骤中的高K后退火的工艺条件为：工艺温度为500～900℃，例如800℃工艺气体为N2，工艺气体的流量为10～30Slm，例如20Slm，工艺时间为0.2～5分钟，例如1分钟。Preferably, the process conditions of the high-K post-annealing in the fifth step are as follows: process temperature is 500-900°C, for example, the process gas is N 2 at 800°C, the flow rate of process gas is 10-30Slm, such as 20Slm, and the process time is 0.2 ~5 minutes, eg 1 minute.
本发明的用于制备高K介质层的界面层的方法尤其适合于45纳米以下高K介质层的界面层的制备方法，其能够抑制后续高K介质层沉积和高K后退火所形成的界面氧化层。The method for preparing the interface layer of the high-K dielectric layer of the present invention is especially suitable for the preparation method of the interface layer of the high-K dielectric layer below 45 nanometers, which can suppress the interface formed by subsequent high-K dielectric layer deposition and high-K post-annealing oxide layer.
此外，需要说明的是，除非特别说明或者指出，否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。In addition, it should be noted that, unless otherwise specified or pointed out, the terms “first”, “second”, “third” and other descriptions in the specification are only used to distinguish each component, element, step, etc. in the specification, and It is not used to represent the logical relationship or sequential relationship between various components, elements, and steps.
可以理解的是，虽然本发明已以较佳实施例披露如上，然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.
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