CN105161425A - Semiconductor stacked packaging method - Google Patents

Abstract

The present invention provides a semiconductor stack packaging method, including A: making an upper package, B: making a middle package packaged with a chip, C: stacking and packaging the upper, middle and lower packages, step B includes: S101: Provide the metal plate; S102: Half-etch the front side of the metal plate to form the first opening; S103: Install the chip to be loaded in the first opening and make wires; S104: Fix and package the chip on the metal plate with plastic underfill above; S105: half-etching the back of the metal plate to form a second opening; S106: filling the area of the second opening with plastic underfill; S107: forming solder balls. In the packaging method provided by the invention, the metal plate is improved to form a QFN frame, and the L-shaped metal sheets on both sides are used as the electrodes of the middle package, so as to realize the up and down conduction of the stacked chips in one package; save the package space, which is beneficial When the multi-layer plastic package is stacked, the miniaturization of the chip package is realized, and the integration degree of the chip package is improved.

Description

Semiconductor Stack Packaging Method

technical field

The invention relates to a semiconductor packaging method, in particular to a semiconductor stack packaging method.

Background technique

With the continuous development of semiconductor manufacturing technology and three-dimensional packaging technology, electronic devices and electronic products have higher and higher requirements for multi-function and miniaturization, and at the same time, the package size of chips is required to be continuously reduced. In order to realize the miniaturization of chip packaging and improve the integration of chip packaging, stacked die package (stacked die package) technology has gradually become the mainstream of technological development.

Stacked chip packaging technology, also known as three-dimensional packaging technology, is specifically a packaging technology that stacks at least two chips in the same package. Stacked chip packaging technology can meet the technical requirements of semiconductor devices such as large capacity, multi-function, small size, and low cost. Therefore, stacked chip technology has developed vigorously in recent years. Taking the memory using the stacked packaging technology as an example, compared with the memory without using the stacked packaging technology, the memory using the stacked packaging technology can have more than twice the storage capacity. In addition, the use of stacked packaging technology can more effectively use the area of the chip, and it is mostly used in U disks and SD cards with large storage spaces.

The stacked chip packaging technology can be realized through various technical means, such as a wire bonding process, a through silicon via (TSV for short) technology, or a through molding via (TMV for short) technology.

For example, through-silicon via (TSV) technology is to form a through hole on the chip, form a metal layer on the side wall of the through hole, and then fill it with conductive material to form a through hole effect to realize the upper and lower connection. The cost of this process is high, and the yield rate is low. Direct openings on the silicon wafer can easily cause damage to the chip or reduce the strength of the entire wafer, resulting in fragments. It is difficult to realize.

As another example, through-molding via (TMV) technology refers to the opening of the plastic sealing layer, that is, the use of lasers and other methods to open the plastic sealing layer after plastic sealing, and to fill the conductive material. Difficult to control.

The rest are some prefabricated conductive materials such as concave structures, which are used for connection through grinding and wire bonding.

In the process of stacking chips in the above process, it is difficult to form electrodes by filling the dielectric in the hole, especially in the process of connecting multiple plastic packages to form the entire package, it is not easy to realize the upper and lower packages through the plastic package in the middle of the traditional process. conduction, so that it is difficult and costly to realize the conduction of the chip up and down in a package.

Contents of the invention

A brief overview of the invention is given below in order to provide a basic understanding of some aspects of the invention. It should be understood that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical parts of the invention nor to delineate the scope of the invention. Its purpose is merely to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

The object of the present invention is to provide a semiconductor stack packaging method to solve the difficulty in forming electrodes in the existing packaging technology (such as TSV, TMV, etc.), especially in the process of connecting multiple plastic packages to form a package. It is not easy to realize the conduction of the upper and lower packages of the plastic package, so it is not easy to realize the problem of the conduction of the chip in the upper and lower packages.

The invention provides a semiconductor stack packaging method, comprising:

A: Make the upper package,

B: Make the middle package with the chip packaged,

C: laminating and encapsulating the upper package, the middle package and the lower package,

Wherein, step B includes:

S101: providing a metal plate for preparing the above-mentioned intermediate package;

S102: half-etching the front side of the metal plate to form a first opening, the depth of the first opening is greater than the thickness of the chip to be loaded;

S103: Install the above-mentioned chip to be loaded in the first opening and perform wire bonding in the first opening;

S104: Fixing and packaging the chip on the metal plate with plastic underfill to form a plastic underfill layer;

S105: half-etching the back of the metal plate to the plastic packing layer to form a second opening;

S106: filling the area of the second opening with a plastic underfill to form a plastic package;

S107: Form solder balls on the front edge or the back edge of the plastic package.

The invention provides a semiconductor stack packaging method. The metal plate is improved to form a four-sided flat no-lead (QFN) frame, and the metal protrusion on the edge is used as the electrode of the middle package to realize the connection between the middle package and the upper package. The lower package is connected, so that the stacked chips can be connected up and down in one package; the middle package formed in the form of a QFN frame saves packaging space, which is conducive to realizing the miniaturization of the package when stacking multiple layers, and improving the reliability of the chip package. Integration.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the flow chart that the present invention makes the middle package body that is packaged with chip;

Fig. 2-Fig. 7 is the schematic diagram of the process of making the intermediate package with chip packaged in the present invention;

Fig. 8 is a schematic diagram of the stacked package structure of the present invention.

Reference signs:

1-metal plate 2-first opening 3-chip

4-plastic packing layer 5-second opening 6-metal layer

7-metal sheet 8-lower package 9-upper package

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The invention provides a semiconductor stack packaging method, comprising:

A: Make the upper package,

B: Make the middle package with the chip packaged,

C: laminating and encapsulating the upper package, the middle package and the lower package,

Wherein, as shown in Figure 1, the step B of making the middle package body packaged with chips includes:

S101: providing a metal plate for preparing the above-mentioned intermediate package;

S102: half-etching the front side of the metal plate to form a first opening, the depth of the first opening is greater than the thickness of the chip to be loaded;

S103: Install the above-mentioned chip to be loaded in the first opening and perform wire bonding in the first opening;

S104: Fixing and packaging the chip on the metal plate with plastic underfill to form a plastic underfill layer;

S105: half-etching the back of the metal plate to the plastic packing layer to form a second opening;

S106: filling the area of the second opening with a plastic underfill to form a plastic package;

S107: Form solder balls on the front edge or the back edge of the plastic package.

The above steps provide a method for manufacturing a mid-level package packaged with a chip. As shown in FIG. 2 , step S101 is implemented to provide a metal plate 1 for preparing the above-mentioned mid-level package.

Optionally, for the convenience of subsequently forming electrodes on the metal plate 1 , the material of the metal plate 1 is a metal material with high conductivity and high melting point, such as copper. In this embodiment, the thickness of the copper plate needs to be greater than the thickness of the chip to be loaded but not too high, so as to save material and facilitate the subsequent formation of openings on the upper and lower surfaces of the metal plate and the addition of chips.

As shown in Figures 3-4, S102-S103 is then implemented: half-etching the front side of the metal plate to form a first opening 2, the depth of the first opening 2 is greater than the thickness of the chip to be loaded;

The chip 3 to be loaded is installed in the first opening 2 and wire-bonded in the first opening 2 to form a structure as shown in FIG. 3 .

Further, in step S102, forming the first opening by half-etching the front side of the metal plate specifically includes:

Paste film on the front of the metal plate for exposure and development;

Etching the exposed and developed parts to form a first opening, and forming protrusions on both sides of the front side of the metal plate 1, the raised parts on both sides as shown in Figure 3 are protrusions;

The remaining film after the above-mentioned exposure and development is removed, and the above-mentioned metal plate has a concave structure after the above-mentioned treatment.

Then proceed to step S104 , fixing and packaging the above-mentioned chip 3 on the above-mentioned metal plate with a plastic underfill to form a plastic-fill layer 4 , as shown in FIG. 5 .

Optionally, in step S104 , the height of the plastic packing layer 4 is equal to the protrusion, and the chip 3 is fixed on the metal plate with the plastic underfill and encapsulated inside the plastic package shown in FIG. 5 . The packaging of the chip adopts the molding bottom filling technology, and the chip and the metal bumps are wrapped inside the plastic package.

The above-mentioned glue used for molding underfill technology is a kind of chemical glue, and its main component can be epoxy resin, which fills the gap between the chip and the metal plate with the above-mentioned concave structure, wraps the chip, and heats the filling glue Curing can achieve the purpose of reinforcement, which ensures the electrical safety of the welding process.

Step S105 is then implemented to half-etch the backside of the metal plate to the plastic packing layer 4 to form a second opening 5 , as shown in FIG. 6 .

Optionally, in step S105, half-etching the back of the metal plate to the 4th layer of the plastic packing, forming the second opening specifically includes:

Stick a film on the back of the above metal plate for exposure and development;

Etching the exposed and developed parts to form a second opening, the second opening separates the metal plate into a plurality of mutually isolated metal plates;

The film remaining after the above-mentioned exposure and development is removed.

Optionally, the area of the first opening 2 is larger than the area of the second opening 5 , and the second opening 5 is located in the area of the metal plate corresponding to the first opening 2 .

Optionally, the plurality of mutually isolated metal plates include a metal layer 6 and L-shaped metal sheets 7 symmetrically arranged on both sides of the metal layer 6, and the metal sheet 7 includes the above-mentioned protrusions; the chip 3 is connected to the metal layer 6 superior.

Continue to implement step S106, fill the area of the second opening 5 with plastic underfill to form the structure shown in Figure 7, of course, you can also fill the second opening with insulating glue to form a plastic package to further improve the packaging strength .

Finally, step S107 is implemented to form solder balls on the front edge or the back edge of the plastic package. In this solution, the solder balls are arranged on the front or back of the L-shaped metal sheet, and the L-shaped metal sheet 7 separated from the metal layer through the first opening and the second opening is the electrode of the middle package.

After the above steps, the mid-level package with the chip packaged is completed, and then step C: it is necessary to connect the upper package and the lower package with the mid-level package, and then perform reflow soldering to form a semiconductor stack as shown in Figure 8. Layer encapsulation structure. As shown in Figure 8, the bottom surface of the substrate of the upper package body 9 in the present invention is a metal plate to serve as the conductive connection part of the upper package body; The pillars are used as the conductive connection parts of the lower package body.

Optionally, in step S107, solder balls are formed on the lower surfaces of the metal sheets on both sides of the plastic package shown in FIG. The above-mentioned middle package body is connected with the upper package body 9 with solder balls on the substrate through the upper surface of the metal sheets on both sides, and then reflow soldering is performed to finally form a semiconductor stack as shown in Figure 8. Layer encapsulation structure.

Alternatively, in step S107, solder balls are formed on the upper surfaces of the metal sheets on both sides of the plastic package shown in FIG. Reflow soldering: the above-mentioned middle package body is connected to the conductive connection part of the upper package body 9 through solder balls formed on the upper surface of the metal sheet 7, and then reflow soldering is performed to finally form a semiconductor stacked package structure as shown in FIG. 8 .

Figure 8 is a schematic diagram of the stacked package structure of the present invention. The QFN frame is formed by improving the metal plate, and the metal sheets 7 on both sides are used as the electrodes of the middle package to realize the electrical interconnection between the upper package 9 and the lower package 8. A plurality of packaged chips realize up-and-down conduction in the entire package body; and the package structure is simple, which saves package space, is conducive to realizing miniaturization of chip packages when stacking multilayer plastic packages, and improves the integration degree of chip packages.

At the same time, the stacked package proposed in this solution is the connection of the upper, middle and lower packages. Of course, according to actual needs, the number of packages in the stacked package can be determined according to the actual situation, and the upper package and the lower package can be connected. More chip packaging layers are stacked and packaged between bodies, and the structure of the stacked package is increased to form a three-layer chip package or a chip package with more layers.

In the above-mentioned embodiments of the present invention, the serial numbers and/or sequences of the embodiments are only for convenience of description, and do not represent the advantages and disadvantages of the embodiments. The description of each embodiment has its own emphases, and for the part that is not described in detail in a certain embodiment, refer to the relevant descriptions of other embodiments.

Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the Including the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: read-only memory (Read-OnlyMemory, ROM for short), random access memory (RandomAccessMemory, RAM for short), magnetic disk or optical disk, etc., which can store program codes medium.

In the embodiments of the device and method of the present invention, obviously, each component or each step can be decomposed, combined and/or recombined after decomposing. These decompositions and/or recombinations should be considered equivalents of the present invention. Meanwhile, in the above descriptions of specific embodiments of the present invention, features described and/or shown for one embodiment can be used in one or more other embodiments in the same or similar manner, and combination of features, or replace features in other embodiments.

It should be emphasized that the term "comprising/comprising" when used herein refers to the presence of a feature, element, step or component, but does not exclude the presence or addition of one or more other features, elements, steps or components.

Finally, it should be noted that although the present invention and its advantages have been described in detail above, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present invention defined by the appended claims. transform. Moreover, the scope of the present invention is not limited to the specific embodiments of the procedures, devices, means, methods and steps described in the specification. Those of ordinary skill in the art will readily appreciate from the disclosure of the present invention that existing and future devices that perform substantially the same function or obtain substantially the same results as the corresponding embodiments described herein can be used in accordance with the present invention. The developed process, device, means, method or steps. Accordingly, the appended claims are intended to include within their scope such processes, means, means, methods or steps.

Claims (10)

1. A semiconductor stack packaging method, comprising: A: Make the upper package, B: Make the middle package with the chip packaged, C: laminating and encapsulating the upper package, the middle package and the lower package, It is characterized in that said step B includes: S101: providing a metal plate for preparing the above-mentioned intermediate package; S102: half-etching the front side of the metal plate to form a first opening, the depth of the first opening is greater than the thickness of the chip to be loaded; S103: Install the above-mentioned chip to be loaded in the first opening and perform wire bonding in the first opening; S104: Fixing and packaging the chip on the metal plate with plastic underfill to form a plastic underfill layer; S105: half-etching the back of the metal plate to the plastic packing layer to form a second opening; S106: filling the area of the second opening with a plastic underfill to form a plastic package; S107: Form solder balls on the front edge or the back edge of the plastic package. 2. The method according to claim 1, wherein the step C comprises: the above-mentioned middle package body is connected to the conductive connection parts of the upper package body and the lower package body through solder balls, and then reflow soldering is performed A semiconductor stack structure is formed. 3. The method according to claim 1, wherein the metal plate in step S101 is a copper plate. 4. The method according to claim 1, wherein step S102: half-etching the front side of the metal plate to form the first opening is specifically: Sticking a film on the front side of the metal plate for exposure and development; Etching the exposed and developed part to form a first opening, and forming protrusions on both sides of the front side of the metal plate; The film remaining after the above-mentioned exposure and development is removed. 5. The method according to claim 4, wherein the height of the plastic packing layer in the plastic package in step S104 is flush with the protrusion, the chip is fixed on the metal plate with the plastic bottom packing and encapsulated inside the plastic package. 6. The method according to claim 4, characterized in that, step S105: half-etching the back of the metal plate to the plastic packing layer to form a second opening, specifically: Sticking a film on the back side of the metal plate for exposure and development; Etching the exposed and developed parts to form a second opening, the second opening separates the metal plate into a plurality of mutually isolated metal plates; The film remaining after the above-mentioned exposure and development is removed. 7. The method according to claim 6, wherein the area of the first opening is larger than the area of the second opening, and the second opening is located in the area of the metal plate corresponding to the first opening . 8. The method according to claim 7, wherein the plurality of mutually isolated metal plates comprise a metal layer and L-shaped metal sheets symmetrically arranged on both sides of the metal layer, and the chip is connected to the on the metal layer; The metal sheet includes the above-mentioned protrusions. 9. The method according to claim 8, wherein in step S107, the solder balls are arranged on the front or back of the L-shaped metal sheet. 10. The method according to any one of claims 1-9, characterized in that one or more intermediate packages are disposed between the upper package and the lower package.