CN105070759A - Nldmos device and manufacturing method thereof - Google Patents

Abstract

The invention discloses an NLDMOS device, comprising: a drift region, a P well, a PTOP layer formed in the drift region, a P-type and an N-type doped implantation region formed on the front surface of the drift region, each P-type and N-type doped The impurity implantation regions are in a strip structure parallel to the channel length direction, and the P-type and N-type dopant implantation regions are arranged alternately along the channel width direction, and each N-type dopant implantation region is used to increase the surface density of the drift region. The doping concentration reduces the on-resistance, and each P-type doping implantation region achieves mutual depletion with the N-type doping implantation region, so that the breakdown voltage of the device will not be reduced due to the increase of the surface doping concentration of the drift region. The invention also discloses a manufacturing method of the NLDMOS device. The invention can reduce the on-resistance of the device under the condition of maintaining high breakdown voltage, thereby improving the performance of the device.

Description

NLDMOS device and its manufacturing method

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an N-type laterally diffused metal oxide semiconductor (NLDMOS) device; the invention also relates to a manufacturing method of the NLDMOS device.

Background technique

The 700V laterally diffused metal oxide semiconductor (LDMOS) device not only has the characteristics of high voltage and high current of discrete devices, but also absorbs the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip realizes the functions that can only be completed by multiple chips, which greatly reduces the area. , reduces costs, improves energy efficiency, and conforms to the development direction of miniaturization, intelligence, and low energy consumption of modern power electronic devices.

Breakdown voltage and on-resistance are key parameters for measuring 700V LDMOS devices. In the prior art, by forming a PTOP layer on the surface of the drift region, the depletion of the drift region can be increased, and the effect of reducing the surface electric field (Resurf) can be realized. As shown in FIG. 1 , it is a schematic structural diagram of an existing NLDMOS device; on a silicon substrate 1 The formation consists of N-type deep well 2, P well 4 and the drift region are separated by a certain distance, P well 4 is also surrounded by an N-type deep well 2, field oxygen 3 is formed on the surface of N-type deep well 2, and the gate structure is composed of gate oxide layer 6 and polysilicon gate 7, the source region 8b is formed in the P well 4 and is self-aligned with the polysilicon gate 7, the P well lead-out region 9 is formed on the surface of the P well 4 and consists of a P+ region, and the drain region 8a is formed in the drift region The surface is self-aligned with one side of the field oxide 3; a polysilicon field plate 7a is formed on the side of the field oxide 3 close to the drain region 8a, and the polysilicon field plate 7a and the polysilicon gate 7 are formed by photolithography of the same layer of polysilicon. The interlayer film 10 covers the device area at the bottom, and the source, drain and gate of the device are drawn out through the contact hole and the front metal layer 11 . A PTOP layer 5 is formed on the surface of the drift region, and a PTOP layer 5 is also formed at the bottom of the P well 4 on the side of the source region 8b. The PTOP layer 5 can increase the depletion of the drift region, reduce the surface electric field, and finally improve the breakdown of the device. Voltage.

Since the breakdown voltage and on-resistance are the key parameters to measure the 700VLDMOS device, although the existing device described in Figure 1 can increase the breakdown voltage of the device, if the on-resistance of the device can be further reduced, the performance of the device can be improved performance.

Contents of the invention

The technical problem to be solved by the present invention is to provide an NLDMOS device, which can reduce the on-resistance of the device while maintaining a high breakdown voltage, thereby improving the performance of the device. Therefore, the invention also provides a manufacturing method of the NLDMOS device.

In order to solve the above technical problems, the NLDMOS device provided by the present invention includes:

The N-type doped drift region is formed in the P-type semiconductor substrate.

A P well is formed in the P-type semiconductor substrate, and the P well is in contact with or separated from a side of the drift region by a certain distance.

A polysilicon gate formed above the semiconductor substrate, the polysilicon gate is isolated from the surface of the semiconductor substrate by a gate dielectric layer, and the polysilicon gate extends from the P well to above the drift region in the lateral direction, and is formed by The P well covered by the polysilicon gate is used to form a channel; the first side of the polysilicon gate is located above the P well, and the second side is located above the drift region.

A source region and a drain region composed of an N+ region, the source region is formed in the P well and self-aligned with the first side of the polysilicon gate, and the drain region is formed in the drift region.

A substrate lead-out region composed of a P+ region, the substrate lead-out region is formed in the P well and used to lead out the P well, and the substrate lead-out region is in lateral contact with the source region.

Field oxygen, located above the drift region between the P well and the drain region, the second side of the field oxygen is in lateral contact with the drain region, the first side of the field oxygen is in contact with the P well wells are spaced apart; the polysilicon gate extends above the field oxygen.

A PTOP layer is formed in the drift region with a space between the PTOP layer and a front surface of the drift region in a longitudinal direction.

The P-type doped implanted region and the N-type doped implanted region formed on the front surface of the drift region, in the vertical direction, each of the P-type doped implanted regions and each of the N-type doped implanted regions The front surface of the region extends toward the inside of the drift region, and the junction depths of each of the P-type doped implanted regions and each of the N-type doped implanted regions are the same, and each of the P-type doped implanted regions or each of the N-type doped implanted regions There is an interval between the bottom of the type doped implant region and the bottom PTOP layer; in the lateral direction, let the direction extending from the source region to the drain region be the channel length direction, and the channel length direction Vertical is the channel width direction, each of the P-type doped implanted regions and each of the N-type doped implanted regions is in a strip structure parallel to the channel length direction, each along the channel width direction The P-type doped implanted regions and each of the N-type doped implanted regions are arranged alternately, and each of the N-type doped implanted regions is used to increase the doping concentration of the surface of the drift region so as to reduce the concentration of the drift region. Each of the P-type doped implanted regions is used to achieve mutual depletion with the adjacent N-type doped implanted regions, so that the breakdown voltage of the device will not be affected by the surface doping of the drift region decreased with the increase of impurity concentration.

A further improvement is that the drift region is composed of a first N-type deep well, the P well is separated from the drift region by a certain distance, the P well is surrounded by a second N-type deep well, and the first N-type deep well The process conditions of the deep well and the second N-type deep well are the same and separated by a certain distance.

A further improvement is that the PTOP layer is also formed at the bottom of the P well.

A further improvement is that the semiconductor substrate is a silicon substrate.

A further improvement is that the gate dielectric layer is a gate oxide layer.

A further improvement is that the field oxygen is shallow trench field oxygen or local field oxygen.

A further improvement is that an interlayer film is formed on the front surface of the semiconductor substrate, and a source, drain and gate formed by a front metal layer are formed on the top of the interlayer film, and the source electrode passes through The contact hole of the interlayer film is in contact with the source region and the substrate lead-out region, the drain is in contact with the drain region through the contact hole passing through the interlayer film, and the gate is in contact with the drain region through the The contact hole passing through the interlayer film is in contact with the polysilicon gate.

A further improvement is that a polysilicon field plate is formed on the top of the field oxide near the drain region, and the polysilicon field plate is connected to the drain through a contact hole passing through the interlayer film.

A further improvement is that the operating voltage of NLDMOS devices is 700V.

In order to solve the above-mentioned technical problems, the manufacturing method of the NLDMOS device provided by the present invention comprises the following steps:

Step 1, forming an N-type doped drift region on a P-type semiconductor substrate.

Step 2, forming field oxygen above the drift region.

Step 3: Opening the P-well implantation region by photolithography and performing P-well implantation to form a P-well in the P-type semiconductor substrate, and the P-well is in contact with or separated from the side of the drift region by a certain distance.

Step 4: Open the PTOP implantation region by photolithography, perform PTOP implantation to form a PTOP layer in the drift region, and there is a space between the PTOP layer and the front surface of the drift region in the longitudinal direction.

Step 5. Form a P-type doped implantation region and an N-type doped implantation region on the front surface of the drift region by photolithography plus ion implantation; The N-type doped implanted region extends from the front surface of the drift region to the inside of the drift region, and the junction depths of each of the P-type doped implanted regions and each of the N-type doped implanted regions are the same, and each of the N-type doped implanted regions has the same junction depth. There is an interval between the bottom of the P-type doped implant region or each N-type doped implant region and the bottom PTOP layer; in the lateral direction, let the direction extending from the source region to the drain region be the channel length direction, and The direction perpendicular to the channel length direction is the channel width direction, and each of the P-type doped implanted regions and each of the N-type doped implanted regions has a strip structure parallel to the channel length direction. Each of the P-type doped implanted regions and each of the N-type doped implanted regions in the channel width direction is arranged alternately, and each of the N-type doped implanted regions is used to increase the doping concentration of the surface of the drift region Thereby reducing the on-resistance of the drift region, each of the P-type doped implanted regions is used to achieve mutual depletion with the adjacent N-type doped implanted regions, so that the breakdown voltage of the device will not be affected by the The increase of the surface doping concentration of the drift region decreases.

Step 6, forming a gate dielectric layer and a polysilicon gate, the polysilicon gate extends laterally from the P well to above the drift region, the P well covered by the polysilicon gate is used to form a channel, the The first side of the polysilicon gate is located above the P-well, and the second side is located above the field oxygen at the top of the drift region.

Step 7, perform N+ implantation to form the source region and the drain region, the source region is formed in the P well and self-aligned with the first side of the polysilicon gate, the drain region is formed in the In the drift region, the second side of the field oxygen is in lateral contact with the drain region.

Step 8: performing P+ implantation to form a substrate lead-out region, the substrate lead-out region is formed in the P well and used to lead the P well out, and the substrate lead-out region is in lateral contact with the source region.

A further improvement is that the drift region is composed of a first N-type deep well, the P well is separated from the drift region by a certain distance, and the P well is surrounded by a second N-type deep well. In step 1, photolithography is used to The process simultaneously opens the formation regions of the first N-type deep well and the second N-type deep well and performs N-type ion implantation to simultaneously form the first N-type deep well and the second N-type deep well.

A further improvement is that in step 4, the PTOP layer is formed at the bottom of the P well at the same time.

A further improvement is that the semiconductor substrate is a silicon substrate.

A further improvement is that the gate dielectric layer is a gate oxide layer.

A further improvement is that the field oxygen is shallow trench field oxygen formed by shallow trench isolation technology, or the field oxygen is local field oxygen formed by local field oxygen technology.

A further improvement is to also include the following steps:

Step 9, forming an interlayer film on the front surface of the semiconductor substrate.

Step 10, forming a contact hole passing through the interlayer film, the contact hole and the bottom corresponding to the source region and the substrate lead-out region, the drain region and the polysilicon gate contact.

Step eleven, forming a front metal layer on the top of the interlayer film and performing photolithography to form a source, a drain and a gate, and the source passes through the contact hole passing through the interlayer film and the source region and the substrate lead-out region, the drain is in contact with the drain region through a contact hole passing through the interlayer film, and the gate is in contact with the drain region through a contact hole passing through the interlayer film. polysilicon gate contact.

A further improvement is that in step 6, while forming the polysilicon gate, a polysilicon field plate is formed on the top of the field oxide near the drain region, and the polysilicon field plate passes through the interlayer film A contact hole is connected to the drain.

A further improvement is that the operating voltage of NLDMOS devices is 700V.

The NLDMOS device of the present invention can maintain a higher breakdown voltage by forming a PTOP layer in the drift region; at the same time, the present invention also forms a P-type doping implantation region and an N-type doping implantation at the position of the front surface of the drift region Each of the P-type and N-type doped implanted regions has a strip structure parallel to the channel length direction and is alternately arranged along the channel width direction. Each N-type doped implanted region can increase the drift on the source-drain channel The doping concentration on the surface of the drift region reduces the on-resistance of the drift region, and the P-type doping implantation region can deplete the adjacent N-type doping implantation region, so that the breakdown voltage of the device will not be affected by the surface of the drift region The increase of the doping concentration decreases, so the present invention can reduce the on-resistance of the device under the condition of maintaining a high breakdown voltage, thereby improving the performance of the device.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

FIG. 1 is a schematic structural diagram of an existing NLDMOS device;

FIG. 2A is a layout of an NLDMOS device according to an embodiment of the present invention;

FIG. 2B is a schematic diagram of a cross-sectional structure of the device along the tangent line AA of FIG. 2A;

FIG. 2C is a schematic diagram of a cross-sectional structure of the device along the tangent line BB of FIG. 2A;

3A-3H are schematic diagrams of device structures in each step of the method of the embodiment of the present invention.

detailed description

As shown in Figure 2A, it is the layout of the NLDMOS device of the embodiment of the present invention; as shown in Figure 2B, it is a schematic diagram of the cross-sectional structure of the device along the tangent AA of Figure 2A; as shown in Figure 2C, it is a device along the tangent BB of Figure 2A Schematic diagram of the cross-sectional structure; the operating voltage of the NLDMOS device in the embodiment of the present invention is 700V, including:

The N-type doped drift region is formed in the P-type semiconductor substrate 101 . The semiconductor substrate 101 is a silicon substrate.

A P well 104 is formed in the P-type semiconductor substrate 101 , and the P well 104 is in contact with or separated from a side of the drift region by a certain distance.

Preferably, the drift region is composed of a first N-type deep well 102a, the P well 104 is separated from the drift region by a certain distance, the P well 104 is surrounded by a second N-type deep well 102b, and the first The first N-type deep well 102a and the second N-type deep well 102b have the same process conditions and are separated by a certain distance.

The polysilicon gate 107 formed above the semiconductor substrate 101, the polysilicon gate 107 is isolated from the surface of the semiconductor substrate 101 by a gate dielectric layer 106 such as a gate oxide layer, and the polysilicon gate 107 is separated from the P The well 104 extends above the drift region, and the P well 104 covered by the polysilicon gate 107 is used to form a channel; the first side of the polysilicon gate 107 is located above the P well 104, and the second side is located above the drift region.

A source region 108b and a drain region 108a composed of an N+ region, the source region 108b is formed in the P well 104 and self-aligned with the first side of the polysilicon gate 107, the drain region 108a is formed in the in the drift zone.

A substrate lead-out region 109 composed of a P+ region, the substrate lead-out region 109 is formed in the P well 104 and is used to lead the P well 104 out, the substrate lead-out region 109 and the source region 108b laterally touch.

The field oxygen 103 is located above the drift region between the P well 104 and the drain region 108a, the second side of the field oxygen 103 is in lateral contact with the drain region 108a, and the second side of the field oxygen 103 One side is separated from the P well 104 by a certain distance; the polysilicon gate 107 extends above the field oxygen 103 . The field oxygen 103 is shallow trench field oxygen or local field oxygen.

A PTOP layer 105 is formed in the drift region, and there is a space between the PTOP layer 105 and the front surface of the drift region in the longitudinal direction.

The P-type doping implantation region 105a and the N-type doping implantation region 105b formed on the front surface of the drift region, vertically, each of the P-type doping implantation regions 105a and each of the N-type doping implantation regions 105b Extending from the front surface of the drift region to the inside of the drift region, and each of the P-type doped implanted regions 105a and each of the N-type doped implanted regions 105b has the same junction depth, and each of the P-type doped implanted regions 105b has the same junction depth. There is an interval between the bottom of the impurity implantation region 105a or each N-type dopant implantation region 105b and the bottom PTOP layer 105; in the lateral direction, let the direction extending from the source region 108b to the drain region 108a be the channel The channel length direction is perpendicular to the channel length direction, and each of the P-type doped implanted regions 105a and each of the N-type doped implanted regions 105b is parallel to the channel length direction. Each of the P-type doped implanted regions 105a and each of the N-type doped implanted regions 105b is arranged alternately along the channel width direction, and each of the N-type doped implanted regions 105b is used for Increase the doping concentration of the surface of the drift region to reduce the on-resistance of the drift region, and each of the P-type doped implanted regions 105a is used to achieve mutual dissipation with the adjacent N-type doped implanted region 105b. As far as possible, the breakdown voltage of the device will not decrease due to the increase of the surface doping concentration of the drift region.

An interlayer film 110 is formed on the front side of the semiconductor substrate 101, and a source, a drain, and a gate formed by a front metal layer 111 are formed on the top of the interlayer film 110, and the source passes through the The contact hole of the interlayer film 110 is in contact with the source region 108b and the substrate lead-out region 109, the drain is in contact with the drain region 108a through the contact hole passing through the interlayer film 110, the The gate is in contact with the polysilicon gate 107 through a contact hole passing through the interlayer film 110 .

A polysilicon field plate 107 a is formed on the top of the field oxygen 103 near the drain region 108 a, and the polysilicon field plate 107 a is connected to the drain through a contact hole passing through the interlayer film 110 .

As shown in Figure 3A to Figure 3H, it is a schematic diagram of the device structure in each step of the method of the embodiment of the present invention. The working voltage of the NLDMOS device of the manufacturing method of the NLDMOS device of the embodiment of the present invention is 700V, including the following steps:

Step 1, as shown in FIG. 3A , an N-type doped drift region is formed on the P-type P-type semiconductor substrate 101 . Preferably, the drift region is composed of a first N-type deep well 102a, and a second N-type deep well 102b is formed while forming the first N-type deep well 102a, and the second N-type deep well 102b and The first N-type deep wells 102a are separated by a certain distance, and the subsequently formed P-wells 104 are located in the second N-type deep wells 102b.

The semiconductor substrate 101 is a silicon substrate.

Step 2, as shown in FIG. 3B , forming field oxygen 103 above the drift region. The field oxygen 103 is a shallow trench field oxygen formed by a shallow trench isolation process (STI), or the field oxygen 103 is a local field oxygen formed by a local field oxygen process (LOCOS).

Step 3, as shown in FIG. 3C, open the P well 104 injection region by photolithography and perform P well 104 implantation to form a P well 104 in the P-type semiconductor substrate 101. In the embodiment of the present invention, the P well 104 is located in the P well 104. in the second N-type deep well 102b.

Step 4, as shown in FIG. 3D, open the PTOP injection region by photolithography, perform PTOP implantation to form a PTOP layer 105 in the drift region, and there is a space between the PTOP layer 105 and the front surface of the drift region in the vertical direction .

Step 5, as shown in Figure 3E, is a schematic diagram of the cross-sectional structure of the device along the tangent line AA in Figure 2A; as shown in Figure 3F, it is a schematic diagram of the cross-sectional structure of the device along the tangent line BB in Figure 2A; A P-type doping implantation region 105a and an N-type doping implantation region 105b are respectively formed on the front surface of the drift region. The front surface of the drift region extends toward the inside of the drift region, and the junction depths of each of the P-type doped implanted regions 105a and each of the N-type doped implanted regions 105b are the same, and each of the P-type doped implanted regions 105b has the same junction depth. There is an interval between the bottom of the region 105a or each N-type doped implant region 105b and the PTOP layer 105 at the bottom; in the lateral direction, let the direction extending from the source region 108b to the drain region 108a be the channel length The direction perpendicular to the channel length direction is the channel width direction, and each of the P-type doped implanted regions 105a and each of the N-type doped implanted regions 105b are strips parallel to the channel length direction. structure, each of the P-type doped implanted regions 105a and each of the N-type doped implanted regions 105b is arranged alternately along the channel width direction, and each of the N-type doped implanted regions 105b is used to increase the The doping concentration on the surface of the drift region reduces the on-resistance of the drift region, and each of the P-type doped implant regions 105a is used to achieve mutual depletion with the adjacent N-type doped implant regions 105b, The breakdown voltage of the device will not be reduced due to the increase of the surface doping concentration of the drift region.

Step 6, as shown in FIG. 3G , form a gate dielectric layer such as a gate oxide layer 106 and a polysilicon gate 107. The polysilicon gate 107 extends from the P well 104 to above the drift region in the lateral direction, and is covered by the polysilicon gate The P well 104 covered by 107 is used to form a channel, the first side of the polysilicon gate 107 is located above the P well 104 , and the second side is located above the field oxygen 103 at the top of the drift region.

In this step six, a polysilicon field plate 107 a is formed on the top of the field oxide 103 near the drain region 108 a while the polysilicon gate 107 is formed.

Step 7, as shown in FIG. 3H, perform N+ implantation to form a source region 108b and a drain region 108a, the source region 108b is formed in the P well 104 and self-aligned with the first side of the polysilicon gate 107, so The drain region 108a is formed in the drift region, and the second side of the field oxygen 103 is in lateral contact with the drain region 108a, that is, the drain region 108a and the second side of the field oxygen 103 are self-aligned .

Step 8, as shown in FIG. 3H, perform P+ implantation to form a substrate lead-out region 109, which is formed in the P well 104 and used to lead the P well 104 out, and the substrate lead-out region 109 is in lateral contact with the source region 108b.

Step 9, as shown in FIG. 2C , an interlayer film 110 is formed on the front surface of the semiconductor substrate 101 .

Step ten, as shown in FIG. 2C , form a contact hole through the interlayer film 110, the contact hole and the bottom correspond to the source region 108b and the substrate lead-out region 109, the drain region 108a and The polysilicon gate 107 contacts;

Step eleven, as shown in FIG. 2C , form a front metal layer 111 on the top of the interlayer film 110 and perform photolithography to form a source, a drain and a gate, and the source passes through the interlayer The contact hole of the film 110 is in contact with the source region 108b and the substrate lead-out region 109, the drain is in contact with the drain region 108a through the contact hole passing through the interlayer film 110, and the gate is in contact with the drain region 108a through the The contact hole passing through the interlayer film 110 is in contact with the polysilicon gate 107 . The polysilicon field plate 107 a is connected to the drain through a contact hole passing through the interlayer film 110 .

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (18)

1. A kind of NLDMOS device, is characterized in that, comprises: An N-type doped drift region is formed in a P-type semiconductor substrate; A P well is formed in the P-type semiconductor substrate, and the P well is in contact with or separated from the side of the drift region by a certain distance; A polysilicon gate formed above the semiconductor substrate, the polysilicon gate is isolated from the surface of the semiconductor substrate by a gate dielectric layer, and the polysilicon gate extends from the P well to above the drift region in the lateral direction, and is formed by The P well covered by the polysilicon gate is used to form a channel; the first side of the polysilicon gate is located above the P well, and the second side is located above the drift region; a source region and a drain region consisting of an N+ region, the source region being formed in the P well and self-aligned with the first side of the polysilicon gate, the drain region being formed in the drift region; a substrate lead-out region consisting of a P+ region, the substrate lead-out region being formed in the P well and used to lead the P well out, the substrate lead-out region and the source region being in lateral contact; Field oxygen, located above the drift region between the P well and the drain region, the second side of the field oxygen is in lateral contact with the drain region, the first side of the field oxygen is in contact with the P well the wells are separated by a distance; the polysilicon gate extends above the field oxygen; a PTOP layer formed in the drift region, with a space between the PTOP layer and the front surface of the drift region in the longitudinal direction; The P-type doped implanted region and the N-type doped implanted region formed on the front surface of the drift region, in the vertical direction, each of the P-type doped implanted regions and each of the N-type doped implanted regions The front surface of the region extends toward the inside of the drift region, and the junction depths of each of the P-type doped implanted regions and each of the N-type doped implanted regions are the same, and each of the P-type doped implanted regions or each of the N-type doped implanted regions There is an interval between the bottom of the type doped implant region and the bottom PTOP layer; in the lateral direction, let the direction extending from the source region to the drain region be the channel length direction, and the channel length direction Vertical is the channel width direction, each of the P-type doped implanted regions and each of the N-type doped implanted regions is in a strip structure parallel to the channel length direction, each along the channel width direction The P-type doped implanted regions and each of the N-type doped implanted regions are arranged alternately, and each of the N-type doped implanted regions is used to increase the doping concentration of the surface of the drift region so as to reduce the concentration of the drift region. Each of the P-type doped implanted regions is used to achieve mutual depletion with the adjacent N-type doped implanted regions, so that the breakdown voltage of the device will not be affected by the surface doping of the drift region decreased with the increase of impurity concentration. 2. The NLDMOS device according to claim 1, wherein the drift region is composed of a first N-type deep well, the P well is separated from the drift region by a certain distance, and the P well is surrounded by a second N-type deep well. The first N-type deep well and the second N-type deep well have the same process conditions and are separated by a certain distance. 3. The NLDMOS device according to claim 2, wherein the PTOP layer is also formed at the bottom of the P-well. 4. The NLDMOS device according to claim 1, wherein the semiconductor substrate is a silicon substrate. 5. The NLDMOS device according to claim 1, wherein the gate dielectric layer is a gate oxide layer. 6. The NLDMOS device according to claim 1, wherein the field oxygen is shallow trench field oxygen or local field oxygen. 7. The NLDMOS device according to claim 1, characterized in that: an interlayer film is formed on the front side of the semiconductor substrate, and a source electrode and a drain electrode formed by a front metal layer are formed on the top of the interlayer film and the gate, the source is in contact with the source region and the substrate lead-out region through the contact hole passing through the interlayer film, and the drain is in contact with the source region and the substrate lead-out region through the contact hole passing through the interlayer film The drain region is in contact, and the gate is in contact with the polysilicon gate through a contact hole passing through the interlayer film. 8. The NLDMOS device according to claim 7, characterized in that: a polysilicon field plate is formed on the top of the field oxygen near the drain region, and the polysilicon field plate passes through the interlayer film The contact hole connects the drain. 9. The NLDMOS device according to any one of claims 1 to 8, wherein the working voltage of the NLDMOS device is 700V. 10. A method for manufacturing an NLDMOS device, comprising the steps of: Step 1, forming an N-type doped drift region on the P-type semiconductor substrate; Step 2, forming field oxygen above the drift region; Step 3: Opening the P-well implantation region by photolithography and performing P-well implantation to form a P-well in the P-type semiconductor substrate, the P-well is in contact with the side of the drift region or is separated by a certain distance; Step 4, open the PTOP injection region by photolithography, perform PTOP injection to form a PTOP layer in the drift region, and there is a space between the PTOP layer and the front surface of the drift region in the longitudinal direction; Step 5. Form a P-type doped implantation region and an N-type doped implantation region on the front surface of the drift region by photolithography plus ion implantation; The N-type doped implanted region extends from the front surface of the drift region to the inside of the drift region, and the junction depths of each of the P-type doped implanted regions and each of the N-type doped implanted regions are the same, and each of the N-type doped implanted regions has the same junction depth. There is an interval between the bottom of the P-type doped implant region or each N-type doped implant region and the bottom PTOP layer; in the lateral direction, let the direction extending from the source region to the drain region be the channel length direction, and The direction perpendicular to the channel length direction is the channel width direction, and each of the P-type doped implanted regions and each of the N-type doped implanted regions is in a strip structure parallel to the channel length direction. Each of the P-type doped implanted regions and each of the N-type doped implanted regions in the channel width direction is arranged alternately, and each of the N-type doped implanted regions is used to increase the doping concentration on the surface of the drift region Thereby reducing the on-resistance of the drift region, each of the P-type doped implanted regions is used to achieve mutual depletion with the adjacent N-type doped implanted regions, so that the breakdown voltage of the device will not be affected by the The increase of the surface doping concentration of the drift region decreases; Step 6, forming a gate dielectric layer and a polysilicon gate, the polysilicon gate extends laterally from the P well to above the drift region, the P well covered by the polysilicon gate is used to form a channel, the The first side of the polysilicon gate is located above the P well, and the second side is located above the field oxygen at the top of the drift region; Step 7, perform N+ implantation to form the source region and the drain region, the source region is formed in the P well and self-aligned with the first side of the polysilicon gate, the drain region is formed in the In the drift region, the second side of the field oxygen is in lateral contact with the drain region; Step 8: performing P+ implantation to form a substrate lead-out region, the substrate lead-out region is formed in the P well and used to lead the P well out, and the substrate lead-out region is in lateral contact with the source region. 11. The method according to claim 10, wherein the drift region is composed of a first N-type deep well, the P well is separated from the drift region by a certain distance, and the P well is surrounded by a second N-type deep well. Surrounded by deep wells, in step 1, a photolithography process is used to simultaneously open the formation regions of the first N-type deep well and the second N-type deep well and perform N-type ion implantation to simultaneously form the first N-type deep well and the second N-type deep well The second N-type deep well. 12 . The method according to claim 11 , wherein in step 4, the PTOP layer is formed at the bottom of the P-well simultaneously. 13 . 13. The method of claim 10, wherein the semiconductor substrate is a silicon substrate. 14. The method according to claim 10, wherein the gate dielectric layer is a gate oxide layer. 15. The method according to claim 10, wherein the field oxygen is a shallow trench field oxygen formed by a shallow trench isolation process, or the field oxygen is a local field oxygen formed by a local field oxygen process. . 16. The method of claim 10, further comprising the steps of: Step 9, forming an interlayer film on the front surface of the semiconductor substrate; Step 10, forming a contact hole through the interlayer film, the contact hole and the bottom corresponding to the source region and the substrate lead-out region, the drain region and the polysilicon gate contact; Step eleven, forming a front metal layer on the top of the interlayer film and performing photolithography to form a source, a drain and a gate, and the source passes through the contact hole passing through the interlayer film and the source region and the substrate lead-out region, the drain is in contact with the drain region through a contact hole passing through the interlayer film, and the gate is in contact with the drain region through a contact hole passing through the interlayer film. polysilicon gate contact. 17. The method according to claim 16, wherein in step 6, a polysilicon field plate is formed on the top of the field oxygen at the side close to the drain region while forming the polysilicon gate, and the polysilicon field plate The plate is connected to the drain through a contact hole passing through the interlayer film. 18. The method according to any one of claims 10-17, wherein the working voltage of the NLDMOS device is 700V.