CN104935665A - Parallel data communication intermediate equipment and parallel data communication method - Google Patents
Parallel data communication intermediate equipment and parallel data communication method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/562—Brokering proxy services
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Abstract
The invention discloses parallel data communication intermediate equipment and a parallel data communication method, relating to the field of data transmission and aiming at providing data transmission intermediate equipment capable of transmitting the data to a lower computer simultaneously and transmitting the data received by the lower computer to an upper computer once, and a method. As for the technological points, the equipment comprises an upper computer interface circuit, N+1 data downlink buffers, N+1 data uplink buffers, a data switching center, N lower computer interface circuits and a logic control circuit. The upper computer interface circuit is in signal connection with the (N+1)th data downlink buffer and the (N+1)th data uplink buffer. The data switching center is in signal connection with all buffers. Each lower computer interface circuit is connected with one data downlink buffer and one data uplink buffer. The logic control circuit is in signal connection with the upper computer interface circuit, the data switching center and 16 lower computer interface circuits.
Description
Technical field
The present invention relates to field of data transmission, especially a kind of intermediate equipment of parallel data communication and method.
Background technology
Nowadays, mainly based on serial line interface (as RS232), a computer may there is 1 or multiple serial line interface in the communication interface of industrial computer.
But as computer upper computer software, if run into the serial line interface of multiple slave computer, so can only carry out exchanges data with each slave computer PORT COM successively, have a strong impact on the communication speed of host computer and slave computer like this, even there will be situations such as substitute.
If data can be sent to slave computer simultaneously, and the data that slave computer is received are disposable is sent to host computer, so just can solve problem.Nowadays, on chip market, have an a lot of serial line interface to be expanded into the chip of 2 or 4 serial line interfaces, but they still can not solve the problem of transmitted in parallel.
Summary of the invention
Technical problem to be solved by this invention is: for above-mentioned Problems existing, provides a kind of parallel data communication intermediate equipment and parallel data communication method.
Parallel data communication intermediate equipment provided by the invention comprises host computer interface circuit, a N+1 data down buffer storage device, a N+1 data uplink buffer, data switching center, N number of slave computer interface circuit and logic control circuit; Described N be greater than 0 integer.
Described host computer interface circuit has signal be connected with data downstream N+1 buffer, data uplink N+1 buffer respectively; Host computer interface circuit is used for receiving under the control of logic control circuit packet that host computer transmits and stored in data downstream N+1 buffer, and sends to host computer for the packet that reads under the control of logic control circuit in data uplink N+1 buffer.
Data switching center has signal with all buffers and is connected; Described data switching center to be used under the control of logic control circuit read data packet from N+1 buffer and according to the address in each packet by packet stored in data downstream the 1st buffer to data downstream N buffer, and under the control of logic control circuit from data uplink the 1st buffer to data uplink N buffer read data packet send to data uplink N+1 buffer.
1st slave computer interface circuit has signal be connected with data downstream the 1st buffer, data uplink the 1st buffer respectively; 2nd slave computer interface circuit has signal be connected with data downstream the 2nd buffer, data uplink the 2nd buffer respectively; By that analogy, N slave computer interface circuit has signal be connected with data downstream N buffer, data uplink N buffer respectively; Each slave computer interface circuit is used for receiving under the control of logic control circuit packet that connected slave computer transmits and by packet stored in connected data uplink buffer, and for being transferred to connected slave computer from connected data downstream buffer read data packet under the control of logic control circuit; Data content and slave computer address is at least comprised in described packet.
Further, N+1 level shifting circuit is also comprised; Host computer interface circuit connects host computer by N+1 level shifting circuit; 1st slave computer interface circuit, the 2nd slave computer interface circuit ..., N slave computer interface circuit respectively by the 1st level shifting circuit, the 2nd level shifting circuit ..., N level shifting circuit and the 1st slave computer, the 2nd slave computer ..., N slave computer connect.
Further, described data switching center be used for read data packet from N+1 buffer at the control periodical of logic control circuit and according to the address in each packet by packet stored in data downstream the 1st buffer to data downstream N buffer, and for the control periodical at logic control circuit from data uplink the 1st buffer to data uplink N buffer read data packet described packet is packed again according to certain format then send to data uplink N+1 buffer.
Present invention also offers a kind of parallel data communication method, comprise data downstream process and data uplink process;
Wherein data downstream process comprises:
Steps A 1: receive the packet that host computer transmits;
Steps A 2: by packet stored in data downstream N+1 buffer;
Steps A 3: read data packet from data downstream N+1 buffer and according to the address in packet by packet stored in data downstream the 1st buffer in data downstream N buffer;
Steps A 4: the packet in data downstream the 1st buffer is exported to the 1st slave computer, exports to the 2nd slave computer by the packet in data downstream the 2nd buffer, by that analogy, the packet in data downstream N buffer is exported to N slave computer;
Data uplink process comprises:
Step B1: the packet receiving n slave computer transmission;
Step B2: by the packet of the 1st slave computer transmission stored in data uplink the 1st buffer, by the packet of the 2nd slave computer transmission stored in data uplink the 2nd buffer, by that analogy, the packet transmitted by N slave computer is stored in data uplink N buffer;
Step B3: read data packet from data uplink the 1st buffer to data uplink N buffer; By described packet stored in data uplink N+1 buffer;
Step B4: by the data packet transmission in data uplink N+1 buffer to host computer;
Data content and slave computer address is at least comprised in described packet.
Preferably, in steps A 3, periodically from N+1 buffer read data packet and according to the address in each packet by packet stored in data downstream the 1st buffer to data downstream N buffer.
Further, in step B3, described packet is also packed according to certain format by read data packet again periodically from data uplink the 1st buffer to data uplink N buffer, then sends to data uplink N+1 buffer.
Further, in steps A 3, to read data packet from N+1 buffer to carry out after CRC check again by each packet stored in data downstream the 1st buffer to data downstream N buffer.
Further, in step B3, after CRC check is carried out to the packet read in from data uplink the 1st buffer to data uplink N buffer, send to data uplink N+1 buffer again.
In sum, owing to have employed technique scheme, the invention has the beneficial effects as follows:
1, autgmentability is strong, and the present invention supports multiple serial interface protocol, and multiple FPDP can be used to carry out data communication with slave computer respectively simultaneously;
2, the data uplink buffer that regular visit of the present invention is corresponding with slave computer, host computer is passed to after the data summarization that each slave computer is transmitted, the data downstream buffer that also regularly orientation is corresponding with host computer, each slave computer is given according to address distribution by the data of host computer, eliminate the time that host computer accesses slave computer data-interface successively, improve the operating efficiency of host computer.
3, can realize the present invention on FPGA, FPGA internal clock frequencies can reach 100MHz, transfer of data and the process upper time used, for serial line interface, negligible, achieves the high-speed transfer of data.On FPGA, realize the present invention in addition, can simplify a large amount of circuit, user can accomplish a chip solution substantially.
4, present invention further introduces CRC check, ensure that the reception correctness of data.
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is the circuit theory diagrams that in the present invention, device is connected with host computer, slave computer.
Fig. 2 is the first embodiment of device in the present invention.
Fig. 3 is the second embodiment of device in the present invention.
Fig. 4 is a specific embodiment of packet in the present invention.
Embodiment
All features disclosed in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Arbitrary feature disclosed in this specification, unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object.That is, unless specifically stated otherwise, each feature is an example in a series of equivalence or similar characteristics.
As Fig. 1, device in the present invention has at least N+1 interface, the communication port of one of them and host computer, as serial line interfaces such as RS232, RS485 or SPI, connect, all the other N number of interfaces are connected successively with the communication port of N number of slave computer, and the communication port of slave computer also can be the serial line interfaces such as RS232, RS485 or SPI.Wherein N be greater than 0 positive integer, in the present invention's specific embodiment, N is 16, and N can increase and decrease as required in other embodiments.
See Fig. 2, first embodiment of apparatus of the present invention comprises: host computer interface circuit, 17 data downstream FIFO, 17 data uplink FIFO, data switching center, 16 slave computer interface circuits and logic control circuits.
Described host computer interface circuit has signal be connected with data downstream 17FIFO, data uplink 17FIFO respectively.
Data switching center has signal with all FIFO and is connected.
1st slave computer interface circuit has signal be connected with data downstream 1FIFO, data uplink 1FIFO respectively; 2nd slave computer interface circuit has signal be connected with data downstream 2FIFO, data uplink 2FIFO respectively; By that analogy, the 16th slave computer interface circuit has signal be connected with data downstream 16FIFO, data uplink 16FIFO respectively.
Logic control circuit has signal with host computer interface circuit, data switching center and 16 slave computer interface circuits respectively and is connected, and controls various piece and carries out data upstream transmission and data downstream transmission according to certain sequential.
Wherein data downstream process:
Logic control circuit controls host computer interface circuit and receives packet that host computer transmits and stored in data downstream 17FIFO.Host computer interface circuit is except receiving except data also for transport protocol conversion in other embodiments.
Then, logic control circuit control data switching center from the 17th FIFO read data packet and according to the address in each packet by packet stored in data downstream 1FIFO to data downstream 16FIFO.Address in packet represents which slave computer this packet will be transferred to, if address is sensing the 5th slave computer, so data switching center by this Packet Generation in data downstream 5FIFO.
In other embodiments, logic control circuit control data switching center is read data packet from data downstream 17FIFO periodically, mentioned herely periodically refers to that data switching center just reads the packet in a data downstream 17FIFO at regular intervals.
Last logic control circuit controls each slave computer interface circuit from connected data downstream buffer read data packet and is transferred to connected slave computer.
Data uplink process:
First logic control circuit controls each slave computer interface circuit and receives packet that connected slave computer transmits and by packet stored in connected data uplink buffer.
Logic control circuit is control data switching center read data packet send to data uplink 17FIFO from data uplink 1FIFO to data uplink 16FIFO then.
Last logic control circuit controls host computer interface circuit and reads the packet in data uplink 17FIFO and send to host computer.
In other embodiments, logic control circuit control data switching center is read data packet from data uplink 1FIFO to data uplink 16FIFO periodically, each packet is synthesized larger packet according to certain der group, and is transferred to data uplink 17FIFO.The benefit done like this is, avoids the communication port that host computer accesses each slave computer successively, improves the operating efficiency of host computer.
See Fig. 3, in the present invention, device second embodiment has increased 17 level shifting circuits newly on the basis of the first embodiment, one of them level shifting circuit is connected with host computer interface circuit, between host computer and host computer interface, play the effect of level conversion, the signal adapting to host computer and host computer interface circuit level is passed to host computer and host computer interface circuit.Other 16 level shifting circuits are connected with 16 slave computer interface circuits respectively, play the effect of level conversion between each slave computer and slave computer interface circuit.The present embodiment is mainly used in host computer, the communication interface of host computer is RS232, RS485, needs the situation of carrying out level conversion.
First embodiment then uses the communication interface of host computer, slave computer for SPI, without the need to carrying out the situation of level conversion.
Present invention also offers a kind of parallel data communication method, comprise data downstream process and data uplink process;
Wherein data downstream process comprises:
Steps A 1: receive the packet that host computer transmits;
Steps A 2: by packet stored in data downstream N+1 buffer;
Steps A 3: read data packet from data downstream N+1 buffer and according to the address in packet by packet stored in data downstream the 1st buffer in data downstream N buffer;
Steps A 4: the packet in data downstream the 1st buffer is exported to the 1st slave computer, exports to the 2nd slave computer by the packet in data downstream the 2nd buffer, by that analogy, the packet in data downstream N buffer is exported to N slave computer;
Data uplink process comprises:
Step B1: the packet receiving n slave computer transmission;
Step B2: by the packet of the 1st slave computer transmission stored in data uplink the 1st buffer, by the packet of the 2nd slave computer transmission stored in data uplink the 2nd buffer, by that analogy, the packet transmitted by N slave computer is stored in data uplink N buffer;
Step B3: read data packet from data uplink the 1st buffer to data uplink N buffer; By described packet stored in data uplink N+1 buffer;
Step B4: by the data packet transmission in data uplink N+1 buffer to host computer.
In the steps A 3 of other embodiments, periodically from N+1 buffer read data packet and according to the address in each packet by packet stored in data downstream the 1st buffer to data downstream N buffer.In step B3, described packet is also packed according to certain format by read data packet again periodically from data uplink the 1st buffer to data uplink N buffer, then sends to data uplink N+1 buffer.
In the steps A 3 of another embodiment, to read data packet from N+1 buffer to carry out after CRC check again by each packet stored in data downstream the 1st buffer to data downstream N buffer.In step B3, after CRC check is carried out to the packet read in from data uplink the 1st buffer to data uplink N buffer, send to data uplink N+1 buffer again.
Packet in the present invention at least should comprise the data content of needs transmission and the slave computer address information of correspondence, and address information shows that this packet will pass past slave computer, or which slave computer this packet comes from.See Fig. 4, in a preferred embodiment, the form of packet comprises frame head, destination address, command type, length, data encryption district, CRC check code and postamble.The form of packet can customize according to the content of concrete transmission, the data packet format in the present embodiment should be interpreted as limitation of the present invention.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature of disclosing in this manual or any combination newly, and the step of the arbitrary new method disclosed or process or any combination newly.
Claims (8)
1. a parallel data communication intermediate equipment, is characterized in that, comprises host computer interface circuit, a N+1 data down buffer storage device, a N+1 data uplink buffer, data switching center, N number of slave computer interface circuit and logic control circuit; Described N be greater than 0 integer;
Described host computer interface circuit has signal be connected with data downstream N+1 buffer, data uplink N+1 buffer respectively; Host computer interface circuit is used for receiving under the control of logic control circuit packet that host computer transmits and stored in data downstream N+1 buffer, and sends to host computer for the packet that reads under the control of logic control circuit in data uplink N+1 buffer;
Data switching center has signal with all buffers and is connected; Described data switching center to be used under the control of logic control circuit read data packet from N+1 buffer and according to the address in each packet by packet stored in data downstream the 1st buffer to data downstream N buffer, and under the control of logic control circuit from data uplink the 1st buffer to data uplink N buffer read data packet send to data uplink N+1 buffer;
1st slave computer interface circuit has signal be connected with data downstream the 1st buffer, data uplink the 1st buffer respectively; 2nd slave computer interface circuit has signal be connected with data downstream the 2nd buffer, data uplink the 2nd buffer respectively; By that analogy, N slave computer interface circuit has signal be connected with data downstream N buffer, data uplink N buffer respectively; Each slave computer interface circuit is used for receiving under the control of logic control circuit packet that connected slave computer transmits and by packet stored in connected data uplink buffer, and for being transferred to connected slave computer from connected data downstream buffer read data packet under the control of logic control circuit;
Data content and slave computer address is at least comprised in described packet.
2. a kind of parallel data communication intermediate equipment according to claim 1, is characterized in that, also comprises N+1 level shifting circuit; Host computer interface circuit connects host computer by N+1 level shifting circuit; 1st slave computer interface circuit, the 2nd slave computer interface circuit ..., N slave computer interface circuit respectively by the 1st level shifting circuit, the 2nd level shifting circuit ..., N level shifting circuit and the 1st slave computer, the 2nd slave computer ..., N slave computer connect.
3. a kind of parallel data communication intermediate equipment according to claim 1, it is characterized in that, described data switching center be used for the control periodical of logic control circuit read data packet from N+1 buffer and according to the address in each packet by packet stored in data downstream the 1st buffer to data downstream N buffer, and for the control periodical at logic control circuit from data uplink the 1st buffer to data uplink N buffer read data packet described packet is packed again according to certain format then send to data uplink N+1 buffer.
4. a parallel data communication method, is characterized in that, comprises data downstream process and data uplink process;
Wherein data downstream process comprises:
Steps A 1: receive the packet that host computer transmits;
Steps A 2: by packet stored in data downstream N+1 buffer;
Steps A 3: read data packet from data downstream N+1 buffer and according to the address in packet by packet stored in data downstream the 1st buffer in data downstream N buffer;
Steps A 4: the packet in data downstream the 1st buffer is exported to the 1st slave computer, exports to the 2nd slave computer by the packet in data downstream the 2nd buffer, by that analogy, the packet in data downstream N buffer is exported to N slave computer;
Data uplink process comprises:
Step B1: the packet receiving n slave computer transmission;
Step B2: by the packet of the 1st slave computer transmission stored in data uplink the 1st buffer, by the packet of the 2nd slave computer transmission stored in data uplink the 2nd buffer, by that analogy, the packet transmitted by N slave computer is stored in data uplink N buffer;
Step B3: read data packet from data uplink the 1st buffer to data uplink N buffer; By described packet stored in data uplink N+1 buffer;
Step B4: by the data packet transmission in data uplink N+1 buffer to host computer;
Data content and slave computer address is at least comprised in described packet.
5. a kind of parallel data communication method according to claim 4, it is characterized in that, in steps A 3, periodically from N+1 buffer read data packet and according to the address in each packet by packet stored in data downstream the 1st buffer to data downstream N buffer.
6. a kind of parallel data communication method according to claim 5, it is characterized in that, in step B3, described packet is also packed according to certain format by read data packet again periodically from data uplink the 1st buffer to data uplink N buffer, then sends to data uplink N+1 buffer.
7. a kind of parallel data communication method according to claim 4, it is characterized in that, in steps A 3, to read data packet from N+1 buffer to carry out after CRC check again by each packet stored in data downstream the 1st buffer to data downstream N buffer.
8. a kind of parallel data communication method according to claim 4 or 7, it is characterized in that, in step B3, after CRC check is carried out to the packet read in from data uplink the 1st buffer to data uplink N buffer, send to data uplink N+1 buffer again.
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| CN108170618A (en) * | 2017-12-28 | 2018-06-15 | 施耐德万高（天津）电气设备有限公司 | Buffer structure and its software control method based on RS485 buses |
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Address after: No.3, 11th floor, building 6, no.599, shijicheng South Road, high tech Zone, Chengdu 610041, China (Sichuan) pilot Free Trade Zone, Chengdu, Sichuan Province Patentee after: Houpu intelligent IOT Technology Co.,Ltd. Address before: 610041 No. 6, No. 1103, D District, 216 century South Road, Chengdu hi tech Zone, Sichuan, China Patentee before: CHENGDU HUAQI HOUPU ELECTRONIC TECHNOLOGY Co.,Ltd. |