CN104716035A - Chemical mechanical polishing method - Google Patents

Abstract

The invention discloses a chemical mechanical polishing method. The method includes: providing a semiconductor substrate on which a dummy gate is formed; forming an etch stop layer covering the dummy gate and the semiconductor substrate and an interlayer covering the etch stop layer Dielectric layer; performing first chemical mechanical polishing to expose the etch stop layer at the top of the dummy gate; forming a sacrificial layer on the polished interlayer dielectric layer and on the polished etch stop layer; and performing second chemical mechanical polishing to expose the dummy gate. According to the chemical mechanical polishing method of the present invention, the bridging problem is avoided, and it also has the advantages of high polishing efficiency, good polishing surface flatness and the like.

Description

chemical mechanical polishing method

technical field

The invention relates to the technical field of semiconductors, in particular to a chemical mechanical polishing method.

Background technique

When the size of a semiconductor device is further reduced, for example, a technology node smaller than 32nm, a metal gate can be used instead of a polysilicon gate. However, the metal gate faces the challenge of planarizing the interlayer dielectric layer during the fabrication process. For example, when a chemical mechanical polishing process is used to planarize the interlayer dielectric layer, deep scratches and pits may be formed on the polished interlayer dielectric layer. In the subsequent process of forming the metal gate, the metal will fill the scratches and pits on the interlayer dielectric layer, which will cause bridge issues and cause the semiconductor device to be scrapped, and the yield rate of the product will be greatly reduced.

Therefore, it is necessary to propose a chemical mechanical polishing method to solve the problems existing in the prior art.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

The invention provides a chemical mechanical polishing method. The method includes: providing a semiconductor substrate on which a dummy gate is formed; forming an etch stop layer covering the dummy gate and the semiconductor substrate and a layer covering the etch stop layer an interlayer dielectric layer; performing a first chemical mechanical polishing to expose the etch stop layer at the top of the dummy gate; forming a sacrificial layer on the polished interlayer dielectric layer and on the polished etch stop layer; and The second chemical mechanical polishing is performed until the dummy gate is exposed.

Preferably, the first chemical mechanical polishing is a polishing process using a fixed abrasive polishing pad.

Preferably, the abrasive particles on the fixed abrasive polishing pad have a high abrasive selectivity ratio.

Preferably, the abrasive particles are CeO ₂ and/or SiO ₂ .

Preferably, the second chemical mechanical polishing is a polishing process using a non-selective abrasive slurry.

Preferably, the thickness of the sacrificial layer is

Preferably, the method further includes: removing the dummy gate to form an opening; forming a metal gate structure in the opening.

Preferably, the material of the etching stop layer is a SiN layer.

Preferably, the material of the interlayer dielectric layer is silicon oxide.

Preferably, the method further includes forming spacers on both sides of the dummy gate after forming the dummy gate and before forming the etch stop layer, wherein the etch stop layer covers the dummy gate , the sidewall and the semiconductor substrate.

According to the chemical mechanical polishing method of the present invention, by re-depositing a layer of sacrificial layer on the interlayer dielectric layer and the etch stop layer after the first chemical mechanical polishing, to fill the gap between the layers in the first chemical mechanical polishing process scratches and pits on the dielectric layer and etch stop layer, and perform a second chemical mechanical polishing to avoid bridging problems. Therefore, the method provided by the present invention also has the advantages of high polishing efficiency, good polishing surface flatness and the like.

The advantages and features of the present invention will be described in detail below in conjunction with the accompanying drawings.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention. In the attached picture,

1 is a flow chart of a method for chemical mechanical polishing according to an embodiment of the present invention; and

2A-2H are cross-sectional views of devices obtained by performing various steps in the chemical mechanical polishing process using the method shown in FIG. 1 .

Detailed ways

Next, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer.

According to one aspect of the present invention, a method of chemical mechanical polishing is provided. The present invention will be described in detail below in conjunction with the flowchart of a chemical mechanical polishing method according to an embodiment of the present invention shown in FIG. 1 and the schematic structural diagrams of semiconductor devices shown in FIGS. 2A-2H .

Step S110 is executed: providing a semiconductor substrate on which a dummy gate is formed.

As shown in FIG. 2A , a semiconductor substrate 210 is provided, and the semiconductor substrate 210 may be silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-on-insulator At least one of silicon germanium (SiGeOI) and germanium-on-insulator (GeOI). Shallow trench isolation (STI) for isolating the active region can be formed in the semiconductor substrate 210, and the shallow trench isolation can be made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped glass and/or other existing formed of low dielectric materials. Of course, doped wells (not shown) and the like may also be formed in the semiconductor substrate 210 . For the sake of brevity, only boxes are used here.

A gate dielectric material layer 220 ′ is formed on the semiconductor substrate 210 . The gate dielectric material layer 220' may include conventional dielectric materials such as oxides (eg, SiO ₂ ), nitrides (eg, Si ₃ N ₄ ) and nitrogen oxides (eg SiON, SiON ₂ ). The gate dielectric material layer 220 ′ made of silicon oxide can be formed by an oxidation process known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like. The gate dielectric material layer 220 ′ made of silicon nitride can be formed by a nitridation process such as high temperature furnace tube nitridation, rapid thermal annealing nitridation or plasma nitridation. Further performing a nitridation process on silicon oxide can form a gate dielectric material layer 220 ′ made of silicon oxynitride.

Alternatively, the layer of gate dielectric material 220' may also include a generally higher K material having a K of from about 20 to at least about 100. Such higher K materials may include, but are not limited to: hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium etc. It can be formed using any suitable formation process. Such as chemical vapor deposition, physical vapor deposition, etc.

A dummy gate material layer 230' is formed on the gate dielectric material layer 220'. The dummy gate material layer 230' can be, for example, polysilicon. The polysilicon can be formed by a low-pressure chemical vapor deposition (LPCVD) process.

As shown in FIG. 2B, the dummy gate material layer 230' and the gate dielectric material layer 220' are etched to form the dummy gate 230 and the gate dielectric layer 220. As an example, the dummy gate material layer 230' and the gate dielectric material layer 220' may be etched by photolithography. Firstly, a photoresist is formed on the dummy gate material layer 230', and it is exposed and developed in alignment with a mask to form a photoresist layer with a dummy gate pattern. Wherein, in order to reduce the reflection of light on the lower surface of the photoresist layer during the exposure process, so that most of the energy of the exposure is absorbed by the photoresist, a Anti-reflective coating. In addition, in order to ensure that the pattern in the photoresist layer can be accurately transferred to the dummy gate material layer 230', a hard mask layer can also be provided between the dummy gate material layer 230' and the anti-reflection coating. The hard mask layer can be one or more of SiN, SiON, SiC and oxide. The hard mask layer can make the formed pattern more accurate during the etching process.

Secondly, using the patterned photoresist layer as a mask, the dummy gate material layer 230' and the gate dielectric material layer 220' are etched to form the dummy gate 230 and the gate dielectric layer 220. Etching may be performed by an etching process such as plasma etching. Wherein, in the case where the anti-reflection coating and/or hard mask layer is provided, the pattern in the photoresist layer can be transferred to the anti-reflection coating and/or hard mask layer first, and the anti-reflection coating layer and/or the hard mask layer as a mask to etch the dummy gate material layer 230 ′ and the gate dielectric material layer 220 ′ to form the dummy gate 230 and the gate dielectric layer 220 .

In addition, in an embodiment according to the present invention, spacers 240 may also be formed on both sides of the dummy gate 230 as shown in FIG. 2B . The material of the sidewall 240 may be at least one of oxide, nitride or oxynitride, for example. It can be formed by known deposition and etching. The sidewall 240 can protect the sidewall of the gate structure from damage during subsequent etching or ion implantation. It can also form regions with different doping concentrations in the source and drain electrodes.

Step S120 is performed: forming an etching stop layer covering the dummy gate and the semiconductor substrate, and an interlayer dielectric layer covering the etching stop layer.

As shown in FIG. 2C , an etch stop layer 250 covering the dummy gate 230 and the semiconductor substrate 210 is formed. Here, it is preferably a contact hole etching stop layer, and the material is silicon nitride. In the semiconductor device structure formed with the spacer 240 , the etch stop layer 250 should also cover the sidewall 240 . The etch stop layer 250 can be formed by a suitable deposition process such as physical vapor deposition, chemical vapor deposition, or other nitridation processes. Here, no more details.

Next, as shown in FIG. 2C , an interlayer dielectric layer 260 covering the etch stop layer is formed on the etch stop layer 250 . The interlayer dielectric layer 260 may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, Examples include undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).

Executing step S130: performing a first chemical mechanical polishing until the etching stop layer on the top of the dummy gate is exposed.

As shown in FIG. 2D , a first chemical mechanical polishing is performed to expose the etch stop layer 250 on the top of the dummy gate. The principle of chemical mechanical polishing includes the combination of chemical and mechanical effects. On the surface of the material layer to be polished, a specific layer is formed due to a chemical reaction, and then the specific layer is removed mechanically. Chemical mechanical polishing can be performed on a fixed abrasive polishing pad, where abrasive particles are immobilized on the pad. Chemical mechanical polishing can also be performed on non-consolidated abrasive pads (such as free abrasive slurry pads), where the abrasive particles can be in granular form and suspended in a liquid carrier. Preferably, in an embodiment according to the present invention, the first chemical mechanical polishing is performed using a fixed abrasive polishing pad. In this case, only the protruding parts (abrasive particles) of the abrasive slurry layer solidified on the polishing pad act on the contact parts of the surface to be polished, compared to traditional non-consolidated abrasive polishing pads (such as free Abrasive polishing pads), the contact area is reduced, the small contact area produces local greater pressure, and the polishing rate is greatly improved. In addition, its polishing rate has high selectivity for the surface morphology of the surface to be polished, and only a small amount of removal is required to achieve the purpose of planarization.

Preferably, the abrasive particles on the fixed abrasive polishing pad have a high abrasive selectivity. For example, in one embodiment according to the present invention, the abrasive particles have a high polishing rate for the interlayer dielectric layer 260 (such as silicon oxide), but have a very low polishing rate for the etch stop layer (such as SiN). . Preferably, the abrasive particles are CeO ₂ and/or SiO ₂ . Therefore, the first CMP can be easily terminated at the etch stop layer 250 .

Executing step S140 : forming a sacrificial layer on the polished interlayer dielectric layer and the polished etch stop layer.

After the first chemical mechanical polishing process, deep scratches and/or pits may be formed on the polished interlayer dielectric layer 260 and the polished etch stop layer 250 . For example, after chemical mechanical polishing using a fixed abrasive polishing pad, hundreds of Deep scratches and/or dents. The scratches and/or pits may go deep into the interlayer dielectric layer 260 below the upper surface of the dummy gate 230, resulting in the subsequent polishing of the dummy gate 230 on the surface of the interlayer dielectric layer 260. Leave scratches and/or dents. In the subsequent process shown in FIGS. 2G-2H , when the dummy gate 230 is removed to form the opening 280 ′, and the metal gate structure 280 is formed in the opening 280 ′, since the interlayer dielectric layer 260 still remains Scratches and/or pits. When the metal gate structure 280 is formed, the metal will fill the scratches and/or pits, thereby causing the bridging problem mentioned above.

Therefore, process improvements can be made. As shown in FIG. 2E , a sacrificial layer 270 is formed on the polished interlayer dielectric layer 260 and on the polished etch stop layer 250 . The sacrificial layer is preferably made of the same material as the interlayer dielectric layer 260 , for example, silicon oxide or the like. The sacrificial layer 270 can fill up the scratches and/or pits generated during the first chemical mechanical polishing process, thus preventing the metal in the metal gate from filling the scratches and/or pits in subsequent processes. The thickness of the sacrificial layer 270 can be The thickness of the sacrificial layer 270 is within this range, which can ensure that the scratches and/or pits are filled, and will not require a long polishing time because the sacrificial layer 270 is too thick in the subsequent second chemical mechanical polishing process .

Executing step S150: performing a second chemical mechanical polishing until the dummy gate is exposed.

As shown in FIG. 2F , the second chemical mechanical polishing is performed until the dummy gate 230 is exposed. Preferably, the second chemical mechanical polishing is a polishing process using a non-selective abrasive slurry. The abrasive slurry has substantially the same polishing rate for nitrides and oxides. The use of a non-selective abrasive slurry enables a very flat surface after the second chemical mechanical polishing.

In actual operation, the polishing rate of the nitride is generally lower than that of the oxide, so the surface of the nitride after the first chemical mechanical polishing and the second chemical mechanical polishing is slightly higher than the surface of the oxide.

Next, when the interlayer dielectric layer 260 and the dummy gate 230 are polished to be flat, a metal gate structure 280 may be further formed. As shown in FIG. 2G, the dummy gate 230 is removed to form an opening 280'. The dummy gate 230 can be removed by an etching process known to those skilled in the art, which will not be repeated here. After the opening 280' is formed, a barrier layer (not shown) may also be deposited on the gate dielectric layer 220 in the opening 280' to prevent the metal gate material to be subsequently formed on the gate dielectric layer 220 from diffusing. onto the gate dielectric layer 220. The barrier layer may include, for example, TiN, TaN, or the like. The barrier layer can be formed by, for example, atomic layer deposition or other suitable means. In addition, a work function layer (not shown) may also be formed on the gate dielectric layer 220 or the barrier layer within the opening 280' to provide a high effective work function (EWF) value. The work function layer may include one or more of Ti, TaN, TiN, AlCO, TiAlN. The work function layer can be formed by atomic layer deposition or other suitable methods.

As shown in FIG. 2H, a metal gate structure 280 is formed within opening 280' (see FIG. 2G). The metal gate structure 280 can be selected from high-K metal materials with lower resistivity, such as aluminum gates, tungsten gates, and the like. It can be formed by suitable methods such as physical vapor deposition and chemical vapor deposition.

In summary, according to the chemical mechanical polishing method of the present invention, a sacrificial layer is re-deposited on the interlayer dielectric layer 260 and the etch stop layer 250 after the first chemical mechanical polishing, so as to fill the The scratches and pits generated on the interlayer dielectric layer 260 and the etch stop layer 250 during the mechanical polishing process are subjected to a second chemical mechanical polishing, thereby avoiding the aforementioned bridging problem. Therefore, the method provided by the present invention also has the advantages of high polishing efficiency, good polishing surface flatness and the like.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (10)

1. A method for chemical mechanical polishing, characterized in that the method comprises: providing a semiconductor substrate on which a dummy gate is formed; forming an etch stop layer covering the dummy gate and the semiconductor substrate and an interlayer dielectric layer covering the etch stop layer; performing a first chemical mechanical polishing until the etch stop layer on the top of the dummy gate is exposed; forming a sacrificial layer on the polished interlayer dielectric layer and on the polished etch stop layer; and The second chemical mechanical polishing is performed until the dummy gate is exposed. 2. The method according to claim 1, wherein the first chemical mechanical polishing is a polishing process using a fixed abrasive polishing pad. 3. The method of claim 2, wherein the abrasive particles on the fixed abrasive polishing pad have a high abrasive selectivity. 4. The method according to claim 3, wherein the abrasive particles are _CeO2 and/or _SiO2 . 5. The method according to claim 2, wherein the second chemical mechanical polishing is a polishing process using a non-selective abrasive slurry. 6. method as claimed in claim 1, is characterized in that, the thickness of described sacrificial layer is 7. The method of claim 1, further comprising: removing the dummy gate to form an opening; A metal gate structure is formed within the opening. 8. The method according to claim 1, wherein the material of the etching stop layer is a SiN layer. 9. The method of claim 1, wherein the material of the interlayer dielectric layer is silicon oxide. 10. The method according to claim 1, further comprising forming spacers on both sides of the dummy gate after forming the dummy gate and before forming the etch stop layer, wherein The etching stop layer covers the dummy gate, the spacer and the semiconductor substrate.