CN104659204B - Resistive memory element and method of operation thereof - Google Patents

Abstract

A resistive memory element. The isolation structures are disposed in the substrate and extend along a first direction. The plurality of word lines are disposed on the substrate and extend along a second direction different from the first direction. At least one doped region is disposed in the substrate between two adjacent word lines. The conductive layer is disposed on the word line. The conductive layer is provided with a plurality of conductive blocks and a plurality of leads extending along the second direction, at least one conductive block is arranged between two adjacent leads, and the leads and the conductive blocks are electrically connected with the doped region. The variable resistance blocks are respectively arranged on the conducting blocks and electrically connected with the conducting blocks. The bit lines extending along the first direction are arranged on the conductive layer and electrically connected with the variable resistance block. A method for operating the resistive memory element is also provided.

Description

Resistive memory element and method of operation thereof

technical field

The present invention relates to a semiconductor device and its operating method, and more particularly to a resistive memory element and its operating method.

Background technique

The non-volatile memory has the advantage that the stored data will not disappear after power off, so it is a necessary storage element for many electrical products to maintain normal operation. At present, resistive random access memory (resistive random access memory, RRAM) is a non-volatile memory that is actively developed in the industry. It has low write operation voltage, short write and erase time, long memory time, non The advantages of destructive reading, multi-state memory, simple structure, and small required area have great potential for application in future personal computers and electronic devices.

In an RRAM array (array), in order to reduce the size of memory cells, it is a conventional practice to connect all source regions to source lines. For bipolar switching type PRAM, 0V voltage is applied to the source line during SET operation, but reset voltage (VRESET) is applied during RESET operation. ) to the source line. In this case, the voltage state of the source line switches repeatedly, and such voltage switching requires a large driving current and a long programming time, thereby degrading the performance of the device.

Contents of the invention

In view of this, the present invention provides a resistive memory element and its operation method, by dividing the source line into a grounded source line and a reset source line, and maintaining the stability of the respective voltages, the programming time can be greatly reduced time, improve the performance of components.

The invention provides a resistive memory element, which includes a plurality of isolation structures, a plurality of word lines, a conductive layer, a plurality of variable resistance blocks and a plurality of bit lines. A plurality of isolation structures are arranged in the substrate and extend along the first direction. A plurality of word lines are arranged on the substrate and extend along the second direction. The second direction is different from the first direction. At least one doped region is configured in the substrate between two adjacent word lines. The conductive layer is configured on the character line. The conductive layer has a plurality of conductive blocks and a plurality of wires extending along the second direction, at least one conductive block is arranged between two adjacent wires, and the wires and the conductive block are electrically connected to the doping region. The wires include a plurality of first wires and a plurality of second wires arranged alternately, the first wires are used for ground potential (0V voltage), and the second wires are used for connecting a reset voltage to reset the resistive memory element . A plurality of variable resistance blocks are respectively arranged on the conductive block and electrically connected with the conductive block. A plurality of bit lines extending along the first direction are disposed on the conductive layer and electrically connected with the variable resistance block.

In an embodiment of the present invention, the above-mentioned second direction is perpendicular to the first direction.

In an embodiment of the present invention, the wires of the above-mentioned conductive layer and the conductive blocks are located on the same plane.

In an embodiment of the present invention, the doped region includes a plurality of source regions and a plurality of drain regions, the wire is electrically connected to the source region, and the conductive block is electrically connected to the drain region.

In an embodiment of the present invention, the above-mentioned wires and the conductive block are electrically connected to the doped region through a plurality of first conductive plugs.

In an embodiment of the present invention, the variable resistance block is electrically connected to the conductive block through a plurality of second conductive plugs.

In an embodiment of the present invention, the bit line is electrically connected to the variable resistance block through a plurality of third conductive plugs.

In an embodiment of the present invention, each variable resistance block includes a bottom electrode, a top electrode, and a variable resistance layer between the bottom electrode and the top electrode.

In an embodiment of the present invention, the resistive memory element further includes at least one insulating layer for isolating the word line from the conductive layer, the variable resistance block and the bit line from each other.

In an embodiment of the present invention, the word lines include a plurality of first word lines and a plurality of second word lines arranged alternately.

The present invention further provides a method for operating a resistive memory element, which is used to operate the resistive memory element as described above. The above operating method includes: when in the setting mode, applying a first AC voltage to the first word line, A voltage of 0V is applied to the second word line, a second AC voltage is applied to the bit line, a voltage of 0V is applied to the substrate, a voltage of 0V is applied to the first wire, and a DC reset voltage is applied to the second wire.

In an embodiment of the present invention, the above operation method further includes: when in the reset mode, applying a 0V voltage to the first word line, applying a third AC voltage to the second word line, applying a 0V voltage to the bit line, applying A voltage of 0V is applied to the substrate, a voltage of 0V is applied to the first wire, and a DC reset voltage is applied to the second wire.

The present invention further proposes a resistive memory element, which includes a plurality of memory cells, and each memory cell includes two gates, a drain node, a variable resistance block, a conductor layer, and two source nodes. The drain node is located between the gates. The variable resistance block is electrically connected to the drain node. The conductor layer is electrically connected to the variable resistance block. The two source nodes are respectively located outside the gate, wherein one of the source nodes is used for ground potential (0V voltage), and the other of the source nodes is used for receiving a reset voltage to reset the memory cell.

Based on the above, in the resistive memory element of the present invention, the source line is divided into a grounded source line and a reset source line, and the grounded source line is grounded no matter during a set (SET) operation or a reset (RESET) operation. The voltages of the source line and the reset source line are kept constant, and conventional voltage switching is not required. Therefore, the programming time can be greatly reduced to improve the performance of components.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of a resistive memory device according to an embodiment of the present invention.

FIG. 2A is a schematic cross-sectional view along line II' of FIG. 1 .

FIG. 2B is a schematic cross-sectional view along line II-II' of FIG. 1 .

FIG. 2C is a schematic cross-sectional view along line III-III' of FIG. 1 .

FIG. 3 is a schematic top view of a source line of a resistive memory device according to an embodiment of the invention.

Wherein, the reference signs are explained as follows:

10: Resistive memory element

100: Substrate

102: Isolation structure

104: active area

105a, 105b: gate insulating layer

106a, 106b: gate structure

107a, 107b: grid

108: doped area

108a: source region

108b: drain region

109a, 109b: mask layer

110, 118, 122, 124: insulating layer

111a, 111b: spacers

112: conductive layer

113a, 113b: wires

115: Conductive block

117: bottom electrode

119: variable resistance layer

121: top electrode

114, 116, 123, 127: Conductive plug

120: variable resistance block

126: bit line

A: storage unit

detailed description

FIG. 1 is a schematic top view of a resistive memory device according to an embodiment of the present invention. FIG. 2A is a schematic cross-sectional view along line II' of FIG. 1 . FIG. 2B is a schematic cross-sectional view along line II-II' of FIG. 1 . FIG. 2C is a schematic cross-sectional view along line III-III' of FIG. 1 . In FIG. 1 , for the sake of clarity, components such as the substrate, doped regions, conductive plugs, and insulating layers are not shown, but the configuration/position of these components can be clearly seen in other cross-sections.

Please refer to FIG. 1 and FIG. 2A to FIG. 2C at the same time. The resistive memory element 10 of the present invention includes multiple isolation structures 102, multiple gate structures 106a and 106b, a conductive layer 112, multiple variable resistance blocks 120, multiple A bit line 126 and a plurality of insulating layers 110 , 118 , 122 and 124 .

A plurality of isolation structures 102 are disposed in the substrate 100 and extend along a first direction. In an embodiment, the first direction is, for example, the X direction. The isolation structure 102 is, for example, a shallow trench isolation (STI) structure, and its material includes silicon oxide. The area between the isolation structures 102 is the active area (AA) 104 .

A plurality of gate structures 106a and 106b are disposed on the substrate 100 and extend along a second direction different from the first direction. In an embodiment, the second direction is, for example, the Y direction. In one embodiment, the gate structures 106 a and the gate structures 106 b are arranged alternately. Each gate structure 106a includes (from bottom to top) a gate insulating layer 105a, a gate 107a, and a mask layer 109a. Similarly, each gate structure 106b includes (from bottom to top) a gate insulating layer 105b, a gate 107b, and a mask layer 109b. The material of the gate insulating layer 105a/105b includes silicon oxide. The gate 107a/107b can be a single-layer or multi-layer structure, and its material includes doped polysilicon, tungsten or a combination thereof. In this embodiment, both the gates 107a and 107b serve as word lines of the resistive memory device 10 . The material of the mask layers 109a, 109b includes silicon nitride. Each gate structure 106a, 106b may further include spacers 111a, 111b, respectively. The material of the spacers 111a, 111b includes insulating materials, such as silicon oxide.

In addition, at least one doped region 108 is disposed in the substrate 100 between two adjacent word lines (ie gates 107a, 107b). In this embodiment, it is illustrated by taking four doped regions 108 disposed in the substrate 100 between two adjacent word lines (ie gates 107a, 107b) as an example, but it is not intended to limit this embodiment. invention. In one embodiment, the doped region 108 includes a plurality of source regions 108 a and drain regions 108 b. As shown in FIG. 2A , the section along line II′ shows that the source regions 108 a and the drain regions 108 b are arranged alternately. The section along the line II-II', as shown in FIG. 2B , only the source region 108a can be seen. A section along the line III-III', as shown in FIG. 2C, only the drain region 108b can be seen.

The insulating layer 110 is disposed on the gate structures 106a, 106b. The material of the insulating layer 110 includes boronphosphosilicate glass (BPSG).

The conductive layer 112 is disposed on the insulating layer 110 . The conductive layer 112 has a plurality of conductive blocks 115 and a plurality of wires 113a and 113b extending along the second direction. In one embodiment, the wires 113 a and 113 b and the conductive block 115 are located on the same plane, as shown in FIG. 2A . However, the present invention is not limited thereto. In another implementation, the wires 113a and 113b and the conductive block 115 may also be located on different planes. For example, the wires 113a and 113b are located on a first plane, and the conductive block 115 is located on a second plane different from the first plane. The material of the conductive layer 112 includes metal, such as aluminum, copper or alloys thereof.

In one embodiment, the plurality of conductors 113a and the plurality of wires 113b are arranged alternately. In addition, at least one conductive block 115 is disposed between two adjacent wires 113a and 113b. In this embodiment, it is illustrated by taking four conductive blocks 115 disposed between two adjacent wires 113a and 113b as an example, but it is not intended to limit the present invention. As shown in FIG. 2A , the section along line II′ shows that the wire 113 a , the conductive block 115 , the wire 113 b , the conductive block 115 , the wire 113 a . . . are arranged in this order.

In addition, the wires 113 a , 113 b and the conductive block 115 are electrically connected to the doped region 108 . Specifically, the wires 113 a and 113 b are electrically connected to the source region 108 a through the conductive plug 114 , and the conductive block 115 is electrically connected to the drain region 108 b through the conductive plug 116 . The material of the conductive plugs 114, 116 includes copper or tungsten.

The insulating layer 118 is disposed on the conductive layer 112 . The material of the insulating layer 118 includes silicon oxide.

A plurality of variable resistance blocks 120 are disposed on the insulating layer 118 and respectively correspond to the conductive blocks 115 . In one embodiment, the variable resistance block 120 is disposed in the insulating layer 122 . The material of the insulating layer 122 includes silicon oxide. Each variable resistance block 120 includes a bottom electrode 117 , a top electrode 121 and a variable resistance layer 119 between the bottom electrode 117 and the top electrode 121 . The material of the bottom electrode 117 includes titanium nitride (eg TiN). The material of the variable resistance layer 119 includes transition metal oxides (such as HfO2 or ZrO2). The material of the top electrode material layer 121 includes titanium nitride (eg Ti/TiN).

In addition, the variable resistor block 120 is electrically connected to the conductive block 115 . Specifically, the variable resistance block 120 is electrically connected to the conductive block 115 through the conductive plug 123 . The material of the conductive plug 123 includes copper or tungsten.

The insulating layer 124 is disposed on the variable resistance block 120 . The material of the insulating layer 124 includes silicon oxide.

A plurality of bit lines 126 are disposed on the insulating layer 124 and extend along a first direction. The material of the bit line 126 includes metals such as copper, aluminum or alloys thereof. The bit line 126 is electrically connected to the variable resistance block 120 . Specifically, the bit line 126 is electrically connected to the variable resistance block 120 through the conductive plug 127 . The material of the conductive plug 127 includes copper or tungsten.

In this embodiment, the insulating layers 110, 118, 122, and 124 together with the insulating spacers 111a, 111b can connect the word line (ie, the gate 107a, 107b) and the conductive layer 112, the variable resistance block 120, and the bit line 126 to each other. electrically isolated.

As shown in FIG. 1 and FIG. 2A , the memory cell A of the present invention has a 2T1R (two transistors and one resistor) structure, which includes two gates 107 a, 107 b and a variable resistance block 120 . More specifically, the memory cell A of the present invention includes a gate 107a and a gate 107b (both serve as word lines), a conductive line 113a and a conductive line 113b (both serve as source lines), a conductive block 115, a The variable resistance block 120 and a bit line 126 . In addition, adjacent memory cells A share an isolation structure 102 . In addition, since adjacent memory cells A share a wire 113a (or 113b), a back-to-back structure is formed.

Hereinafter, the method of operating the resistive memory element of the present invention will be described. A specific description will be given using the above-mentioned resistive memory element of FIGS. 1 to 2C .

When in the setting (SET) mode, apply a first AC voltage (AC voltage) (for example, about 1-3V) to the first word line (for example, gate 107a), and apply a voltage of 0V to the second word line (for example, gate 107b), apply a second AC voltage (for example, about 1-2V) to the bit line 126, apply a 0V voltage to the substrate 100, apply a 0V voltage to the first wire (such as the wire 113a), and apply a DC reset voltage (DC reset voltage) (eg about 1-3V) to the second wire (eg wire 113b).

When in reset (RESET) mode, apply 0V voltage to the first word line (such as gate 107a), apply a third AC voltage (such as about 1 ~ 3V) to the second word line (such as gate 107b), apply A voltage of 0V is applied to the bit line 126, a voltage of 0V is applied to the substrate 100, a voltage of 0V is applied to the first wire (eg, wire 113a), and the same DC reset voltage (eg, about 1-3V) is applied to the second wire (eg, wire 113b ) ).

In the above embodiment, as shown in FIG. 2A , the wire 113a or 113b, the conductive plug 114 and the source region 108a form a source node (source node), and the conductive block 115, the conductive plug 116 and the source region 108b constitutes a drain node. Therefore, in the resistive memory element 10 including a plurality of memory cells A of the present invention, each memory cell A includes two gates 107a and 107b, a drain node, a variable resistance block 120, a conductor layer (such as bit line 126) and two source nodes. The drain node is located between the gates 107a and 107b. The variable resistance block 120 is electrically connected to the drain node. The conductive layer (such as the bit line 126 ) is electrically connected to the variable resistance block 120 . Two source nodes are respectively located outside the gates 107a and 107b, wherein one of the source nodes (for example, the source node including the wire 113a) is used for ground potential (0V voltage), and the other source node The other (for example, the source node including the wire 113b) is used to connect the reset voltage to reset the memory cell.

To sum up, in the resistive memory element of the present invention, the source line is divided into the ground source line (such as the wire 113a) and the reset source line (such as the wire 113b), regardless of whether it is set (SET) During operation or RESET operation, 0V voltage is applied to the ground source line (eg, wire 113a ) and a DC reset voltage is applied to the reset source line (eg, wire 113b ). More specifically, please refer to FIG. 3 , in the memory cell array area (shown as a dotted box), the ground source line (such as the wire 113a) and the reset source line (such as the wire 113b) are finger-plugged ( Inter-digital) configuration, each connected to a different DC voltage. Therefore, in the resistive memory element of the present invention, the voltages of the grounded source line and the reset source line are kept stable, and voltage switching is not required. Therefore, the programming time can be greatly reduced to improve the performance of components.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the concept and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (13)

1. a kind of resistive memory element, it is characterised in that including：

A plurality of isolation structure, is configured in substrate and extends in a first direction；

A plurality of character line, is configured on the substrate and extends in a second direction, and the doped region of wherein at least one is configured at adjacent In the substrate between two character lines, and the second direction is different from the first direction；

Conductive layer, is configured on the character line, and the conductive layer has multiple conductive areas and prolongs along the second direction The a plurality of wire stretched, at least a conductive area are configured between two adjacent wires, and the wire and the conduction region Block is electrically connected with the doped region, wherein the wire includes a plurality of first wire and a plurality of second wire that are alternately arranged, First wire is used for earthing potential, and second wire resets voltage to reset the resistance-type storage unit for connecing Part；

Multiple variable resistor blocks, are respectively arranged in the conductive area and are electrically connected with the conductive area；And

Multiple bit lines, are configured on the conductive layer, extend along the first direction and electrically connect with the variable resistor block Connect.

2. resistive memory element according to claim 1, wherein the second direction is vertical with the first direction.

3. resistive memory element according to claim 1, wherein the wire and the conductive area of the conductive layer It is generally aligned in the same plane.

4. resistive memory element according to claim 1, wherein the doped region includes plurality of source regions and multiple drain electrodes Area, the wire is electrically connected with the source area, and the conductive area is electrically connected with the drain region.

5. resistive memory element according to claim 1, wherein the wire and the conductive area are by multiple first Conductive plunger is electrically connected with the doped region.

6. resistive memory element according to claim 1, wherein the variable resistor block passes through multiple second conductive plungers It is electrically connected with the conductive area.

7. resistive memory element according to claim 1, wherein the bit line pass through multiple 3rd conductive plungers with it is described Variable resistor block is electrically connected with.

8. resistive memory element according to claim 1, wherein each variable resistor block includes hearth electrode, top electrode and position Variable resistance layer between the hearth electrode and the top electrode.

9. resistive memory element according to claim 1, also including an at least insulating barrier, the character line is led with described Electric layer, the variable resistor block and the bit line are isolated from each other.

10. resistive memory element according to claim 1, wherein the character line includes a plurality of first character being alternately arranged Line and a plurality of second character line.

A kind of 11. operating methods of resistive memory element, are used to operate resistive memory element as claimed in claim 10, Characterized in that, the operating method includes：

When in the pattern of setting, apply the first alternating voltage to first character line, apply 0V voltages to second character Line, applies the second alternating voltage to the bit line, applies 0V voltages to the substrate, applies 0V voltages to first wire, And applying direct current resets voltage to second wire.

The operating method of 12. resistive memory elements according to claim 11, wherein the operating method also includes：

When pattern is reseted, 0V voltages to first character line are applied, apply the 3rd alternating voltage to second character Line, applies 0V voltages to the bit line, applies 0V voltages to the substrate, applies 0V voltages to first wire, and apply The direct current resets voltage to second wire.

A kind of 13. resistive memory elements, including multiple memory cell, it is characterised in that each memory cell includes：

Two grids；

One drain node, between the grid；

Variable resistor block, is electrically connected to the drain node；

Conductor layer, is electrically connected to the variable resistor block；And

Two source nodes, respectively positioned at the outside of the grid, wherein one of described source node is used for earthing potential, And the other of described source node is used to connect to reset voltage to reset the memory cell.