CN104617137A - Field effect device and preparation method thereof - Google Patents

Abstract

The embodiment of the present invention discloses a field effect device and a manufacturing method thereof, which are used to solve various defects existing in existing tunneling transistors. The method in the embodiment of the present invention includes: a semiconductor substrate having a first doping type; A drain region with the first doping type formed on the surface of the semiconductor substrate; a convex body formed on the surface of the drain region; a gate formed on the surface of the drain region other than the convex body, the gate is higher than the convex body, and between The gate dielectric layer between the gate and the drain region and between the gate and the convex body; the semiconductor thin film formed on the surface of the structure composed of the gate dielectric layer and the convex body, as a pocket layer; the source region formed on the surface of the pocket layer , the source region is a semiconductor substrate with the second doping type; the convex body acts as a channel between the drain region and the source region.

Description

A kind of field effect device and its preparation method

technical field

The invention relates to the technical field of semiconductors, in particular to a field effect device and a preparation method thereof.

Background technique

With the evolution of semiconductor manufacturing technology, the size of electronic devices is gradually reduced, bringing improvements in chip speed, integration, power consumption, and cost. However, as the size of electronic devices approaches the physical limit, the power density of chips also increases. It has become a bottleneck restricting the evolution of semiconductor technology.

In order to continue to obtain the improvement of chip characteristics by new process technology, the power consumption of transistors must be reduced. The most effective way to reduce power consumption of transistors is to reduce the supply voltage, but due to the metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect) Transistor, MOSFET) is limited by the carrier thermodynamic transport mechanism, and the lower limit of its subthreshold swing is 60mV/dec. Reducing the supply voltage of the device will increase the subthreshold current of the device, resulting in an increase in the total leakage current of the device. big. Tunnel Field Effect Transistor (TFET) due to its unique quantum mechanical mechanism of band-to-band tunneling, the subthreshold swing of the device can break through the limit of 60mV/dec, while ensuring the current driving capability of the device, it can realize reduction of the device supply voltage. In addition, TFET also has the advantages of weak short channel effect and low off-state current, and is considered by the industry as a potential device architecture that can replace MOSFET.

An existing conventional N-type TFFT transistor is shown in FIG. 1 , the source region 101 is a P+ doped region, and the drain region 102 is an N+ doped region. Small leakage current; when the TFET is turned on, that is, when a certain gate voltage is applied, the electron concentration in the channel region 103 reaches a degenerate state, the channel region 103 and the source region 101 form a tunnel junction, the energy band bends, and the source The conduction band of region 101 overlaps with the valence band of channel region 103, and interband tunneling of carriers occurs, and current is generated in channel region 103. The tunneling mechanism belongs to the category of point tunneling, that is, the direction of carrier tunneling is the same as The gate electric fields are not in the same direction.

But the TFFT transistor shown in Figure 1a has the following disadvantages:

1. The conduction band of the source region overlaps with the valence band of the channel, and the resulting tunneling mechanism is a point tunneling mechanism, that is, the carrier tunneling direction is not in the same direction as the gate electric field, so the electrostatic control effect of the gate voltage is weak, and the load The efficiency of current tunneling is low;

2. The electric field in the drain region interferes with the formation of the tunneling junction, affects the threshold voltage of the device, and degrades the subthreshold swing at the same time;

3. The traditional TFET structure is a planar structure, which occupies a large substrate area and affects the integration density.

Another existing N-type TFET transistor with a wire tunneling mechanism is shown in FIG. layer 205, under the action of the gate electric field, the carriers in the epitaxial layer 205 accumulate, and finally form a tunnel junction with the source region 201. In this device structure, the carrier tunneling direction is parallel to the gate electric field.

As shown in Figure 1b, the tunneling direction of carriers in the TFET transistor is parallel to the electric field of the gate, and the gate control capability is enhanced, and the magnitude of the tunneling current can also be regulated by the overlapping area of the gate and source, which effectively improves the efficiency shown in Figure 1a. Type 1 defect of TFET transistors.

However, the substrate area consumed by the device is also increased, thereby reducing the integration density of the transistor. In addition, the planar structure adopts the source replacement technology, which will damage the epitaxial layer, resulting in a decrease in device characteristics.

Contents of the invention

Embodiments of the present invention provide a field effect device and a manufacturing method thereof, which are used to solve the above-mentioned various defects existing in existing tunneling transistors.

A first aspect of the present invention provides a field effect device, comprising:

a semiconductor substrate having a first doping type;

a drain region with the first doping type formed on the surface of the semiconductor substrate;

A protrusion formed on the surface of the drain region, the protrusion being a fin or a nanowire with a first doping type perpendicular to the surface of the drain region;

a gate formed on the surface of the drain region other than the protrusion, the gate being higher than the protrusion;

a gate dielectric layer formed between the gate and the drain region and between the gate and the protrusion;

A semiconductor thin film formed on the surface of the structure composed of the gate dielectric layer and the protrusions, as a pocket layer;

a source region formed on the surface of the pocket layer, the source region being a semiconductor substrate having a second doping type;

The protrusion serves as a channel between the drain region and the source region.

In combination with the first aspect of the present invention, in the first possible implementation manner of the first aspect of the present invention, the field effect device further includes:

electrodes formed on the source region, the drain region and the source region respectively.

In combination with the first aspect of the present invention, in the second possible implementation manner of the first aspect of the present invention, the source region and the pocket layer form a tunnel junction, and the tunnel junction controls the flow of carriers through the electric field of the gate. Tunneling can realize the on and off of the current in the device.

In combination with the first aspect of the present invention, the first possible implementation of the first aspect of the present invention, or the second possible implementation of the first aspect of the present invention, in the third possible implementation of the first aspect of the present invention:

The first doping type is n-type, and the second doping type is p-type;

Or, the first doping type is p-type, and the second doping type is n-type.

In combination with the first aspect of the present invention, the first possible implementation of the first aspect of the present invention, or the second possible implementation of the first aspect of the present invention, in the fourth possible implementation of the first aspect of the present invention:

The semiconductor substrate is bulk silicon, silicon on insulator, germanium or III-V group compound semiconductor material, the nanowires and fins are silicon, germanium, germanium silicon or III-V group compound semiconductor material, the pocket The layer is silicon, germanium, silicon germanium or III-V compound semiconductor material, the source region is silicon, germanium, germanium silicon or III-V compound semiconductor material, and the first part of the gate dielectric layer is silicon dioxide, nitrogen Silicon oxide, high dielectric material or other dielectric insulating materials, and the gate is metal, alloy or doped polysilicon.

In combination with the first possible implementation of the first aspect of the present invention, in the fifth possible implementation of the first aspect of the present invention:

The electrode is aluminum or copper or aluminum alloy or copper alloy;

The spacer is silicon dioxide, silicon nitride or silicon oxynitride.

The second aspect of the present invention provides a method for preparing a field effect device as described above, comprising:

forming an alternative source thin film layer on the surface of the semiconductor substrate having the first doping type;

A hard mask layer is deposited on the surface of the replaceable source thin film layer, and the positions of the device bumps and drain regions are defined by photolithography and etching processes, and the bumps are fins with the first doping type or Nanowires;

Using the hard mask layer as a mask, etching the replaceable source thin film layer and the semiconductor substrate by reactive ion etching technology to form the protrusions;

Using the hard mask layer as a mask, performing ion implantation of the first doping type on the semiconductor substrate, and annealing to activate the implanted ions, to form the drain region;

forming a first part of the gate dielectric layer on the surface of the formed structure;

forming a gate on the first part of the gate dielectric layer, and etching the gate and the first part of the gate dielectric layer to expose the hard mask layer;

forming a second part of the gate dielectric layer on the exposed surface of the gate, and removing the hard mask layer and the replaceable source film layer, the first part of the gate dielectric layer and the second part of the gate dielectric layer Composing the gate dielectric layer of the device;

Forming a semiconductor thin film on the surface of the formed structure as a pocket layer;

A source region is formed on the surface of the pocket layer, and the source region is a plate conductor substrate with the second doping type.

In combination with the second aspect of the present invention, the first possible implementation manner of the second aspect of the present invention further includes:

The electrode windows of the drain region, the source region and the gate are opened by photolithography and etching technology, metal is deposited on the electrode window, and electrodes are formed on the drain region, the source region and the gate respectively.

In combination with the second aspect of the present invention or the first possible implementation of the second aspect of the present invention, in the second possible implementation of the second aspect of the present invention:

The first doping type is n-type, and the second doping type is p-type;

Alternatively, the first doping type is p-type, and the second doping type is n-type.

In combination with the second aspect of the present invention or the first possible implementation of the second aspect of the present invention, in the third possible implementation of the second aspect of the present invention:

The alternative source thin film layer is polycrystalline silicon, polycrystalline germanium or other similar materials, and the hard mask layer is a material resistant to ion etching.

It can be seen from the above that the field effect device of the embodiment of the present invention forms a source region on the surface of the pocket layer by forming a pocket layer, and the pocket layer and the source region form a tunnel junction of the device, thus, it has the following technical effects:

(1) The device adopts the post-source replacement technology, that is, the source region is made at the end of the process flow, and the pocket layer and source region are made at the back of the process flow, so that various types of heterogeneous tunneling can be selected during preparation Junction, which improves the engineering flexibility of preparing the heterogeneous tunneling junction in the source region;

(2) In this device, the contact surface between the tunnel junction formed by the source region and the pocket layer and the gate dielectric layer is vertical, and the direction of carrier tunneling must be consistent with the direction of the gate electric field. This device belongs to the line tunneling mechanism , the gate voltage controls the tunneling of carriers. In the wire tunneling mechanism, the direction of carrier tunneling is consistent with the direction of the gate electric field, so the voltage control ability of the gate is strengthened, and the magnitude of the tunneling current can also be controlled by the gate The overlapping area of the electrode and the tunneling junction is adjusted to improve the tunneling efficiency. In addition, the line tunneling mechanism can reduce the subthreshold swing due to its unique quantum mechanical mechanism of interband tunneling.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that are required in the description of the embodiments and prior art. Obviously, the accompanying drawings in the following description are only some implementations of the present invention For example, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Figure 1a is a schematic diagram of an N-type traditional TFET;

Figure 1b is a schematic diagram of an N-type line tunneling TFET;

Fig. 2 is a schematic diagram of a field effect device provided by an embodiment of the present invention;

Fig. 3 is a flowchart of a method for preparing a field effect device provided by an embodiment of the present invention;

4a to 4k are schematic diagrams of various process steps in the method of the embodiment of the present invention.

Detailed ways

Embodiments of the present invention provide a field effect device and a manufacturing method thereof, so as to solve the above-mentioned various defects in existing tunneling transistors.

In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

In the following, specific examples will be used to describe in detail respectively.

Please refer to FIG. 2, an embodiment of the present invention provides a field effect device, including:

a semiconductor substrate 301 having a first doping type;

a drain region 302 formed on the surface of the semiconductor substrate 301 and having the first doping type;

forming protrusions 303 on the surface of the drain region 302, the protrusions 303 being fins or nanowires with the first doping type perpendicular to the surface of the drain region;

The gate 305 formed on the surface of the drain region other than the protrusion 303, the gate 305 is higher than the protrusion 303, and is between the gate 305 and the drain region 302 and between a gate dielectric layer 304 between the gate 305 and the protrusion 303;

The semiconductor thin film formed on the surface of the structure composed of the gate dielectric layer 304 and the protrusion 303 serves as the pocket layer 306;

A source region 307 is formed on the surface of the pocket layer 306, and the source region 307 is a semiconductor substrate with a second doping type.

In some embodiments of the present invention, the field effect device further includes:

The electrodes respectively formed on the source region 307 , the drain region 302 and the gate 305 ; specifically include: a drain region electrode 308 , a source region electrode 309 and a gate electrode 310 .

Optionally, the first doping type is n-type, and the second doping type is p-type; or, the first doping type is p-type, and the second doping type For n type.

Optionally, the semiconductor substrate 301 is bulk silicon, silicon-on-insulator, germanium, or III-V compound semiconductor materials, and the nanowires and fins are silicon, germanium, silicon germanium, or III-V compound semiconductor materials. Material, the pocket layer 306 is silicon, germanium, silicon germanium or III-V compound semiconductor material, the source region 307 is silicon, germanium, germanium silicon or III-V compound semiconductor material, the gate dielectric layer 304 It is silicon dioxide, silicon nitride, high dielectric material or other dielectric insulating material, and the gate 305 is metal, alloy or doped polysilicon.

Optionally, the electrode is aluminum or copper or aluminum alloy or copper alloy; the separator 311 is silicon dioxide, silicon nitride or silicon oxynitride.

In the field effect device of the embodiment of the present invention:

The source region 307 and the pocket layer 306 form a tunnel junction, and the tunnel junction controls the tunneling of carriers through the electric field of the gate, so as to realize the on and off of the current in the device.

The principle of the technical solution of the embodiment of the present invention is as follows:

The embodiment of the present invention adopts the post-source replacement technology. The source region 307 and the pocket layer 306 form the tunneling junction of the device. The electric field of the gate can control whether the carrier tunnels or not. Obviously, the direction of the carrier tunneling Consistent with the direction of the electric field of the gate, it belongs to the line tunneling mechanism. Taking the enhanced N-channel field effect transistor as an example, the source region 307 is p-type doped, the drain region 302 is n-type doped, and the pocket layer 306 is n-type doped , the convex body 303 (that is, silicon fin or silicon nanowire) is used as a channel, and the doping is the same as that of the semiconductor substrate 301, which is n-type doping. When the gate 305 is applied with a forward voltage and the drain region 302 is applied with a reverse bias, The surface of the convex body 303 and the gate dielectric layer 304 will enter the accumulation state, the convex body 303 and the pocket layer 306 have a large amount of carriers gathered on the surface, the source region 307 and the pocket layer 306 form a tunnel junction, therefore, electrons from the convex body 303 tunnels to the source region 307, and the source region 307 and the drain region 302 have current generation; when the drain region 302 is positively biased and the gate 305 is reversely biased, there is no tunneling carrier in the tunnel junction, and the source region 307 and the drain region No current is generated between 302.

In order to better implement the above solutions of the embodiments of the present invention, the following also provides related methods for preparing and implementing the above-mentioned field effect devices. In the figure, for the convenience of illustration, the thicknesses of layers and regions are enlarged, and the shown sizes do not represent Actual dimensions, the referenced figures are schematic illustrations of idealized embodiments of the invention, and the illustrated embodiments of the invention should not be construed as limited to the particular shapes of the regions shown in the figures, but include resulting shapes, such as manufacturing-induced Deviations, such as etched protrusions, have curved or rounded features, but in the embodiments of the present invention, they are all represented by rectangles, but this should not be considered as limiting the scope of the present invention.

Please refer to FIG. 2 and FIG. 3 and FIG. 4a to FIG. 4j. An embodiment of the present invention provides a method for manufacturing a field effect device, which may include:

401. As shown in FIG. 4a, an alternative source thin film layer 502 is formed on the surface of the semiconductor substrate 301 having the first doping type, and a hard mask layer 501 is formed on the surface of the alternative thin film layer, and the material of the alternative source thin film layer 502 is Different from the semiconductor substrate 301, which is easy to be removed, it can be made of polycrystalline silicon, polycrystalline germanium or other similar materials. The hard mask layer 501 is a material resistant to ion etching, specifically silicon nitride, etc. The first doped The heterotype can be n-doped or p-doped, and the semiconductor substrate 301 can be bulk silicon, silicon-on-insulator, germanium or III-V compound semiconductor materials.

402. As shown in FIG. 4b, use a photolithography process to define a hard mask, and use the hard mask as a mask to perform an etching process (such as reactive ion etching) on the replaceable source thin film layer 502 and the semiconductor substrate 301. Etching, forming the bumps 303 on the semiconductor substrate 301, and the etched thickness of the substrate may be 10 nanometers to hundreds of nanometers.

403. As shown in FIG. 4c, perform self-aligned first type ion implantation on the semiconductor substrate 301 on the generated structure, and anneal to activate the implanted ions to form the drain region 302 of the device.

404. As shown in FIG. 4d, on the generated structure, deposit silicon dioxide, silicon nitride, high dielectric material or other dielectric insulating materials to form a layer of insulating film as the first part 3041 of the gate dielectric layer. Metal, alloy or doped polysilicon is deposited on the surface of the first part of the dielectric layer 3041 to form a conductive film, which is used as the gate 305, and the structure formed above is planarized. After planarization, the gate 305 and the first part of the gate dielectric layer are etched by an etching-back process 3041 until the hard mask layer 501 is exposed, the thickness of the first part 3041 of the gate dielectric layer is less than 10 nanometers; the gate 305 is made of metal, alloy or doped polysilicon.

405. As shown in FIG. 4e, deposit silicon dioxide, silicon nitride, high dielectric material or other dielectric insulating materials on the exposed surface of the gate 305 to form a layer of insulating film as the second part 3042 of the gate dielectric layer. The first part 3041 of the dielectric layer and the second part 3042 of the gate dielectric layer are made of the same material, and are connected to each other to form the gate dielectric layer 304 .

406 , as shown in FIG. 4f , remove the replaceable source film layer 502 and the hard mask layer 501 by using an etching technique.

407. As shown in FIG. 4g, deposit silicon, germanium, silicon germanium, or III-V compound semiconductor materials on the generated structure to form a semiconductor thin film as the pocket layer 306, and the thickness of the pocket layer 306 is between 1 nanometer and 10 nanometers. between nanometers.

408. As shown in FIG. 4h, generate a source region 307 on the surface of the pocket layer 306. The source region 307 is a semiconductor substrate with the second doping type. The source region 307 is an inverted convex shape, and its size is not limited.

409. As shown in FIG. 4i , before step 410, it also includes: forming a rectangular region above the drain region 302 and outside the region on the left side of the gate 305 by etching technology, and forming a rectangular region on the right side of the source region 307 above the region on the right side of the gate 305 Rectangular region, the upper surface of the rectangular region is flush with the upper surface of the source region, and an electrically insulating material is deposited in the rectangular region to form a spacer 311, so that the drain region electrode 308 and the gate electrode 310 formed in step 410 are separated from the source region 307 .

410. As shown in FIG. 4j, open the electrode window of the drain region 302 and the gate 305 by photolithography and etching technology, and after depositing metal on the electrode window and the source region 307, form a device by lift-off technology source electrode 309 , drain electrode 308 and gate electrode 310 .

It should be noted that, in the structure shown in FIG. Compared with the above structure, the pocket layer 306 is smaller in size, but does not affect performance. In this structure, the upper surface of the source region 307 does not exceed the upper surface of the gate 305, so the second part 3042 of the gate dielectric layer may not be formed. Step 405 It does not need to be executed, and the specific situation may depend on the actual situation in the technological process.

It should be noted that the first doping type is n-type, and the second doping type is p-type; or, the first doping type is p-type, and the second doping type is n-type .

Optionally, the semiconductor substrate 301 is bulk silicon, silicon-on-insulator, germanium, or III-V compound semiconductor materials, and the nanowires and fins are silicon, germanium, silicon germanium, or III-V compound semiconductor materials. Material, the pocket layer 306 is silicon, germanium, silicon germanium or III-V compound semiconductor material, the source region 307 is silicon, germanium, germanium silicon or III-V compound semiconductor material, the gate dielectric layer 304 It is silicon dioxide, silicon nitride, high dielectric material or other dielectric insulating material, and the gate 305 is metal, alloy or doped polysilicon.

Optionally, the electrode is aluminum or copper or aluminum alloy or copper alloy; the separator 311 is silicon dioxide, silicon nitride or silicon oxynitride.

To sum up, the field effect device according to the embodiment of the present invention forms a source region on the surface of the pocket layer by forming a pocket layer, and the pocket layer and the source region form a tunnel junction of the device, thus having the following technical effects:

(1) The device adopts the post-source replacement technology, that is, the source region is made at the end of the process flow, and the pocket layer and source region are made at the back of the process flow, so that various types of heterogeneous tunneling can be selected during preparation Junction, which improves the engineering flexibility of preparing the heterogeneous tunneling junction in the source region;

(2) In this device, the contact surface between the tunnel junction formed by the source region and the pocket layer and the gate dielectric layer is vertical, and the direction of carrier tunneling must be consistent with the direction of the gate electric field. This device belongs to the line tunneling mechanism , the gate voltage controls the tunneling of carriers. In the wire tunneling mechanism, the direction of carrier tunneling is consistent with the direction of the gate electric field, so the voltage control ability of the gate is strengthened, and the magnitude of the tunneling current can also be controlled by the gate The overlapping area of the electrode and the tunneling junction is adjusted to improve the tunneling efficiency. In addition, the line tunneling mechanism can reduce the subthreshold swing due to its unique quantum mechanical mechanism of interband tunneling.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because Certain steps may be performed in other orders or simultaneously in accordance with the present invention. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions recorded in each embodiment are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. A field effect device, characterized in that, comprising: a semiconductor substrate having a first doping type; a drain region with the first doping type formed on the surface of the semiconductor substrate; A protrusion formed on the surface of the drain region, the protrusion being a fin or a nanowire with a first doping type perpendicular to the surface of the drain region; a gate formed on the surface of the drain region other than the protrusion, the gate being higher than the protrusion; a gate dielectric layer formed between the gate and the drain region and between the gate and the bump; A semiconductor thin film formed on the surface of the structure composed of the gate dielectric layer and the protrusions, as a pocket layer; a source region formed on the surface of the pocket layer, the source region being a semiconductor substrate of the second doping type; The protrusion serves as a channel between the drain region and the source region. 2. The field effect device according to claim 1, further comprising: electrodes respectively formed on the source region, the drain region and the gate. 3. The field effect device according to claim 1, wherein the source region and the pocket layer form a tunnel junction, and the tunnel junction controls the tunneling of carriers through the electric field of the gate, which can realize The on and off of the current in the device. 4. The field effect device according to any one of claims 1 to 3, characterized in that: The first doping type is n-type, and the second doping type is p-type; Or, the first doping type is p-type, and the second doping type is n-type. 5. The field effect device according to any one of claims 1 to 3, characterized in that: The semiconductor substrate is bulk silicon, silicon on insulator, germanium or III-V group compound semiconductor material, the nanowires and fins are silicon, germanium, germanium silicon or III-V group compound semiconductor material, the pocket The layer is silicon, germanium, silicon germanium or III-V compound semiconductor material, the source region is silicon, germanium, germanium silicon or III-V compound semiconductor material, and the gate dielectric layer is silicon dioxide, silicon nitride , high dielectric material or other dielectric insulating materials, the gate is metal, alloy or doped polysilicon. 6. The field effect device according to claim 2, characterized in that: The electrode is aluminum or copper or aluminum alloy or copper alloy; The spacer is silicon dioxide, silicon nitride or silicon oxynitride. 7. A preparation method of a field effect device as claimed in claim 1, characterized in that, comprising: forming an alternative source film layer on the surface of the semiconductor substrate having the first doping type; A hard mask layer is deposited on the surface of the replaceable source thin film layer, and the positions of the device bumps and drain regions are defined by photolithography and etching processes, and the bumps are fins with the first doping type or Nanowires; Using the hard mask layer as a mask, etching the replaceable source thin film layer and the semiconductor substrate by reactive ion etching technology to form the protrusions; Using the hard mask layer as a mask, performing ion implantation of the first doping type on the semiconductor substrate, and annealing to activate the implanted ions to form the drain region; forming a first part of the gate dielectric layer on the surface of the formed structure; forming a gate on the first part of the gate dielectric layer, and etching the gate and the first part of the gate dielectric layer to expose the hard mask layer; forming a second part of the gate dielectric layer on the exposed surface of the gate, and removing the hard mask layer and the replaceable source film layer, the first part of the gate dielectric layer and the second part of the gate dielectric layer Composing the gate dielectric layer of the device; Forming a semiconductor thin film on the surface of the formed structure as a pocket layer; A source region is formed on the surface of the pocket layer, and the source region is a semiconductor substrate with a second doping type. 8. The method according to claim 7, further comprising: The electrode windows of the drain region, the source region and the gate are opened by photolithography and etching technology, metal is deposited on the electrode window, and electrodes are formed on the drain region, the source region and the gate respectively. 9. According to the field effect device described in claim 7 or 8, it is characterized in that: The first doping type is n-type, and the second doping type is p-type; Alternatively, the first doping type is p-type, and the second doping type is n-type. 10. The field effect device according to claim 7 or 8, characterized in that: The alternative source thin film layer is polycrystalline silicon, polycrystalline germanium or other similar materials, and the hard mask layer is a material resistant to ion etching.