CN104570630A

CN104570630A - Photoetching and overlaying mark and forming method thereof

Info

Publication number: CN104570630A
Application number: CN201310517465.XA
Authority: CN
Inventors: 孟鸿林; 王雷
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-10-28
Filing date: 2013-10-28
Publication date: 2015-04-29
Anticipated expiration: 2033-10-28
Also published as: CN104570630B

Abstract

The invention discloses a forming method of a photoetching and overlaying mark. The forming method comprises the following steps: (1) forming a thin oxidized layer on a first layer of wafer; (2) etching a groove-shaped overlaying mark on the first layer of wafer; (3) forming an integrated circuit pattern on the first layer of wafer and removing the oxidized layer; (4) forming an etching stopping layer on the first layer of wafer; (5) bonding the first layer of wafer with a second layer of wafer; (6) aligning the second layer of wafer with the overlaying mark of the first layer of wafer, exposing and developing to form an integrated circuit pattern and an overlaying pattern; and (7) etching a groove-shaped overlaying mark and a needed integrated circuit pattern on the second layer of wafer; and exposing the overlaying mark of the first layer of wafer. The invention further discloses the photoetching and overlaying mark formed by the method; the section of the photoetching and overlaying mark is groove-shaped; and the etching stopping layer is formed on the surface of the overlaying mark on the lower layer of wafer. The groove-shaped overlaying marks are etched on the upper and lower layers of wafers so that the measurement of photoetching and overlaying precision after the wafers are bonded is simplified and the manufacturing cost is reduced.

Description

Photoetching alignment mark and forming method thereof

Technical field

The present invention relates to IC manufacturing field, particularly relating to photoetching alignment mark for detecting alignment precision between wafer and wafer and forming method thereof.

Background technology

In integrated semiconductor processes, usually all need through photo-mask process repeatedly.Except ground floor photoetching, the quality of aiming at front layer when generally each layer photoetching all needs measuring unit marking to carry out monitoring photoetching.And overlay mark normally inside casing be the photoetching offset plate figure of 10 × 10 μm, housing is the square frame that other film quality of 20 × 20 μm are formed, no matter and inside casing or housing all need a step difference, be all to be detected by optical lens simultaneously simultaneously.

In micro electronmechanical (MEMS) technique, be first do some structure graphs on ground floor silicon chip, then by second layer silicon chip and ground floor wafer bonding, then on second layer silicon chip, do structure graph again.But we need the figure that the figure that does on second layer silicon chip and ground floor silicon chip do to have good aligned relationship, also detect this alignment precision simultaneously.In production technology due to current integrated circuit, alignment precision is measured by optical tooling, and in microelectromechanical processes, ground floor silicon chip and second layer silicon chip are opaque, so alignment precision just cannot be detected by existing means.

Summary of the invention

One of the technical problem to be solved in the present invention is to provide a kind of formation method of photoetching alignment mark, and it can simplify the measurement of alignment precision between wafer, and can save cost.

For solving the problems of the technologies described above, the formation method of photoetching alignment mark of the present invention, comprises step:

The formation method of photoetching alignment mark, it is characterized in that, step comprises:

1) on ground floor wafer, thin oxide layer is formed;

2) on ground floor wafer, groove type photoetching alignment mark is etched;

3) on ground floor wafer, carry out normal gluing, photoetching, development, etch process step, the integrated circuit pattern needed for formation, then removes thin oxide layer;

4) on ground floor wafer, etch stop is formed;

5) by ground floor wafer and second layer bonding chip;

6) by the photoetching alignment mark on second layer wafer aligned ground floor wafer, second layer wafer is coated with photoresist, exposure imaging, the integrated circuit pattern needed for formation and photoetching alignment mark figure;

7) on second layer wafer, etch groove type photoetching alignment mark and required integrated circuit pattern, and the photoetching alignment mark on ground floor wafer is exposed.

Two of the technical problem to be solved in the present invention is to provide the photoetching alignment mark formed with said method.

For solving the problems of the technologies described above, the cross section of photoetching alignment mark of the present invention is groove type, and there is one deck etch stop on the surface of the photoetching alignment mark in lower chip.

Preferably, the sectional dimension of the photoetching alignment mark in lower chip is less than the sectional dimension of the photoetching alignment mark in upper chip.

The present invention is by the photoetching alignment mark of etched recesses shape on upper and lower two-layer wafer, the measurement of photoetching alignment precision after simplifying wafer bonding, meanwhile, owing to not needing extra purchase of equipment, the instrument and supplies in existing manufacture of semiconductor can be utilized, therefore can also reduce processing procedure cost.

Accompanying drawing explanation

Fig. 1-7 is formation method flow schematic diagram of the photoetching alignment mark of the embodiment of the present invention.Wherein, Fig. 7 shows the side view of the pattern of the photoetching alignment mark that the present embodiment makes.

Fig. 8 is the vertical view of the pattern of the photoetching alignment mark that the embodiment of the present invention makes.

Embodiment

Understand more specifically for having technology contents of the present invention, feature and effect, now in conjunction with illustrated embodiment, details are as follows:

The photoetching alignment mark of the present embodiment, its concrete fabrication processing is as follows:

Step 1, ground floor wafer (diameter 200 millimeters, thickness 725 microns) forms with physical gas-phase deposite method the thin oxide layer that a layer thickness is 125 Ethylmercurichlorendimides, as shown in Figure 1.

Step 2, on ground floor wafer, etching forms the photoetching alignment mark of groove type, as shown in Figure 2.The sectional dimension of groove is 10 μm × 10 μm, and the degree of depth of groove is 70 μm.

Step 3, ground floor wafer carries out the processing steps such as normal gluing, photoetching, development, etching, and the integrated circuit pattern needed for formation, then removes thin oxide layer, as shown in Figure 3.This step photoetching board used is TEL, Nikon etc.

Step 4, on ground floor wafer with physical gas-phase deposite method formed a layer thickness be the thick thermal oxide layer of 5000 Ethylmercurichlorendimides as etch stop, as shown in Figure 4.

Step 5, adopts the method for Si-Si bonding, by ground floor wafer and second layer wafer (diameter 200 millimeters, thickness 30 microns) Direct Bonding together, as shown in Figure 5.

The concrete grammar of Si-Si bonding is: ground floor wafer and second layer wafer are placed in oxygen or nitrogen environment, with 800 celsius temperature process more than 6 hours, makes ground floor wafer and second layer bonding chip.

Step 6, by the photoetching alignment mark on second layer wafer aligned ground floor wafer, second layer wafer is coated with photoresist, exposure imaging, the integrated circuit pattern needed for formation and photoetching alignment mark figure, as shown in Figure 6.

Step 7, second layer wafer etches groove type photoetching alignment mark and required integrated circuit pattern, makes the photoetching alignment mark on ground floor wafer expose, as shown in Figure 7 simultaneously.The channel section of the photoetching alignment mark on second layer wafer is of a size of 20 μm × 20 μm ~ 30 μm × 30 μm, and the degree of depth of groove is 70 μm.

Claims

1. the formation method of photoetching alignment mark, it is characterized in that, step comprises:

1) on ground floor wafer, thin oxide layer is formed;

2) on ground floor wafer, groove type photoetching alignment mark is etched;

4) on ground floor wafer, etch stop is formed;

5) by ground floor wafer and second layer bonding chip;

2. method according to claim 1, is characterized in that, the channel section size of the photoetching alignment mark on second layer wafer is greater than the channel section size of the photoetching alignment mark on ground floor wafer.

3. method according to claim 2, is characterized in that, step 2) sectional dimension of described groove is 10 μm × 10 μm; The sectional dimension of groove described in step 7) is 20 μm × 20 μm ~ 30 μm × 30 μm.

4. method according to claim 1, is characterized in that, step 1), and the thickness of described thin oxide layer is 125 Ethylmercurichlorendimides.

5. method according to claim 1, is characterized in that, step 4), and the thickness of described etch stop is 5000 Ethylmercurichlorendimides.

6. the method according to claim 1 or 6, is characterized in that, described etch stop is thermal oxide layer.

7., with the photoetching alignment mark that claim 1-6 method described in any one is formed, it is characterized in that, the cross section of photoetching alignment mark is groove type, and there is one deck etch stop on the surface of the photoetching alignment mark in lower chip.

8. photoetching alignment mark according to claim 7, is characterized in that, the sectional dimension of the photoetching alignment mark in lower chip is less than the sectional dimension of the photoetching alignment mark in upper chip.

9. photoetching alignment mark according to claim 8, is characterized in that, the sectional dimension of the photoetching alignment mark in lower chip is 10 μm × 10 μm; The sectional dimension of the photoetching alignment mark in upper chip is 20 μm × 20 μm ~ 30 μm × 30 μm.

10. photoetching alignment mark according to claim 7, is characterized in that, described etch stop is thermal oxide layer.