CN104536755A - Reconstruction method and device for programmable logic device - Google Patents

Abstract

The present invention provides a programmable logic device reconfiguration method and device, the method comprising: determining the resource area to be reconfigured of the programmable logic device; dividing the resource area to be reconfigured into at least one basic unit, the basic unit includes at least one programmable Reconstruct the device; reconfigure each basic unit separately. Through the implementation of the present invention, the resource area to be reconfigured in the programmable logic device is determined according to the needs, and it is divided into basic units, and each basic unit is reconfigured respectively, and the reconfiguration with the basic unit as the smallest reconfiguration unit is realized Compared with the existing reconfiguration technology that uses basic devices as the minimum reconfiguration unit, the minimum reconfiguration range increases, and the number of control signals and data streams required for reconfiguration will be reduced, reducing the cost of programmable logic devices. Device complexity and reconfiguration costs.

Description

Programmable Logic Device Reconfiguration Method and Device

technical field

The invention relates to the application field of programmable logic devices, in particular to a programmable logic device reconfiguration method and device.

Background technique

For programmable logic devices such as FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), you only need to use development tools to convert the designed circuit into a bit stream file and import it to get the desired circuit function. Compared with the tape-out cost, it is more flexible and can be reprogrammed to achieve different logic functions.

Programmable logic devices are convenient for users to use, but they also have some disadvantages. For example, when using zynq7000 series SoC FPGA for circuit design, the existing FPGA reconfigurable technology adopts the configuration frame method, and the basic logic units (look-up table, Flip-flops, CLB, IOB and other basic devices) to achieve fine-grained reconstruction, this method needs to generate bit stream files of all circuits according to the reconfigured target circuit, and send the bit stream data required for reconstruction to these basic devices, these The basic device has been updated and reconfigured. This type of FPGA chip structure design is difficult to implement, the chip area is large, and the chip cost is high.

Therefore, how to provide a low-cost programmable logic device reconfiguration technology is a technical problem to be solved urgently by those skilled in the art.

Contents of the invention

The invention provides a programmable logic device reconfiguration method and device to reduce the reconfiguration cost of the programmable logic device.

The present invention provides a method for reconfiguring a programmable logic device. In one embodiment, the method includes: determining a resource area to be reconfigured in a programmable logic device; dividing the resource area to be reconfigured into at least one basic unit, basically The unit includes at least one reconfigurable device; each basic unit is reconfigured separately.

Further, the basic unit in the above embodiment also includes a reconfigurable line connection between the reconfigurable device and other devices.

Further, the reconfigurable device in the above embodiments includes a configurable logic module CLB.

Further, dividing the resource area to be reconfigured into at least one basic unit in the above embodiment includes: dividing the resource area to be reconfigured into at least one basic unit according to physical areas; or dividing the resource area to be reconfigured into at least one basic unit according to physical areas and The target function is divided into at least one basic unit.

Further, the target function in the above embodiment includes: the function that needs to be realized by the basic unit, or the function that needs to be realized by the resource area to be reconfigured.

Further, the reconstruction of each basic unit in the above embodiment includes: respectively generating a new bit stream file of each basic unit according to the target function; and configuring the new bit stream file of each basic unit to the corresponding basic unit.

The present invention provides a device for reconfiguring a programmable logic device. In one embodiment, the device includes: a determining module, used to determine a resource area to be reconfigured in a programmable logic device; The resource area is divided into at least one basic unit, and the basic unit includes at least one reconfigurable device; the reconfiguration module is used to reconfigure each basic unit respectively.

Further, the basic unit in the above embodiment also includes a reconfigurable line connection between the reconfigurable device and other devices.

Further, the reconfigurable device in the above embodiments includes a configurable logic module CLB.

Further, the division module in the above embodiment is specifically used to: divide the resource area to be reconfigured into at least one basic unit according to the physical area; or divide the resource area to be reconfigured into at least one basic unit according to the physical area and target function .

Further, the target function in the above embodiment includes: the function that needs to be realized by the basic unit, or the function that needs to be realized by the resource area to be reconfigured.

Further, the reconstruction module in the above embodiment is specifically configured to generate a new bit stream file of each basic unit according to the target function; configure the new bit stream file of each basic unit to the corresponding basic unit.

Beneficial effects of the present invention:

According to the solution provided by the present invention, the resource area to be reconfigured in the programmable logic device is determined according to the needs, and it is divided into basic units, and the basic unit includes at least one reconfigurable device. After writing the bit stream data, these reconfigurable devices The basic logic functions can be realized, that is, each basic unit can realize some functions of the target circuit. On this basis, each basic unit is reconstructed separately, and the reconstruction technology with the basic unit as the smallest reconstruction unit is realized. , compared with the existing reconfiguration technology with the basic device as the minimum reconfiguration unit, the minimum reconfiguration range increases, the number of control signals and data streams required for reconfiguration will be reduced, and the device cost of the programmable logic device is reduced. Complexity and refactoring costs.

Description of drawings

FIG. 1 is a flow chart of the programmable logic device reconfiguration method provided by the first embodiment of the present invention;

FIG. 2 is a schematic diagram of a programmable logic device reconfiguration device provided by a second embodiment of the present invention;

FIG. 3 is a flowchart of a programmable logic device reconfiguration method provided by a third embodiment of the present invention;

Fig. 4 is the schematic diagram of the division steps of the FPGA device in the third embodiment of the present invention;

FIG. 5 is a schematic diagram of reconfiguration of the resource area to be reconfigured in the third embodiment of the present invention;

Fig. 6 is a schematic diagram of realization of a single basic unit in the third embodiment of the present invention.

Detailed ways

The present invention will be further explained by means of specific embodiments in combination with the accompanying drawings.

First embodiment:

Fig. 1 is a flow chart of the programmable logic device reconfiguration method provided by the first embodiment of the present invention. It can be seen from Fig. 1 that in this embodiment, the programmable logic device reconfiguration method provided by the present invention includes the following steps:

S101: Determine the resource area to be reconfigured of the programmable logic device;

This step first needs to determine the reconfigurable resource area that supports dynamic reconfiguration in the programmable logic device. There are many types of programmable logic devices. The present invention uses FPGA as an example to illustrate: the user selects some Model FPGA, the FPGA is divided into a reconfigurable resource area and a non-reconfigurable resource area. The reconfigurable resource area means that the resources in this area are dynamically reconfigurable and can be written by time division multiplexing during circuit operation. Different bit stream data can realize different functions in a short time, and the non-reconfigurable resource area means that the resources in this area do not support dynamic writing of bit stream data to achieve different functions during circuit operation.

After the user selects the FPGA according to the needs, the range of the reconfigurable resource area on the device can be known according to the device specification, and then the user can according to the function of the reconfigurable sub-circuit and the reconfigurable resources in the target circuit to be changed One or more resource areas to be reconfigured are determined on the device. The resource area to be reconfigured can be a part of the reconfigurable resource area (completely belonging to the reconfigurable resource area), or it can include part of the reconfigurable resource area. Resource area and part of the non-reconfigurable resource area (used to realize circuit functions that do not need to be reconfigured in the target circuit).

S102: Divide the resource area to be reconfigured into at least one basic unit, where the basic unit includes at least one reconfigurable device;

After the resource area to be reconfigured is determined, the resources in the resource area to be reconfigured (including CLBs, editable interconnects, etc.) are divided into at least one basic unit, and each basic unit includes at least one reconfigurable device (such as CLB), so that some basic functions can be implemented after writing the bitstream file.

The number of reconfigurable devices between different basic units can be different, and can be divided according to the target functions that the basic units need to achieve. If the target functions that some basic units need to achieve are simple, then only one reconfigurable device can be included. Devices, correspondingly, if the target functions to be realized by some basic units are relatively complex, a larger number of reconfigurable devices may be included.

In some embodiments, in order to facilitate the user to allocate corresponding basic units for each sub-function in the target function that the target circuit needs to realize, it can be set that each basic unit includes the same number of reconfigurable devices (these reconfigurable devices mutual cooperation can realize some small functions of the target circuit), which ensures that each basic unit can realize certain functions after writing the bit stream data, and the reconfigurable resources of each basic unit are the same, On this basis, the target circuit can be decomposed into many small functions, and the corresponding basic units can be assigned to these small functions, without first judging the complexity of the implementation of such small functions, and the division of basic units is simple.

S103: Reconfigure each basic unit separately, which can be realized by constraining the bit stream file of the target circuit to the basic unit through a development tool.

In some embodiments, the basic unit in the above embodiments further includes reconfigurable circuit connections between the reconfigurable device and other devices. In practical applications, reconfigurable devices need to communicate with other devices during work, such as completing the acquisition of bit stream files, and the working logic relationship between reconfigurable devices. This embodiment uses the reconfigurable device The reconfigurable circuit connection with other devices is also divided into the basic unit, making the function of the basic unit more complete. The reconfigurable circuit connection includes editable interconnection lines, IOB resources, etc.

In some embodiments, taking the FPGA device as an example, the reconfigurable device in the above embodiments is a configurable logic module CLB. Of course, in some special application fields, the types of reconfigurable resources in the FPGA device used are different. Correspondingly, a reconfigurable device is a reconfigurable resource in this type of FPGA device.

In some embodiments, dividing the resource area to be reconfigured into at least one basic unit in the above embodiment includes: dividing the resource area to be reconfigured into at least one basic unit according to physical areas; or dividing the resource area to be reconfigured into at least one basic unit according to The physical area and the target function are divided into at least one basic unit. This embodiment provides the division method of the basic unit, which is divided according to the physical area, or according to the physical area and the target function, so that all the devices in the basic unit are continuous in physical position, thus reducing the distance between the devices in the basic unit. The complexity of the communication between them, thereby reducing the length and complexity of the bit stream data in the bit stream file generated according to the target function of the basic unit, and reducing the cost of realizing reconfigurability.

In some embodiments, the two basic units in the above embodiments are adjacent and non-overlapping; of course, they can also be separated by a certain area, so that some features can be realized by setting bit stream files in the interval area. Fixed sub-circuits for functions such as control and storage.

In some embodiments, when a basic unit in the above embodiment includes multiple (two or more) reconfigurable devices, the types of these reconfigurable devices are related in the target functions to be realized, such as basic When the unit needs to implement functions such as resistance and capacitance, its internal devices can include reconfigurable resistance and capacitance.

In some embodiments, the target functions in the above embodiments include: functions that need to be realized by the basic unit, or functions that need to be realized by the resource area to be reconfigured. The function that the basic unit needs to realize refers to the function corresponding to the bit stream file written by the basic unit in the target circuit. For example, when realizing the resistance function of a specific resistance value, the basic unit includes a reconfigurable device and corresponding communication lines That's it. The functions to be implemented in the resource area to be reconfigured refer to the functions that the target circuit needs to implement in the resource area to be reconfigured. These functions can be composed of multiple sub-functions. The basic units are divided according to these sub-functions, so that each basic unit can be Realize the corresponding sub-functions, the basic units obtained in this way are functionally independent and easy to refactor.

In some embodiments, the reconstruction of each basic unit in the above embodiment includes: respectively generating a new bit stream file of each basic unit according to the target function; configuring the new bit stream file of each basic unit to the corresponding basic unit. The new bit stream file refers to the bit stream data and other information required by the basic unit to realize the target function. Configuring the new bit stream file of each basic unit to the corresponding basic unit refers to importing the new bit stream file into the corresponding The basic unit of the basic unit, and replace the bit stream file in the basic unit with a new bit stream file to complete the reconstruction to achieve the target function.

In some embodiments, the above embodiment further includes a step of determining the target function according to the reconfigured sub-circuit in the target circuit before generating a new bit stream file of each basic unit according to the target function. In this embodiment, by determining the target function according to the reconfigured sub-circuit and cooperating with the bit stream file of the basic unit generated according to the target function, the purpose of constraining the reconfigured sub-circuit to the basic unit is realized, that is, the reconfigured sub-module is determined by the The basic unit in the resource area is reconstructed to realize the reconstruction.

In some embodiments, step S103 in the embodiment shown in FIG. 1 includes: determining the reconfiguration sub-circuit in the target circuit that needs to be reconfigured, and selecting one or more basic units according to the function that the reconfiguration sub-circuit needs to realize; The functions that the sub-circuit needs to realize generate the bit stream data of the bit stream file, generate the address of the bit stream file according to the address of the basic unit selected for the reconstructed sub-circuit, and generate the timing of the bit stream file according to the reconstruction order of the reconstructed sub-circuit Determine the basic unit of ownership according to the address of the bit stream file, store the bit stream file in the storage unit corresponding to the basic unit of ownership, and the control unit sequentially writes the bit stream data of the bit stream file into the bit stream file according to the timing of the bit stream file according to the control signal belonging to the basic unit. This embodiment provides a specific implementation scheme of dynamic reconfiguration, and the reconstruction is completed completely according to the content in the bit stream file. It is not necessary to compare the front and rear bit stream files as in the prior art, and the corresponding basic data of the bit stream data can be determined. The addresses of the units and the order in which they are written correspond to the basic units.

The target circuit involved in the present invention refers to the circuit used when the user needs to realize certain functions. When the circuit is in use, some sub-circuits therein need to be fault-tolerant (such as some demodulators may have errors, and the experimental effect is dynamic according to the needs. correction adjustment, etc.), replacement (realization of different specifications) and other specific functions, for such sub-circuits, the present invention defines it as a reconfiguration sub-circuit, while others do not need to be fault-tolerant (such as the implementation circuit of a radio frequency antenna generally does not make mistakes), Subcircuits that are replaced (and the antenna does not need to be replaced) are defined in the present invention as fixed subcircuits.

In this embodiment, the target circuit is divided into reconfigurable sub-circuits that need to be reconfigured and fixed sub-circuits that do not need to be reconfigured. It is realized by resources in the structural resource area, which further reduces the occupation of the limited basic units in the FPGA. In this embodiment, only the functions that need to be implemented by the reconfigured sub-circuit are resolved into the bit stream data of the bit stream file of the basic unit, and the functions of the fixed sub-circuit are not resolved into the bit stream file of the basic unit, so that only the reconfigurable sub-circuit can be realized. Compared with the current analysis process that needs to analyze all the reconstructed target circuits into bit stream files, the analysis speed is fast and the implementation is simple. After the bit stream files are generated, the basic unit.

In some embodiments, after dividing the resource area to be reconfigured into basic units, the embodiment shown in FIG. 1 further includes: setting a control unit and a storage unit for one basic unit, or setting a control unit and a storage unit for multiple basic units unit, or a step of setting a control unit and a storage unit for reconfigurable resource area division. A basic unit needs to be reconfigured, and it needs to have a storage unit for storing bitstream files and a control unit for controlling the reconstruction time. This embodiment provides three ways to set up the control unit and storage unit, and the user can configure the configuration according to actual needs. Choice, such as when the number of reconfigurable devices in the basic unit is large, a single basic unit can realize relatively complex circuit functions. At this time, control units and storage units can be set for each basic unit. When the number of reconfigurable devices in a unit is small, a control unit and a storage unit can be set up for multiple basic units (realize the storage and control of multiple basic units by time-division multiplexing). Of course, when the reconfigurable resource area When the total number of divided basic units is small or small, only one control unit and storage unit can be provided (realize the storage and control of all basic units by means of time division multiplexing).

Second embodiment:

FIG. 2 is a schematic diagram of a programmable logic device reconfiguration device provided in the second embodiment of the present invention. It can be seen from FIG. 2 that in this embodiment, the programmable logic device reconfiguration device 2 provided by the present invention includes: a determination module 21, Division module 22 and reconstruction module 23, wherein,

A determining module 21, configured to determine the resource area to be reconfigured of the programmable logic device;

A dividing module 22, configured to divide the resource area to be reconfigured into at least one basic unit, where the basic unit includes at least one reconfigurable device;

The reconstruction module 23 is used to reconstruct each basic unit respectively.

In some embodiments, the basic unit in the above embodiments further includes reconfigurable circuit connections between the reconfigurable device and other devices.

In some embodiments, the reconfigurable device in the above embodiments is a configurable logic block CLB.

In some embodiments, the division module 21 in the above embodiments is specifically configured to: divide the resource area to be reconfigured into at least one basic unit according to the physical area; or divide the resource area to be reconfigured into at least one basic unit according to the physical area and the target function At least one base unit.

In some embodiments, the target functions in the above embodiments include: functions that need to be realized by the basic unit, or functions that need to be realized by the resource area to be reconfigured.

In some embodiments, the reconstruction module 23 in the above embodiments is specifically configured to respectively generate new bit stream files of each basic unit according to target functions; configure the new bit stream files of each basic unit to corresponding basic units.

In some embodiments, the reconfiguration module 23 in the above embodiments is further configured to determine the target function according to the reconfigured sub-circuits in the target circuit.

In practical applications, the programmable logic device reconfiguration device 2 provided by the present invention can realize its functions through development tools, and can be realized by resources on the programmable logic device.

Now in conjunction with actual application, the present invention is explained.

Third embodiment:

In this embodiment, the application scenario where the reconfiguration mechanism needs to be used to achieve dynamic fault-tolerant effects in the aviation field is taken as an example, the programmable logic device is FPGA, and the reconfigurable device is CLB as an example; for the sake of illustration, only one reconfiguration is used As an example, record the circuits to be realized as target circuit 1 (the circuit before reconstruction) and target circuit 2 (the circuit after reconstruction), as shown in Table 1 below:

target circuit circuit composition target circuit 1 Subcircuit a, subcircuit b, subcircuit c, subcircuit d, subcircuit e target circuit 2 Subcircuit a, subcircuit b, 2 subcircuits c, 2 subcircuits d

Table 1

It can be seen from Table 1 that the target circuit 1 and the target circuit 2 have the same sub-circuit a and sub-circuit b (the sub-circuits a and b do not need to be reconfigured, they are fixed sub-circuits); the remaining sub-circuits of the target circuit 1 and the target circuit 2 The circuit is not the same (it needs to be reconfigured, that is, the reconfigured sub-circuit).

Fig. 3 is a flow chart of the programmable logic device reconfiguration method provided by the third embodiment of the present invention. It can be seen from Fig. 3 that in this embodiment, the programmable logic device reconfiguration method provided by the present invention includes the following steps:

S301: Select FPGA devices according to needs, and divide basic units;

The user selects the appropriate FPGA device according to the functional complexity and other requirements of the target circuit to be realized; Figure 4 does not show the editable interconnection lines, DSP and other devices in the FPGA device, as shown in Figure 4 (A), the hollow circle Represents resources that do not support dynamic reconfiguration on the FPGA device (can be used to implement subcircuits that do not need to be reconfigured in the target circuit), and solid circles represent resources that support dynamic reconfiguration on the FPGA device (can be used to implement subcircuits that do not need to be reconfigured in the target circuit). Sub-circuits that need to be reconfigured, such as programmable logic blocks CLB, etc.).

Divide the FPGA device into a reconfigurable resource area and a non-reconfigurable resource area; as shown in (B) in Figure 4, on the physical area, the hollow circle area is defined as a non-reconfigurable resource area (dotted line area), The solid circle area is defined as the reconfigurable resource area (solid line area); in this application example, the reconfigurable resource area is used as the resource area to be reconfigured.

Divide the resource area to be reconfigured into basic units; determine the number of reconfigurable devices in the basic unit according to the target function of the basic unit, and the basic units are physically adjacent; as shown in (C) in Figure 4, each The basic unit includes 4 CLBs that support dynamic reconfiguration. After the 4 CLBs are written into the bit stream file, they can cooperate with each other to realize a basic function of the target circuit. The resource area to be reconfigured is divided into For the 12 basic units (JB1-JB12), the reconfigurable devices with redundant corners are not processed (also not shown in FIG. 4 ).

S302: Allocate resources for the target circuit;

The target circuit includes a fixed sub-circuit and a reconfigurable sub-circuit, and allocates resources in a non-reconfigurable resource area for the fixed sub-circuit, and allocates basic units for the reconfigurable sub-circuit; the present invention will not repeat the description of the resource allocation method for the fixed sub-circuit. Only the resource allocation method of the reconfigured sub-circuit is described. The prior art is to allocate a lot of basic devices such as CLB, DSP and editable interconnection wires (these devices need to be coded one by one), but the present invention is for it. Allocate basic units (the number is much smaller than the number of basic devices), as shown in Figure 5, allocate 2 basic units for subcircuit c, allocate 3 basic units for subcircuit d, and allocate 5 basic units for subcircuit e ;

S303: converting the target circuit into a bit stream file of the basic unit;

This step is only described for the bit stream file of the reconstructed sub-circuit in the target circuit, and the bit stream file only needs to be generated once for the fixed sub-circuit, so no further description is given;

As shown in Figure 5, the content of the bit stream file for each reconstructed sub-circuit in the target circuit 1 (the circuit before reconstruction) is as follows:

The bit stream file of sub-circuit c includes 2 sub-files (corresponding to 2 basic units), namely: bit stream data C1, address JB1, timing 1, bit stream data C2, address JB7, timing 1;

The bitstream file of subcircuit d includes 3 subfiles (corresponding to 3 basic units), which are: bitstream data D1, address JB2, timing 1, bitstream data D2, address JB8, timing 1, bitstream data D3, address JB9, timing 1;

The bit stream file of sub-circuit e includes 5 sub-files (corresponding to 5 basic units), which are: bit stream data E1, address JB3, timing 1, bit stream data E2, address JB4, timing 1, bit stream data E3, address JB5, timing 1, bit stream data E4, address JB10, timing 1, bit stream data E5, address JB11, timing 1;

As shown in Figure 5, the content of the bit stream file for each reconstructed sub-circuit in the target circuit 2 (reconstructed circuit) is as follows:

The bit stream file of the first sub-circuit c includes 2 sub-files (corresponding to 2 basic units), namely: bit stream data C1, address JB1, timing 2, bit stream data C2, address JB7, timing 2;

The bit stream file of the second sub-circuit c includes 2 sub-files (corresponding to 2 basic units), which are respectively: bit stream data C1, address JB2, timing 2, bit stream data C2, address JB8, timing 2;

The bit stream file of the first sub-circuit d includes 3 sub-files (corresponding to 3 basic units), which are: bit stream data D1, address JB3, timing 2, bit stream data D2, address JB9, timing 2, bit stream data D3, address JB10, timing 2;

The bit stream file of the second sub-circuit d includes 3 sub-files (corresponding to 3 basic units), namely: bit stream data D1, address JB4, timing 2, bit stream data D2, address JB5, timing 2, bit stream data D3 , address JB11, timing 2;

S304: Constrain the bit stream file to the corresponding basic unit;

As shown in Figure 6, a control unit and a storage unit are set for each basic unit, and the storage unit may be composed of a block memory (BRAM); specifically,

Basic unit: It is mainly composed of reconfigurable devices such as configurable logic blocks (CLB) and digital signal processors (DSP), which realize functions such as mathematical operations and logic processing. During work, the data is input from the IO port and processed by digital logic , the reconfigurable logic unit outputs the processed data;

Storage unit: mainly used to store the configuration bit stream that needs to be reconstructed, consisting of block memory (BRAM);

Control unit: Received from an external command, when the configuration bit stream needs to be replaced, the CPU sends a reconstruction request. After receiving the request, the control unit imports the bit stream data corresponding to the timing into the basic unit to replace the previous bit stream file and realize the new circuit; when the basic unit is configuring the bit stream data, the control unit sends a BUSY command to prevent input data, when the configuration is completed, the control unit outputs a DONE command to allow input, and informs the CPU that the configuration is over and is ready to accept the next reconstruction request ;

According to the assumptions in the previous steps, there are two bit stream files stored in the storage units corresponding to the basic units JB1-5 and 7-11, as shown in Table 2 below:

Table 2

S305: Complete the reconstruction according to the control signal;

The control unit of each basic unit controls the reconfiguration timing according to external signals, such as the reconfiguration signal sent by the user through the buttons of the development tool;

After completing the function test of the target circuit 1, the user needs to test the function of the target circuit 2, press the reconfiguration button of the development tool, and perform reconstruction at this time. The data is imported into the basic unit to replace the bit stream data with a timing of 1 to realize new circuit functions. The schematic diagram of the sub-circuit structure before and after reconstruction is shown in Figure 5;

As shown in Figure 5, before reconstruction, the bit stream file in the basic unit is bit stream data with a time sequence of 1. At this time, the basic units JB1 and JB7 realize the function of sub-circuit c; the basic units JB2, JB8 and JB9 realize The function of sub-circuit d; the basic units JB3, JB4, JB5, JB10 and JB11 realize the function of sub-circuit e; after reconstruction, the bit stream file in the basic unit is bit stream data with a sequence of 2. At this time, the basic unit JB1 and JB7 realize the function of the first sub-circuit c; basic units JB2 and JB8 realize the function of the second sub-circuit c; basic units JB3, JB9 and JB10 realize the function of the first sub-circuit d; basic units JB4, JB5 and JB11 realizes the function of the second sub-circuit d.

In summary, through the implementation of the present invention, there are at least the following beneficial effects:

Determine the resource area to be reconfigured in the programmable logic device according to the needs, and divide it into basic units, the basic unit includes at least one reconfigurable device, and these reconfigurable devices can realize basic logic after writing bit stream data function, that is, each basic unit can realize some functions of the target circuit. On this basis, each basic unit is reconstructed separately, and the reconstruction technology with the basic unit as the smallest reconstruction unit is realized, which is different from the existing basic Compared with the reconfiguration technology in which the device is the smallest reconfiguration unit, the minimum reconfiguration range is increased, and the number of control signals and data streams required for reconfiguration will be reduced, reducing the device complexity and reconfiguration cost of programmable logic devices ;

Furthermore, only the reconfigurable sub-circuits in the target circuit that need to be reconfigured are constrained to the resource area to be reconfigured, which reduces the waste of reconfigurable resources.

The above are only specific embodiments of the present invention, and do not limit the present invention in any form. Any simple modification, equivalent change, combination or modification made to the above embodiments according to the technical essence of the present invention still belong to this invention. The protection scope of the technical solution of the invention.

Claims (12)

1. a programmable logic device (PLD) reconstructing method, is characterized in that, comprising:

That determines programmable logic device (PLD) treats reconstruct resource-area;

Treat that reconstruct resource dividing is divided at least one elementary cell by described, described elementary cell comprises at least one reconfigurable device;

Respectively each elementary cell is reconstructed.

2. programmable logic device (PLD) reconstructing method as claimed in claim 1, it is characterized in that, described elementary cell also comprises reconfigurable connection between described reconfigurable device and other devices.

3. programmable logic device (PLD) reconstructing method as claimed in claim 1, it is characterized in that, described reconfigurable device comprises configurable logic blocks CLB.

4. the programmable logic device (PLD) reconstructing method as described in any one of claims 1 to 3, it is characterized in that, treat that reconstruct resource dividing is divided at least one elementary cell to comprise by described: treat that reconstruct resource-area is divided at least one elementary cell according to physical region by described; Or, treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function by described.

5. programmable logic device (PLD) reconstructing method as claimed in claim 4, it is characterized in that, described objective function comprises: the function that described elementary cell needs realize, or described in wait to reconstruct the function that resource-area needs realization.

6. the programmable logic device (PLD) reconstructing method as described in any one of claims 1 to 3, is characterized in that, is reconstructed respectively and comprises: the new bit stream file generating each elementary cell according to objective function respectively to each elementary cell; The new bit stream file of each elementary cell is configured to corresponding elementary cell.

7. a programmable logic device (PLD) reconfiguration device, is characterized in that, comprising:

Determination module, for determine programmable logic device (PLD) wait reconstruct resource-area;

Divide module, for treating that reconstruct resource dividing is divided at least one elementary cell by described, described elementary cell comprises at least one reconfigurable device;

Reconstructed module, for being reconstructed each elementary cell respectively.

8. programmable logic device (PLD) reconfiguration device as claimed in claim 7, it is characterized in that, described elementary cell also comprises reconfigurable connection between described reconfigurable device and other devices.

9. programmable logic device (PLD) reconfiguration device as claimed in claim 7, it is characterized in that, described reconfigurable device comprises configurable logic blocks CLB.

10. the programmable logic device (PLD) reconfiguration device as described in any one of claim 7 to 9, is characterized in that, described division module specifically for: by described treat reconstruct resource-area be divided at least one elementary cell according to physical region; Or, treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function by described.

11. programmable logic device (PLD) reconfiguration devices as claimed in claim 10, it is characterized in that, described objective function comprises: the function that described elementary cell needs realize, or described in wait to reconstruct the function that resource-area needs to realize.

12. programmable logic device (PLD) reconfiguration devices as described in any one of claim 7 to 9, it is characterized in that, described reconstructed module is specifically for generating the new bit stream file of each elementary cell respectively according to objective function; The new bit stream file of each elementary cell is configured to corresponding elementary cell.