CN104425275B - The forming method of semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate having a first region and a second region; forming a first dummy fin on the surface of the first region of the semiconductor substrate, and forming a first dummy fin on the surface of the semiconductor substrate A second dummy fin is formed on the surface of the second region; an insulating material layer is formed on the surface of the semiconductor substrate, and the surface of the insulating material layer is flush with the top surfaces of the first dummy fin and the second dummy fin; The first dummy fin is formed to form a first groove; the first semiconductor material is filled in the first groove to form a first fin, and the top surface of the first fin is flush with the top surface of the insulating material layer ; removing the second dummy fin to form a second groove; filling the second groove with a second semiconductor material layer to form a second fin, the top surface of the second fin and the insulating material layer The top surface is flush. The above method can form a FinFET with different fin materials, thereby improving the performance of the FinFET.

Description

Formation method of semiconductor structure

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure.

Background technique

With the continuous development of semiconductor process technology, the process node is gradually reduced, and the gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance. Fin field effect transistor (Fin FET) is obtained as a multi-gate device. received widespread attention.

A fin field effect transistor is a common multi-gate device, and FIG. 1 shows a schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art. As shown in FIG. 1 , it includes: a semiconductor substrate 10, on which a protruding fin 11 is formed, and the fin 11 is generally obtained by etching the semiconductor substrate 10; a dielectric layer 12, Covering the surface of the semiconductor substrate 10 and a part of the sidewall of the fin 11; the gate structure 13, straddling the fin 11, covering part of the top and sidewall of the fin 11, the gate structure 13 includes a gate dielectric layer (not shown in the figure) and a gate electrode (not shown in the figure) on the gate dielectric layer. For the fin field effect transistor, the top of the fin 11 and the parts where the sidewalls on both sides are in contact with the gate structure 13 become the channel region, that is, there are multiple gates, which is beneficial to increase the driving current and improve device performance.

The performance of the fin field effect transistor formed in the prior art needs to be further improved.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a semiconductor structure, which adopts the method of forming an N-type fin field effect transistor and a P-type fin field effect transistor with different fin materials.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate has a first region and a second region; forming a second region on the surface of the first region of the semiconductor substrate A dummy fin, forming a second dummy fin on the surface of the second region of the semiconductor substrate; forming an insulating material layer on the surface of the semiconductor substrate, the surface of the insulating material layer is in contact with the first dummy fin, the second The top surfaces of the two dummy fins are flush; the first dummy fin is removed to form a first groove; the first groove is filled with a first semiconductor material to form a first fin, and the first fin The top surface of the portion is flush with the top surface of the insulating material layer; the second dummy fin is removed to form a second groove; the second semiconductor material layer is filled in the second groove to form a second fin, so The top surface of the second fin is flush with the top surface of the insulating material layer.

Optionally, the first dummy fin and the second dummy fin are formed by a double patterning process or a multiple patterning process.

Optionally, the method for forming the first dummy fin and the second dummy fin includes: forming a sacrificial layer on the surface of the semiconductor substrate, a mask layer on the surface of the sacrificial layer, and a mask layer on the surface of the mask layer. A photoresist layer on the surface, the photoresist layer covers part of the mask layer; sidewalls are formed on the surface of the sidewalls of the photoresist layer, and the sidewalls on one side of the photoresist layer are located on the semiconductor substrate Above the first region, the sidewall on the other side of the photoresist layer is located above the second region of the semiconductor substrate; remove the photoresist layer; use the sidewall as a mask to etch the mask The film layer and the sacrificial layer are connected to the surface of the semiconductor substrate, and a first dummy fin is formed on the first region, and the first dummy fin includes a first part of the sacrificial layer on the first region and a top part of the first part of the sacrificial layer. A first part of the mask layer, forming a second dummy fin on the surface of the second region, the second dummy fin including a second part of the sacrificial layer on the second region and a second part on top of the second part of the sacrificial layer masking layer; removing the sidewalls.

Optionally, the material of the sidewall is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide nitride; the material of the mask layer is silicon oxide, silicon nitride , silicon oxynitride, silicon carbide, silicon carbide nitride, and amorphous silicon, the material of the mask layer is different from that of the sidewall; the material of the sacrificial layer is silicon oxide, silicon nitride, nitrogen One or more of silicon oxide, silicon carbide, silicon carbide nitride, and amorphous silicon, the material of the sacrificial layer is different from that of the mask layer.

Optionally, the material of the sacrificial layer is silicon nitride, the material of the mask layer is amorphous silicon, and the material of the sidewall is silicon oxide.

Optionally, the method further includes: after forming the insulating material layer, forming a protection layer on top surfaces of the first dummy fin and the second dummy fin.

Optionally, the method for forming the protective layer is an oxidation process.

Optionally, the method for removing the first dummy fin and forming the first groove includes: forming a second hard mask layer covering part of the insulating material layer and the second dummy fin above the second region, using A wet etching process removes the first dummy fin, and forms a first groove on the surface of the first region of the semiconductor substrate.

Optionally, the material of the second hard mask layer is silicon nitride.

Optionally, a selective deposition process is used to fill the first groove with the first semiconductor material.

Optionally, the material of the first semiconductor material is Si, GaAs or GaN.

Optionally, the first fin is doped with N-type ions, and the N-type ions include at least one of P, As, and Sb ions.

Optionally, the method for doping the first fin is an in-situ doping process.

Optionally, the method for removing the second dummy fins and forming the second grooves includes: forming a first hard mask layer covering part of the insulating material layer and the first fins above the first region, using wet The second dummy fin is removed by an etching process to form a second groove on the surface of the second region of the semiconductor substrate.

Optionally, the material of the second hard mask layer is silicon nitride.

Optionally, a selective deposition process is used to fill the second groove with a second semiconductor material layer.

Optionally, the material of the second semiconductor material layer is SiGe or Ge.

Optionally, the second fin is doped with P-type ions, and the P-type ions include at least one of B, Ga, and In.

Optionally, the method of doping the second fin is an in-situ doping process.

Optionally, it also includes etching the insulating material layer to form an insulating layer, the surface of the insulating layer is lower than the top surfaces of the first fin and the second fin; the surface of the insulating layer on the first region forming a first gate structure spanning and covering part of the first fin; forming a second gate structure spanning and covering part of the second fin on the surface of the insulating layer on the second region; A first source/drain is formed in the first fins on both sides of the gate structure; a second source/drain is formed in the second fins on both sides of the second gate structure.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, the first dummy fin is formed on the first region of the semiconductor substrate, the second dummy fin and the insulating material layer on the surface of the semiconductor substrate are formed on the second region, and then the the first dummy fin, forming a first groove, and filling the first semiconductor material in the first groove to form the first fin; removing the second dummy fin, forming a second groove, and The first groove is filled with a second semiconductor material to form a second fin. According to the type of FinFETs to be formed on the first fin and the second fin, the first fin and the second fin can be formed by using the corresponding first semiconductor material and the second semiconductor material, so that the first fin and the second fin can be formed simultaneously FinFETs with different fin materials.

Further, the first semiconductor material is Si, GaAs or GaN, and the electron mobility of the first fin formed by the first semiconductor material is relatively high, which can improve the performance of the N-type fin field effect transistor; the first The second semiconductor material is SiGe or Ge, and the mobility of holes in the second fin formed by the second semiconductor material is relatively high, which can improve the performance of the P-type fin field effect transistor.

Description of drawings

Fig. 1 is the structural representation of the fin field effect transistor transistor that the prior art of the present invention forms;

2 to 13 are structural schematic diagrams of the formation process of the semiconductor structure according to the embodiment of the present invention.

Detailed ways

As mentioned in the background art, the performance of the fin field effect transistor formed in the prior art needs to be further improved.

Research has found that the fins of N-type fin field effect transistors and P-type fin field effect transistors commonly formed in the prior art use the same fin material, while the N-type fin field effect transistors and P-type fin field effect transistors The mobility rates of the corresponding carriers in the same material, that is, electrons and holes in the N-type FET, are different, which leads to the saturation of the formed N-type FIN-FET and P-type FIN-FET. The current is not the same. As the process node drops further, this difference will become more prominent. Studies have found that for P-type fin field effect transistors, the material of the fins can be Ge or SiGe, which can improve the mobility of hole carriers in P-type fin field effect transistors, thereby improving the efficiency of P-type fin field effect transistors. The performance of the field effect transistor; for the N-type fin field effect transistor, the material of the fin can be Si or GaN, which can make the N-type fin field effect transistor have a higher electron carrier mobility, thereby improving the N Type fin field effect transistor performance. How to simultaneously form N-type fin field effect transistors and P-type fin field effect transistors with different fin materials on a substrate has become an urgent problem to be solved.

The method for forming a semiconductor structure in the embodiment of the present invention can simultaneously form N-type fin field effect transistors and P-type fin field effect transistors with different fin materials, and can improve the performance of the N-type fin field effect transistors and P-type fin field effect transistors. Type fin field effect transistor performance.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 2 , a semiconductor substrate 100 having a first region 101 and a second region 102 is provided.

The semiconductor substrate 100 may be silicon or silicon-on-insulator (SOI), and the semiconductor substrate 100 may also be germanium, silicon-germanium, gallium arsenide, or germanium-on-insulator. In this embodiment, the semiconductor substrate 100 The material is silicon.

FinFETs of different types are subsequently formed on the first region 101 and the second region 102 respectively. In this embodiment, an N-type fin field effect transistor is formed on the first region 101 , and a P-type fin field effect transistor is formed on the second region 102 .

Referring to FIG. 3 , a sacrificial layer 200 and a mask layer 201 located on the surface of the sacrificial layer 200 are formed on the surface of the semiconductor substrate 100 .

The material of the mask layer 201 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and amorphous silicon; the material of the sacrificial layer is silicon oxide, nitride One or more of silicon, silicon oxynitride, silicon carbide, silicon nitride carbide, and amorphous silicon, the material of the sacrificial layer is different from that of the mask layer. In this embodiment, the material of the sacrificial layer 200 is silicon nitride, and the material of the mask layer 201 is amorphous silicon.

The sacrificial layer 200 and the mask layer 201 are formed by a chemical vapor deposition process. The total thickness of the sacrificial layer 200 and the mask layer 201 is the same as the thickness of the first fin and the second fin formed subsequently. The thickness of the layer 200 is 50nm-200nm, and the thickness of the mask layer 201 is 10nm-50nm.

Referring to FIG. 4 , a photoresist layer 300 and sidewalls 301 located on both sides of the photoresist layer are formed on the surface of the mask layer 201 .

The photoresist layer 300 covers part of the surface of the mask layer 201 on the first region 101 and the second region 102, and the size of the photoresist layer 300 defines the first fin and the second fin to be formed subsequently. spacing between.

The material of the sidewall 301 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide nitride, and the material of the sidewall 301 is different from that of the mask layer 201. In an embodiment, the material of the sidewall 301 is silicon oxide.

The method for forming the sidewall 301 includes: forming a sidewall material layer covering the mask layer 201 and the photoresist layer 300, performing maskless etching on the sidewall material layer, and removing the The surface and part of the sidewall material layer on the top of the photoresist layer 300 form sidewalls 301 located on the sidewall surfaces on both sides of the photoresist layer 300 . The sidewall 301 on one side of the photoresist layer 300 is located above the first region 101 of the semiconductor substrate 100 , and the sidewall 301 on the other side of the photoresist layer 300 is located on the second region of the semiconductor substrate 100 . area 102 above.

The width of the sidewall 201 is 10nm-40nm, and the width of the sidewall 301 defines the width of the subsequently formed first fin and second fin.

Referring to FIG. 5 , the photoresist layer 300 is removed.

In this embodiment, the photoresist layer 300 is removed by a plasma ashing process containing oxygen. In other embodiments of the present invention, the photoresist layer 300 may also be removed by a wet etching process.

After the photoresist layer 300 is removed, the surface of the mask layer 201 has discrete sidewalls 301 , and the sidewalls 301 are subsequently used as masks for etching the mask layer 201 and the sacrificial layer 200 .

Please refer to FIG. 6 , using the sidewall 301 (please refer to FIG. 5 ) as a mask, etch the mask layer 201 (please refer to FIG. 5 ) and the sacrificial layer 200 (please refer to FIG. 5 ) to the semiconductor substrate 100 On the first region 101, a first dummy fin 231 is formed, and the first dummy fin 231 includes a first part of the sacrificial layer 211 on the first region 101 and a first part of the mask on top of the first part of the sacrificial layer 211. A film layer 221, forming a second dummy fin 232 on the surface of the second region 102, the second dummy fin 232 including the second part of the sacrificial layer 212 on the second region 102 and the top of the second part of the sacrificial layer 212 The second part of the mask layer 222 is removed, and then the spacer 301 is removed.

The first dummy fin 231 and the second dummy fin 232 are formed by a dry etching process, and the sidewall 301 is used as an etching mask to transfer the pattern of the sidewall 301 to the mask layer 201 (please refer to FIG. 5 ) After that, the sacrificial layer 200 is etched using the mask layer 201 as a mask (please refer to FIG. 5 ). The mask layer 201 can keep the sidewalls of the first dummy fin 231 and the second dummy fin 232 vertical to reduce etching errors.

In this embodiment, the above-mentioned method of forming the first dummy fin 231 and the second dummy fin 232 is a double patterning process. fin and a second dummy fin. The double patterning process or the multiple patterning process can obtain the first dummy fin part and the second dummy fin part with smaller adjacent pitches and smaller widths.

In other embodiments of the present invention, the sacrificial layer may also be etched after the patterned mask layer is directly formed on the surface of the sacrificial layer to form the first dummy fin and the second dummy fin.

Referring to FIG. 7 , an insulating material layer 400 is formed on the surface of the semiconductor substrate 100 , the surface of the insulating material layer 400 is flush with the top surfaces of the first dummy fin 231 and the second dummy fin 232 .

The material of the insulating material layer 400 is different from the materials of the first part of the sacrificial layer 211 , the second part of the sacrificial layer 212 , the first part of the mask layer 221 and the second part of the mask layer 222 . In this embodiment, the material of the insulating material layer is silicon oxide. In other embodiments of the present invention, the insulating material layer 400 may also be a dielectric material such as silicon nitride, silicon oxynitride, or silicon oxycarbide.

The method for forming the insulating material layer 400 includes: depositing an insulating material on the surface of the semiconductor substrate 100 by using a chemical vapor deposition process, the insulating material covering the first dummy fin 231 and the second dummy fin 232; The first part of the mask layer 221 and the second part of the mask layer 222 are stop layers, and the insulating material is planarized by using a chemical mechanical masking process to form an insulating material layer 400, so that the insulating material layer 400 The surface of the first dummy fin portion 231 and the top surface of the second dummy fin portion 232 are flush with each other.

In this embodiment, after the insulating material layer is formed, the protection layer 202 is further formed on the surfaces of the first dummy fin portion 231 and the second dummy fin portion 232 . In this embodiment, since the materials of the first partial mask layer 221 and the second partial mask layer 222 are amorphous silicon, the surfaces of the first partial mask layer 221 and the second partial mask layer 222 can be made of The protection layer 201 is formed by an oxidation process, and the oxidation process may be a thermal oxidation or a wet oxidation process.

The protective layer 202 has a thickness of 0.5 nm˜10 nm. The protective layer 202 plays a role in protecting the first part of the mask layer 221 or the second part of the mask layer 222 during the subsequent selective epitaxy process, so as to avoid Layer 222 forms an epitaxial layer.

In other embodiments of the present invention, the material of the first part of the mask layer and the second part of the mask layer is not a semiconductor material, and selective epitaxy cannot be performed on the surface of the first part of the mask layer and the second part of the mask layer. For growing the semiconductor material, it may not be necessary to form a protective layer on top of the first partial mask layer and the second partial mask layer.

Please refer to FIG. 8 , a second hard mask layer 502 covering part of the insulating material layer 401 and the second dummy fin 232 is formed above the first region 102 , and the protection of the first dummy fin 231 and its top is removed. layer 202 (please refer to FIG. 7 ), forming a first groove 401 .

The material of the second hard mask layer 502 is silicon nitride, and the first dummy fins 231 are removed by a wet etching process (please refer to FIG. 7 ), and formed on the surface of the first region 101 of the semiconductor substrate 100. The first groove 401 . When using a wet etching process to remove the first dummy fin 231 and the protective layer 202 on top (please refer to FIG. 7 ), different etching solutions need to be selected according to different materials. For example, HF solution can be used to remove the protective layer 202 Afterwards, the first part of the mask layer 221 is etched and removed with a KOH solution, and the first part of the sacrificial layer 211 is removed with a phosphoric acid solution.

In other embodiments of the present invention, the first dummy fin portion 231 may also be removed by a dry etching process (please refer to FIG. 7 ). A mask layer is formed on the surface of the insulating material layer 400, the mask layer exposes the surface of the protective layer 202 on the top of the first dummy fin portion 231 on the first region 101, and then etched and removed by a dry etching process The protection layer 202 and the first dummy fin portion 231 .

During the process of removing the first dummy fin portion 231 (please refer to FIG. 7 ), the surface of the second dummy fin portion 232 on the second region 102 is protected by the second hard mask layer 502 and will not be damaged.

Referring to FIG. 9 , the second hard mask layer 502 (please refer to FIG. 8 ) is removed, and the first groove 401 (please refer to FIG. 8 ) is filled with a first semiconductor material to form a first fin 601 . The top surface of the first fin portion 601 is flush with the top surface of the insulating material layer 400 .

The first semiconductor material is Si or a III-V semiconductor material, and the III-V semiconductor material may be GaN or GaAs. Subsequently, an N-type fin field effect transistor is formed on the first region 101. The electron mobility of the first fin 601 formed by the first semiconductor material is relatively high, and the N-type fin field effect transistor formed on the first fin 601 is subsequently formed. Performance of FinFETs.

A specific method for forming the first fin portion 601 includes: filling the first groove 401 (please refer to FIG. 8 ) with a first semiconductor material by using a selective deposition process. Since the top of the second dummy fin 232 on the second region 102 has a protective layer, the first semiconductor material will not be grown on the surface of the second part of the mask layer 302 .

The temperature for forming the first semiconductor material in the selective epitaxial process is 600°C to 1100°C, the pressure is 1 torr to 500 torr, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , and HCl gas and H ₂ are also included, wherein the silicon source The flow rates of gas and HCl are both 1 sccm to 1000 sccm, and the flow rates of _H2 are 0.1 slm to 50 slm.

After the first groove is filled with the first semiconductor material, the insulating material layer 400 is used as a stop layer to planarize the first semiconductor material to form a first fin 601, and the first fin 601 is formed. The top surface of a fin 601 is flush with the surface of the insulating material layer 400 .

The first fin portion 601 may also be doped with N-type ions, including at least one of P, As, and Sb ions. While filling the first groove with the first semiconductor material, an in-situ doping process can be performed to dope the first semiconductor material, so as to form the N-type doped first fin 601 . The threshold voltage of the subsequently formed N-type fin field effect transistor can be adjusted by adjusting the doping concentration of the N-type ions in the first fin portion 601 . In other embodiments of the present invention, N-type ion implantation may be performed on the first fin 601 after forming the first fin 601 , so as to form the N-type doped first fin 601 .

Referring to FIG. 10 , a first hard mask layer 501 covering part of the insulating material layer 400 and the first fin portion 601 is formed above the first region 101 , and the second dummy fin portion 232 and the protective layer on the top thereof are removed. 202 (please refer to FIG. 9 ), forming a second groove 402 .

The material of the first hard mask layer 501 is silicon nitride, and the second dummy fins 232 (please refer to FIG. 9 ) are removed by a wet etching process, and formed on the surface of the second region 102 of the semiconductor substrate 100. The second groove 402 . When using a wet etching process to remove the second dummy fin 232 and the protective layer 202 on top (please refer to FIG. 9 ), it is necessary to select different etching solutions according to different materials. For example, HF solution can be used to remove the protective layer 202 Afterwards, the second part of the mask layer 222 is removed by etching with a KOH solution, and the second part of the sacrificial layer 212 is removed with a phosphoric acid solution.

In other embodiments of the present invention, the second dummy fin portion 232 may also be removed by a dry etching process (please refer to FIG. 9 ). A mask layer is formed on the surface of the insulating material layer 400, the mask layer exposes the surface of the protective layer 202 on the top of the second dummy fin portion 232 on the second region 102, and then etched and removed by a dry etching process The protection layer 202 and the second dummy fin portion 232 .

During the process of removing the second dummy fin 232 (please refer to FIG. 9 ), the surface of the first fin 601 on the first region 101 is protected by the first hard mask layer 501 and will not be damaged.

Referring to FIG. 11 , the first hard mask layer 501 (please refer to FIG. 10 ) is removed, and a second semiconductor material is filled in the second groove 402 (please refer to FIG. 10 ) to form a second fin 602 . The top surface of the second fin portion 602 is flush with the top surface of the insulating material layer 400 .

The second semiconductor material is SiGe or Ge, and a P-type fin field effect transistor is subsequently formed on the second region 102. The hole mobility of the second fin 602 formed by the second semiconductor material is relatively high, which can improve Performance of P-type FinFETs.

A specific method for forming the second fin portion 602 includes: using a selective deposition process to fill the second semiconductor material in the second groove 402 (please refer to FIG. 10 ). In this embodiment, the second semiconductor material is SiGe, the reaction temperature of the selective epitaxy process used is 600°C-1100°C, the pressure is 1 Torr-500 Torr, and the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , The germanium source gas is GeH ₄ , and also includes HCl gas and H ₂ , wherein the flow rates of silicon source gas, germanium source gas, and HCl are all 1 sccm-1000 sccm, and the flow rates of H ₂ are 0.1 slm-50 slm.

After the second groove is filled with the second semiconductor material, the insulating material layer 400 is used as a stop layer to planarize the second semiconductor material to form a second fin 602, and the second fin 602 is formed. Top surfaces of the two fins 602 are flush with the surface of the insulating material layer 400 .

The second fin portion 602 may also be doped with P-type ions, including at least one of B, Ga, and In ions. While filling the second groove with the second semiconductor material, an in-situ doping process can be performed to dope the second semiconductor material, so as to form a P-type doped second fin 602 . The threshold voltage of the subsequently formed P-type fin field effect transistor can be adjusted by adjusting the doping concentration of the P-type ions in the second fin portion 602 . In other embodiments of the present invention, P-type ion implantation may be performed on the second fin 602 after forming the second fin 602 , so as to form a P-type doped second fin 602 .

Referring to FIG. 12 , the insulating material 400 (please refer to FIG. 11 ) is etched to form an insulating layer 401 , the surface of the insulating layer 401 is lower than the top surfaces of the first fin 601 and the second fin 602 .

The insulating material 400 is etched by a dry etching process (please refer to FIG. 11 ) to form an insulating layer 401, and the insulating layer 401 serves as the first gate structure subsequently formed on the first region 101, and in the second region The isolation structure between the second gate structure formed on the semiconductor substrate 102 and the semiconductor substrate 100, and the insulating layer 401 can also be used as an N-type fin formed on the first fin 601 and the second fin 602 respectively. The isolation structure between the field effect transistor and the P-type fin field effect transistor.

Please refer to FIG. 13 , a first gate structure 701 is formed on the surface of the insulating layer 401 on the first region 101 across and covers part of the first fin 601; The second gate structure 702 straddles and covers part of the second fin.

The first gate structure 701 includes a first gate dielectric layer 711 located on a part of the surface of the insulating layer 401 and a part of the surface of the first fin 601 on the first region 101, and a first gate dielectric layer 711 located on the surface of the first gate dielectric layer 711. gate 721; the second gate structure 702 includes a second gate dielectric layer 712 located on a part of the surface of the insulating layer 401 and a part of the surface of the second fin 602 on the second region 102; The second grid 722 on the surface. The first gate structure 701 and the second gate structure 702 are disconnected from each other.

In this embodiment, after forming the first gate structure 701 and the second gate structure 702, a first source/drain ( not shown in the figure); a second source/drain (not shown in the figure) is formed in the second fin portion 602 on both sides of the second gate structure 702 .

In this embodiment, it also includes forming a medium located on the surface of the insulating layer 401 and covering part of the first fin 601 and the second fin 602, the surface of which is flush with the first gate structure 701 and the second gate structure 702 layer 700 , the first gate structure 701 and the second gate structure 702 are separated by a dielectric layer 700 .

In this embodiment, the first fins and the second fins formed are respectively different semiconductor materials, wherein the material of the first fins is Si or a III-V semiconductor material, and the III-V semiconductor material may be GaN or GaAs, the material of the first fin can improve the mobility of electrons, thereby improving the performance of the N-type fin field effect transistor subsequently formed on the first fin; the material of the second fin is SiGe or Ge The material of the second fin can increase the mobility of holes, thereby improving the performance of the P-type fin field effect transistor subsequently formed on the second fin.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. A method for forming a semiconductor structure, comprising: providing a semiconductor substrate having a first region and a second region; A sacrificial layer, a mask layer on the surface of the sacrificial layer, and a photoresist layer on the surface of the mask layer are formed on the surface of the semiconductor substrate, the photoresist layer covers part of the mask layer, and the sacrificial layer covers part of the mask layer. The total thickness of the layer and the mask layer is the same as the thickness of the subsequently formed first and second fins; A side wall is formed on the surface of the side wall of the photoresist layer, the side wall located on one side of the photoresist layer is located above the first region of the semiconductor substrate, and the side wall located on the other side of the photoresist layer is located above the first region of the semiconductor substrate. Above the second region of the semiconductor substrate, the width of the sidewall defines the width of the subsequently formed first fin and second fin; removing the photoresist layer; Using the sidewall as a mask, etching the mask layer and the sacrificial layer to the surface of the semiconductor substrate to form a first dummy fin on the first region, the first dummy fin includes a The first part of the sacrificial layer and the first part of the mask layer on the top of the first part of the sacrificial layer form a second dummy fin on the surface of the second region, and the second dummy fin includes a second part of the sacrificial fin located on the second region. layer and a second partial mask layer on top of said second partial sacrificial layer; removing said side wall; An insulating material layer is formed on the surface of the semiconductor substrate, and the surface of the insulating material layer is flush with the top surfaces of the first dummy fin and the second dummy fin; removing the first dummy fin to form a first groove; Filling the first groove with a first semiconductor material to form a first fin, the top surface of the first fin is flush with the top surface of the insulating material layer; removing the second dummy fin to form a second groove; filling the second groove with a second semiconductor material layer to form a second fin, the top surface of the second fin is flush with the top surface of the insulating material layer; Etching the insulating material layer to form an insulating layer, the surface of the insulating layer is lower than the top surfaces of the first fin and the second fin; the surface of the insulating layer on the first region is formed across and covers part of the second fin. A first gate structure of a fin; a second gate structure spanning and covering a part of the second fin is formed on the surface of the insulating layer on the second region; a second gate structure on both sides of the first gate structure A first source/drain is formed in a fin; a second source/drain is formed in a second fin on both sides of the second gate structure. 2. The method for forming a semiconductor structure according to claim 1, wherein the material of the sidewall is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide nitride The material of the mask layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and amorphous silicon, and the material of the mask layer is different from that of the sidewall; The material of the sacrificial layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and amorphous silicon, and the material of the sacrificial layer is different from that of the mask layer. 3. The method for forming a semiconductor structure according to claim 2, wherein the material of the sacrificial layer is silicon nitride, the material of the mask layer is amorphous silicon, and the material of the sidewall is oxide silicon. 4. The method for forming a semiconductor structure according to claim 3, further comprising: after forming the insulating material layer, forming a protective layer on the top surfaces of the first dummy fin and the second dummy fin . 5 . The method for forming a semiconductor structure according to claim 4 , wherein the method for forming the protective layer is an oxidation process. 6. The method for forming a semiconductor structure according to claim 1, wherein the method for removing the first dummy fin and forming the first groove comprises: forming a covering part of an insulating material layer above the second region and the second hard mask layer of the second dummy fin, the first dummy fin is removed by a wet etching process, and a first groove is formed on the surface of the first region of the semiconductor substrate. 7. The method for forming a semiconductor structure according to claim 6, wherein the material of the second hard mask layer is silicon nitride. 8 . The method for forming a semiconductor structure according to claim 1 , wherein a selective deposition process is used to fill the first groove with the first semiconductor material. 9. The method for forming a semiconductor structure according to claim 8, wherein the first semiconductor material is Si, GaAs or GaN. 10 . The method for forming a semiconductor structure according to claim 9 , wherein the first fin is doped with N-type ions, and the N-type ions include at least one of P, As, and Sb ions. 11 . 11 . The method for forming a semiconductor structure according to claim 10 , wherein the method of doping the first fin is an in-situ doping process. 12. The method for forming a semiconductor structure according to claim 1, wherein the method for removing the second dummy fin and forming the second groove comprises: forming a covering part of an insulating material layer above the first region and the first hard mask layer of the first fin, and the second dummy fin is removed by using a wet etching process to form a second groove on the surface of the second region of the semiconductor substrate. 13. The method for forming a semiconductor structure according to claim 12, wherein the material of the first hard mask layer is silicon nitride. 14 . The method for forming a semiconductor structure according to claim 1 , wherein a selective deposition process is used to fill the second groove with a second semiconductor material layer. 15. The method for forming a semiconductor structure according to claim 14, wherein the material of the second semiconductor material layer is SiGe or Ge. 16 . The method for forming a semiconductor structure according to claim 15 , wherein the second fin is doped with P-type ions, and the P-type ions include at least one of B, Ga, and In ions. 17 . The method for forming a semiconductor structure according to claim 16 , wherein the method of doping the second fin is an in-situ doping process.