CN104377289B - Packaging structure for two transistors and power supply circuit comprising same - Google Patents

Abstract

A package structure of a double transistor, comprising a body and first to fifth functional pins, the first to third functional pins constitute the gate, drain and source of the first transistor in the double transistor, The third to fifth function pins form the drain, gate and source of the second transistor in the dual transistor; the first and second function pins are arranged on the first side of the body, The third and fourth function pins are arranged on the second side relative to the first side of the body, and the fifth function pin is arranged on the bottom of the body. The invention also provides a power supply circuit using the packaging structure. In the package structure of the above-mentioned double transistors, the third function pin is arranged on the second side of the body, thereby saving space when wiring the multi-phase power supply circuit.

Description

Package structure of double transistor and power supply circuit using the package structure

technical field

The invention relates to a package structure of double transistors and a power supply circuit using the package structure.

Background technique

The package structure of existing double transistor (DUAL MOSFET) 11 is as shown in Figure 1, and pin G1, D1 and S1 constitute the gate, drain and source of the first transistor; Pin G2, D2 and S2 constitute the second The gate, drain and source of a transistor. Wherein, the source of the first transistor and the drain of the second transistor are packaged as the same pin S1/D2, that is, a switch node pin.

10 in FIG. 2 is a circuit diagram of a first-phase power supply circuit connected between a pulse width modulation (Pulse Width Modulation, PWM) controller 20 and a central processing unit (Central Processing Unit, CPU) 30 in a multi-phase power supply circuit, wherein, The source of the field effect transistor Q1 and the drain of the field effect transistor Q2 are connected to the CPU 30 through an inductor L1 to provide power for the CPU 30 .

Please refer to Figure 3, since the switching node pin S1/D2 in the dual transistor 11 is located in the middle of the dual transistor 11 body, in order to save the space of the printed circuit board as much as possible, when wiring, the first end of the inductor L1 is close to the dual transistor 11 On one of the two opposite sides without pins, the other end of the inductor L1 is close to the CPU 30 , so that the switching node pin S1 / D2 in the dual transistor 11 and the first end of the inductor L1 minimize wiring. The double transistor 11 and the inductor L1 constitute the first phase power supply circuit 10, wherein the pin G1 of the first transistor in the double transistor 11 is connected to the first high-pass drive pin Hgate10 of the PWM controller 20, and the pin D1 of the first transistor is connected to a The voltage source Vin, the pin S1 is connected to the first end of the inductor L1. The pin G2 of the second transistor in the dual transistor 11 is connected to the first low-pass driving pin Lgate10 of the PWM controller 20 , the pin D2 of the second transistor is connected to the first end of the inductor L1 , and the pin S2 is grounded. That is, the PWM controller 20 supplies power to the CPU through the pin S1 of the first transistor and the pin D2 of the second transistor, that is, the switching node pin S1/D2 of the dual transistor 11 and the inductor L1.

When the power supply circuit is a multi-phase power supply circuit, such as a two-phase power supply circuit, that is, there is a second-phase power supply circuit 40 between the PWM controller 20 and the CPU 30 . When wiring, the double transistor 12 in the second phase power supply circuit 40 is close to one of the two opposite sides of the double transistor 11 in the first phase power supply circuit 10, wherein the first transistor in the double transistor 12 The pin G1 is connected to the second high-pass driving pin Hgate20 of the PWM controller 20 , the pin D1 of the first transistor is connected to a voltage source Vin, and the pin S1 is connected to the first end of the inductor L2 . The pin G2 of the second transistor in the dual transistor 12 is connected to the second low-pass driving pin Lgate20 of the PWM controller 20 , the pin D2 of the second transistor is connected to the first end of the inductor L2 , and the pin S2 is grounded.

At this time, there are four lines between the double transistor 11 and the double transistor 12, that is, the pin G2 of the second transistor in the double transistor 11 is connected to the line of the first low-pass drive pin Lgate10 of the PWM controller 20; The pin S2 of the second transistor is grounded, the pin G1 of the first transistor in the double transistor 12 is connected to the second high-pass drive pin Hgate20 of the PWM controller 20, and the pin D1 of the first transistor in the double transistor 12 is connected line of the voltage source Vin. In this way, a larger space is required on the printed circuit board to lay out the multi-phase power supply circuit, so as to avoid interference between lines.

Contents of the invention

In view of the above, it is necessary to provide a double-transistor packaging structure and a power supply circuit using the packaging structure, so as to make full use of the space on the printed circuit board when wiring the multi-phase power supply circuit.

A package structure of a double transistor, comprising a body and first to fifth functional pins, the first to third functional pins constitute the gate, drain and source of the first transistor in the double transistor, The third to fifth function pins form the drain, gate and source of the second transistor in the dual transistor; the first and second function pins are arranged on the first side of the body, The third and fourth function pins are arranged on the second side relative to the first side of the body, and the fifth function pin is arranged on the bottom of the body.

A power supply circuit using the package structure of the dual transistors, in the wiring area of the power supply circuit, the dual transistors are arranged between a pulse width modulation controller and an inductor, and the pulse width modulation controller passes through the dual The transistor and the inductor supply power to a central processing unit, the pulse width modulation controller is close to the first side of the dual-transistor body, and the first end of the inductor is close to the second side of the dual-transistor body; The first function pin of the double transistor is connected to the first high-pass drive pin of the pulse width modulation controller, the second function pin of the double transistor is connected to a voltage source, and the third function pin of the double transistor is The pin is connected to the first end of the inductor, the fourth function pin of the dual transistor is connected to the first low-pass drive pin of the pulse width modulation controller, and the fifth function pin of the dual transistor is grounded, The second end of the inductor is connected to the CPU.

In the package structure of the above-mentioned double transistors, the third function pin is arranged on the second side of the body, thereby saving space when wiring the multi-phase power supply circuit.

Description of drawings

FIG. 1 is a schematic diagram of a package structure of an existing dual transistor.

Fig. 2 is a circuit diagram of a multi-phase power supply circuit.

Fig. 3 is a wiring diagram of a conventional multi-phase power supply circuit.

Fig. 4 is a schematic diagram of the packaging structure of the double transistor of the present invention.

FIG. 5 is a wiring diagram of a multi-phase power supply circuit using the package structure of the dual transistors of the present invention.

Description of main component symbols

Dual Transistor 11, 12, 100, 200

First phase power supply circuit 10, 123

PWM controller 20

CPU 30, 900

Inductors L1, L2, L10, L20

Second phase power supply circuit 40, 223

Body 110

Bottom 111

first side 1

second side 2

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

detailed description

Below in conjunction with accompanying drawing and preferred embodiment the present invention is described in further detail:

Please refer to FIG. 4 , the packaging structure of the dual transistor 100 of the present invention includes a body 110 , function pins D1 and S2 located on the bottom surface 111 of the body 110 and function pins D1, G1, S1/D2 and G2 located on two opposite sides of the body 110 , wherein the function pins D1 and G1 located on two opposite sides of the body 110 are arranged on the first side 1 of the body 110, and the function pins S1/D2 and G2 are arranged on the second side relative to the first side 1 of the body 110 On side 2, the functional pins G1, D1 and S1 form the gate, drain and source of the first transistor; the functional pins G2, D2 and S2 form the gate, drain and source of the second transistor. Wherein, the number of each function pin can be set according to needs. In this embodiment, there are four function pins D1 and three function pins D1 are arranged on the first side 1 of the body 110, and the other one The function pin D1 is disposed on the bottom surface 111 of the body 110 , and three function pins S1 / D2 are disposed on the second side 2 of the body 110 .

Please refer to FIG. 5, in a multi-phase power supply circuit such as a two-phase power supply circuit, the first high-pass drive pin Hgate1 and the first low-pass drive pin Lgate1 of the pulse width modulation (Pulse WidthModulation, PWM) controller (not shown) pass through The dual transistors 100 and an inductor L10 are connected to a central processing unit (CPU) 900 for powering the CPU 900 . The second high-pass driving pin Hgate2 and the second low-pass driving pin Lgate2 of the PWM controller 20 are connected to a central processing unit (CPU) 900 through a pair of transistors 200 and an inductor L20 to provide power for the CPU 900 . Wherein, the packaging structure of the dual transistor 200 is the same as that of the dual transistor 100 .

When wiring, the first end of the inductor L10 is close to the second side 2 of the dual transistor 100, the other end of the inductor L10 is close to the CPU 900 and connected to the CPU 900, the inductor L10 and the dual The transistor 100 constitutes the first phase power supply circuit 123, wherein the functional pin G1 of the dual transistor 100 is connected to the first high-pass drive pin Hgate1 of the PWM controller 20, and the functional pin D1 of the dual transistor 100 is connected to a voltage source Vin , the function pin S1/D2 of the dual transistor 100 is connected to the first end of the inductor L10; the function pin G2 of the dual transistor 100 is connected to the first low-pass drive pin Lgate1 of the PWM controller 20, the The function pin S2 of the dual transistor 100 is grounded. That is, the PWM controller 20 supplies power to the CPU 900 through the function pins S1 / D2 of the dual transistor 100 and the inductor L10 .

Similarly, the wiring manner of the dual transistor 200 and the inductor L20 in the second phase power supply circuit 223 is the same as that of the first phase power supply circuit 123 . That is, the first end of the inductor L20 is close to the second side 2 of the dual transistor 200, and the other end of the inductor L20 is close to the CPU 900 and connected to the CPU 900, wherein the function of the dual transistor 200 is Pin G1 is connected to the second high-pass drive pin Hgate2 of the PWM controller 20, the function pin D1 of the dual transistor 200 is connected to the voltage source Vin, and the function pin S1/D2 of the dual transistor 200 is connected to the inductor L20 The first end of the first terminal; the function pin G2 of the dual transistor 200 is connected to the second low-pass drive pin Lgate2 of the PWM controller 20, and the function pin S2 of the dual transistor 200 is grounded. That is, the PWM controller 20 supplies power to the CPU 900 through the function pins S1 / D2 of the dual transistor 200 and the inductor L20 .

At this time, there is only one line between the dual transistor 100 and the dual transistor 200 , that is, the line connecting the function pin G2 of the dual transistor 200 to the second low-pass driving pin Lgate2 of the PWM controller 20 . A large space is not needed to lay out the multi-phase power supply circuit, which saves space.

Claims (4)

1. A package structure of a double transistor, comprising a body and first to fifth function pins, the first to third function pins constitute the gate, drain and source of the first transistor in the double transistor The third to fifth function pins constitute the drain, gate and source of the second transistor in the dual transistor; the first and second function pins are arranged on the first side of the body The third and fourth function pins are arranged on the second side relative to the first side of the body, and the fifth function pin is arranged on the bottom of the body. 2. The package structure of dual transistors according to claim 1, characterized in that: the number of the second function pins is four, and three of the second function pins are arranged on the first side of the body , and the other second function pin is set at the bottom of the body. 3 . The package structure of dual transistors according to claim 2 , wherein there are three third function pins, all of which are arranged on the second side of the body. 4 . 4. A power supply circuit using a package structure of dual transistors as claimed in claim 1, characterized in that: in the wiring area of the power supply circuit, the dual transistors are arranged between a pulse width modulation controller and an inductor, The pulse width modulation controller supplies power to a central processing unit through the dual transistor and the inductor, the pulse width modulation controller is close to the first side of the dual transistor body, and the first end of the inductor is close to The second side of the dual-transistor body; the first functional pin of the dual-transistor is connected to the first high-pass drive pin of the pulse width modulation controller, and the second functional pin of the dual-transistor is connected to a A voltage source, the third function pin of the dual transistor is connected to the first end of the inductor, and the fourth function pin of the dual transistor is connected to the first low-pass drive pin of the pulse width modulation controller, so The fifth function pin of the dual transistor is grounded, and the second end of the inductor is connected to the central processing unit.