CN104124240A - stacked integrated circuit system - Google Patents

Abstract

A stacked integrated circuit system includes a first chip having a first average pattern density and including memory cells, a second chip having a second average pattern density and including logic circuitry and a functional unit for the memory cells, and a plurality of through silicon vias in one of the first and second chips to electrically connect the first and second chips, wherein the memory cells of the first chip and the logic circuitry of the second chip are designed to be used together to achieve a complete memory function, wherein the first average pattern density is higher than the second average pattern density.

Description

stacked integrated circuit system

technical field

The invention relates to a stacked integrated circuit system, in particular to a stacked integrated circuit system with through-silicon holes.

Background technique

In order to save valuable layout space or increase the efficiency of interconnection, multiple integrated circuit (IC) chips can be stacked together to form an IC package structure. To achieve this, a three-dimensional (3D) stack packaging technique may be used to package multiple integrated circuit chips together. This three-dimensional (3D) stack packaging technology is widely used in through-silicon vias (TSVs). Through-silicon via (TSV) is a vertical conductive via that can completely penetrate a silicon wafer, silicon plate, substrate or chip made of any material. Nowadays, 3D integrated circuits (3DICs) are widely used in many fields such as memory stacks, image sensor chips, and so on.

Although TSV has many advantages, it also brings many challenges to integrated circuits. For example, its huge size (100 times or more larger than conventional transistors) wastes a lot of layout space compared to its surrounding neighbors such as transistors and interconnects. The more space it wastes, the larger the chip becomes. Today, all electronic devices are in a race to shrink, so it is not wise to waste space. Therefore, it is necessary to strive for and save the space wasted by TSVs as much as possible.

Contents of the invention

The present invention relates to a stacked integrated circuit system comprising: a first chip having a first average pattern density and including memory cells; a second chip having a second average pattern density and including logic circuits for the memory cells and a functional unit and a plurality of through-silicon vias located in one of the first chip and the second chip to electrically connect the first chip and the second chip, wherein the memory cell of the first chip and the logic of the second chip Circuits are designed to be used together to achieve full memory function, wherein the first average pattern density is higher than the second average pattern density.

A stacked integrated circuit system is provided, comprising: a first chip having a memory cell; a second chip having a first portion of a logic circuit for the memory cell; a third chip having a second portion of the logic circuit for the memory cell and a plurality of through-silicon vias located in one of the first chip, the second chip, and the third chip to electrically connect the first chip, the second chip, and the third chip, wherein the memory of the first chip The cell, the first part of the logic circuit of the second chip and the second part of the logic circuit of the third chip are designed to be used together to achieve a complete memory function.

A stacked integrated circuit system is provided, comprising: a first chip including only analog circuits; a second chip including only digital circuits; a plurality of through-silicon vias located in one of the first chip and the second chip to electrically connect the The first chip and the second chip, wherein the analog circuit of the first chip and the digital circuit of the second chip are designed to be used together to achieve complete functions.

Description of drawings

FIG. 1 shows a schematic layout plan of a conventional memory array according to the prior art;

2 shows a schematic cross-sectional view of a stacked integrated circuit (IC) system according to one embodiment of the present invention;

FIG. 3 shows an overview of the layout of two chips before stacking them together according to an embodiment of the present invention;

FIG. 4 shows an overview of the layout of two chips before stacking them together according to another embodiment of the present invention;

Figure 5 shows a cross-sectional view of a transistor level of an integrated circuit;

Figure 6 shows a schematic cross-sectional view of the transistor level and interconnection level of an integrated circuit;

FIG. 7 shows a schematic cross-sectional view of a stacked integrated circuit (IC) system according to another embodiment of the present invention.

Detailed ways

The preferred embodiments of the present invention will be described in detail below. For example, all components, component sub-parts, structures, materials, configurations, etc. described herein can be arbitrarily matched into new embodiments without following the order of description or the embodiments to which they belong. , these embodiments should belong to the protection category of the present invention. After reading the present invention, those skilled in the art should be able to make some changes and modifications to the above-mentioned components, sub-components, structures, materials, configurations, etc. without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of patent protection shall be defined by the appended claims of the present claims, and these changes and modifications shall fall within the claims of the present invention.

There are many embodiments and illustrations of the present invention, in order to avoid confusion, similar components are indicated by the same or similar symbols. The diagrams are intended to convey the concept and spirit of the present invention, so the distances, sizes, proportions, shapes, connections, etc. shown in the diagrams are all schematic rather than actual, and all distances that can achieve the same function or result in the same way , size, proportion, shape, connection relationship, etc. can all be adopted as equivalents.

Please refer to FIG. 1 , which shows a schematic layout plan of a conventional memory block in the prior art. In the center of the block are a plurality of memory arrays and a plurality of sense amplifiers adjacent to the memory arrays. Each memory array includes hundreds or thousands of memory cells such as static random access memory cells or static random access memory cells, and each static random access memory cell or dynamic random access memory cell includes at least one transistor. Logic circuits such as column decoders, buffers and input/output (I/O) are arranged in the peripheral area of the memory block. A memory chip may contain hundreds or thousands of such memory blocks.

In a single die (or chip), the pattern density, line width plus spacing, and the number of interconnect layers depend on the complexity of the circuit, the generation of the manufacturing process, the layout method used, and the required performance. . In a die (or chip) with a memory array and a logic circuit area, most of the places with the highest pattern density and the smallest line width plus spacing appear in the memory array. Therefore, using the same manufacturing process to manufacture the memory array and the logic circuit area shown in Figure 1 often leads to problems such as uneven thickness, uneven critical dimension (CD), and uneven dopant distribution, resulting in low yield. In addition, in order to manufacture a memory array with higher pattern density and smaller line width and pitch, it is necessary to use higher-precision process control and better-capable machine equipment, thus increasing the cost. In addition, memory cells such as static random access memory cells or dynamic random access memory cells typically require fewer interconnect layers than logic circuits. Interconnects can be thought of as the streets and highways of integrated circuits (ICs), connecting the components in an IC to function as a whole and connecting the IC to the outside world; adjacent layers of interconnects are usually positive to each other pay. Although interconnects are very important for integrated circuits, too many layers of interconnects can cause certain problems such as high parasitic capacitance that slows down the speed of the chip, crosstalk that affects the accuracy of signal reading, and heat dissipation. Therefore, a solution is needed to solve the above problems.

Referring now to FIG. 2, there is shown a schematic cross-sectional view of a stacked integrated circuit (IC) system in accordance with one embodiment of the present invention. In FIG. 2 , chip 1 and chip 2 are stacked together and electrically connected to each other by using through-silicon via (TSV) 100 and micro-bump/bump 200 . Chip 1 and chip-on-board integrated circuits are designed to be used together for full memory functionality, ie, either chip 1 or chip 2 alone cannot properly perform the memory function. In an embodiment shown in FIG. 3, chip 1 may carry all memory cells such as static random access memory cells or dynamic random access memory cells, and chip 2 may carry all logic circuits such as sense amplifiers, rows of regions Decoders, Column Decoders for Areas, Row Decoders for All Areas, Column Decoders for All Areas, Buffers and I/O. Moreover, the chip 2 is not only loaded with a logic circuit for controlling the chip 1 and used in common with the chip 1, but the chip 2 is also loaded with another complete functional unit such as a central processing unit (CPU), a graphics processing unit (GPU), etc. ), cooling unit, or basic input/output system (BIOS). In many prior art, the memory cell and its logic circuit are disposed in the same chip and another complete function such as the central processing unit is disposed in another chip. It should be noted that each dynamic random access memory cell (DRAM) includes at least one transistor and at least one capacitor (whether trench type or stack type capacitor), and each static random access memory cell (SRAM) includes data transistors (taking 6T SRAM as an example, six transistors), and there will be more than one million, tens of millions of these memory cells tightly arranged together in the chip 1.

In another example of the present invention shown in FIG. 4 , since the sense amplifier is more susceptible to noise than the decoder and I/O, the sense amplifier and the memory cells are disposed in the chip 1 . Not only that, the complete functional unit in the last embodiment is divided into two parts, namely the first part and the second part. The first part and the memory cells and the sense amplifier are arranged in the chip 1 , and the logic circuits used for the second part and the memory cells are arranged in the chip 2 .

Referring now to FIG. 5, a cross-sectional view of a transistor level of an integrated circuit is shown. As shown in FIG. 5 , it is assumed that both chip 1 and chip 2 have a plurality of transistors 20 formed on the substrate 10 and each transistor 20 has at least one gate electrode 22 and source/drain (S/D) 24 . The integrated circuit on the chip 1 has the first average pattern density and the first minimum pattern line width plus spacing for the gate electrode 22 (the gate electrode 22 will be omitted later, referred to as the first average pattern density and the first minimum pattern line width plus spacing respectively. ). The volume circuit on the chip 2 has a second average pattern density and a second minimum pattern line width plus spacing for the gate electrode 22 (the gate electrode 22 will be omitted later, referred to as the second average pattern density and the second minimum pattern line width plus spacing respectively. ). The average pattern density of the gate electrodes 22 is defined as the area occupied by all the gate electrodes 22 divided by the area of the entire chip. The minimum pattern line width plus space of the gate electrodes 22 is defined as the minimum line width plus space of the gate electrodes that can be found throughout the chip. The first average pattern density is different from the second average pattern density, and the first minimum pattern linewidth plus spacing is different from the second minimum pattern linewidth plus spacing.

Next, please refer to FIG. 6 , which shows a schematic cross-sectional view of the transistor level and the interconnection level of the integrated circuit. FIG. 6 provides a simple relationship between the substrate 10, the transistor 20, and the first-level metal (M1) to the sixth-level metal (M6). As shown in FIG. 6, the contact couples the source/drain (S/D) 24 to the first level metal (M1), the first via (V1) couples the first level metal (M1) to the second Metal (M2), second via (V2) couples second metal (M2) to third metal (M3), third via (V3) couples third metal (M3) to fourth Level metal (M4), fourth via (V4) couples fourth level metal (M4) to fifth level metal (M5), fifth via (V5) couples fifth level metal (M5) to sixth Layer metal (M6), so the number of layers of the interconnection layer shown in Figure 6 is 6 based on the highest metal layer (ie, the sixth metal layer). The integrated circuit on chip 1 has a first number of interconnect layers, and the integrated circuit on chip 2 has a second number of interconnect layers. The first number of layers is different from the second number of layers.

In the preferred embodiment shown in Figure 2, the first average pattern density is higher than the second average pattern density, the first minimum pattern line width plus spacing is smaller than the second minimum pattern line width plus spacing, and the first layer number is less than The second layer.

Although in FIG. 2 , the size of the chip 1 is larger than that of the chip 2 , the sizes of the chip 1 and the chip 2 are not limited thereto. For example, chip 1 and chip 2 may have the same size. Also, in FIG. 2 , the chip 2 is placed on the chip 1 and provided with the TSV 100 and the micro-bump/bump 200 , but the present invention is not limited thereto. The TSVs 100 and the microbumps/bumps 200 can also be disposed in/on the chip 1 , and the chip 1 can be disposed under the chip 2 .

Referring now to FIG. 7, a schematic cross-sectional view of a stacked integrated circuit (IC) system according to another embodiment of the present invention is shown. The embodiment of FIG. 7 is similar to the embodiment of FIG. 2, but the embodiment of FIG. 7 has a chip 3 arranged on the chip 1, and the chip 3 uses the through-silicon via 100' and the chip 3 in/on the chip 3. Microbumps/bumps 200 ′ are connected to the chip 1 . Chip 1, Chip 2, and Chip 3 carry integrated circuits that are designed to be used together to perform the full memory function, that is, only one or both of Chip 1, Chip 2, and Chip 3 cannot properly perform the intended function. function. For example, chip 1 can carry all memory cells such as static random access memory cells or dynamic random access memory cells and sense amplifiers, and chip 2 can carry part of logic circuits such as area column decoders and area row decoders. chip 3 can carry the remaining logic circuits such as input/output, global decoder and static protection circuit. The integrated circuit on the chip 3 has a third average pattern density and a third minimum pattern line width plus spacing for the gate electrode 22, and the chip 3 has a third number of interconnection layers. The third average pattern density is different from the second and first average pattern density; the third minimum pattern line width plus spacing is different from the second and first minimum pattern line width plus spacing; the third layer number is different from the first and second layers.

In a preferred embodiment shown in FIG. 7 , the first average pattern density is the highest, the second average pattern density is between the first average pattern density and the third average pattern density, and the third average pattern density is the lowest. The ranking order for the smallest pattern width plus spacing is the same as the average pattern density. As for the number of layers in the inline network, the number of the first layer should be the lowest, but the number of the second layer and the third layer can be the same or different.

Similar to the embodiment of Fig. 2, the size of the chip should not be limited. For example, chip 2 and chip 3 may have the same size. Also, in FIG. 7, chip 2 and chip 3 are located on chip 1 and are provided with TSVs 100/100' and micro bumps/bumps 200/200', but the present invention is not limited thereto. TSVs 100/100' and microbumps/bumps 200/200' may also be disposed in/on chip 1 and chip 1 may be located below chip 2 and chip 3.

Alternatively, chip 3 in FIG. 7 is a silicon interposer without active devices disposed thereon. In this case, Chip 1 and Chip 2 are used together to implement complete memory functions and central/graphics processing functions, but Chip 3 only has an interface function to connect Chips 1 and 2 and connect them to the outside world. At this time, the chip 3 may include TSVs, micro-bumps/bumps, interconnects, passive components, and the like. Since the chip 3 does not have active components such as transistors, it does not have an average pattern density, nor does it have a minimum pattern line width plus spacing, and the number of interconnection layers is not many.

In this way, the present invention can apply different process generations to different chips, thereby improving uniformity within each chip and reducing cost. In addition, the present invention can customize the number of internal connection layers for each chip, so more sensitive memory cells such as static random access memory cells or dynamic random access memory cells are less likely to be disturbed by noise. It is worth mentioning that sometimes analog circuits and digital circuits may have very different layout densities, noise margins, and number of interconnect layers, so the principles of the present invention can be applied to integrated circuit systems including analog circuits and digital circuits. By applying the principle of the present invention, an analog circuit can be arranged on one chip and a digital circuit can be arranged on another chip, and the two chips can be electrically connected by using TSVs to implement a series of complete functions that cannot be achieved by separate chips. A chip with analog circuitry and another chip with digital circuitry may have a different average pattern density and/or a different minimum pattern line width plus spacing and/or a different number of interconnect layers for gate electrodes.

The above-mentioned embodiments are only examples for the convenience of description, and even if they are arbitrarily modified by those skilled in the art, they will not depart from the scope of protection as claimed in the claims.

Claims (10)

1. A stacked integrated circuit system comprising: a first chip having a first average pattern density and including memory cells; a second chip having a second average pattern density and including a logic circuit and a functional unit of the memory cell; and a plurality of TSVs located in one of the first chip and the second chip to electrically connect the first chip and the second chip, Wherein the memory cell of the first chip and the logic circuit of the second chip are designed to be used together to achieve a complete memory function, Wherein the first average pattern density is higher than the second average pattern density. 2. The stacked integrated circuit system as claimed in claim 1, wherein the memory cell is a dynamic random access memory cell (DRAM) or a static random access memory cell (SRAM). 3. The stacked integrated circuit system as claimed in claim 2, wherein the first chip further comprises a sense amplifier for memory cells. 4. The stack integrated circuit system as claimed in claim 3, wherein the logic circuit comprises a region row decoder, a region column decoder, a whole region row decoder, a whole region column decoder, a buffer with input/output. 5. The stacked integrated circuit system according to claim 2, wherein the logic circuit comprises a sense amplifier, an area row decoder, an area column decoder, an entire area row decoder, an entire area column decoder buffers, and input/output. 6. The stacked integrated circuit system as claimed in claim 1, wherein the functional unit comprises a central processing unit (CPU), a graphics processing unit (GPU), a cooling unit or a basic input/output system (BIOS). 7. The stacked integrated circuit system of claim 1, wherein the first chip has a first number of interconnect layers and the second chip has a second number of interconnect layers and the first layer number is less than the second layer number. 8. The stacked integrated circuit system of claim 1, wherein a size of the first chip is larger than a size of the second chip. 9. A stacked integrated circuit system comprising: a first chip having memory cells; a second chip having a first portion of logic circuitry for the memory cell; a third chip having a second portion of logic circuitry for the memory cell; and a plurality of TSVs located in one of the first chip, the second chip and the third chip to electrically connect the first chip, the second chip and the third chip, The memory cell of the first chip, the first part of the logic circuit of the second chip and the second part of the logic circuit of the third chip are designed to be used together to achieve a complete memory function. 10. A stacked integrated circuit system comprising: The first chip, containing only analog circuits; a second chip containing only digital circuits; and a plurality of TSVs located in one of the first chip and the second chip to electrically connect the first chip and the second chip, Wherein the analog circuit of the first chip and the digital circuit of the second chip are designed to be used together to achieve complete functions.