CN104036812B - Comparator with improved time constant - Google Patents
Comparator with improved time constant Download PDFInfo
- Publication number
- CN104036812B CN104036812B CN201310067310.0A CN201310067310A CN104036812B CN 104036812 B CN104036812 B CN 104036812B CN 201310067310 A CN201310067310 A CN 201310067310A CN 104036812 B CN104036812 B CN 104036812B
- Authority
- CN
- China
- Prior art keywords
- circuit
- phase inverter
- output end
- coupled
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Amplifiers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention provides a comparator with an improved time constant and an apparatus used for comparing input of differential input signals. The apparatus comprises a CMOS read amplifier (which is provided with a first input terminal, a second input terminal, a first output terminal and a second output terminal), a first output circuit (which is provided with a first load capacitor), a second output circuit (which is provided with a second load capacitor) and an isolation circuit. The isolation circuit is connected with and arranged between the first output terminal of the CMOS read amplifier and the first output circuit and connected with and arranged between the second output terminal of the CMOS read amplifier and the second output circuit. The isolation circuit isolates the first and second load capacitors from the CMOS read amplifier.
Description
Technical field
This invention relates generally to comparator, and relate more specifically to based on the comparator of read-out amplifier.
Background technology
Comparator is nonlinear circuit, is commonly used for detecting the mark difference between two or more signals, and
Jing is used for analytic signal, such as memory and analog-digital converter in numerous applications（ADC）In.For example, illustrate that reading is put in Fig. 1
Big device 50（For example, it can act as the comparator in memory application）.Specifically, this read-out amplifier 50 is used as regeneration
The cmos circuit of clock comparator.It generally comprises the PMOS of cross-join and nmos pass transistor Q2 to Q5, nmos pass transistor Q7
With the Differential Input pair of Q8, and clock circuit（It generally includes PMOS transistor Q1 and Q6 and nmos pass transistor Q9）.When this
Clock signal clk is logic low potential or when " 0 ", and output end R and S can be precharged to the electricity on power supply rail VDD
Pressure, when clock signal clk is logic high potential or when " 1 ", then terminal R and S output valve according in input INM
Parse with the input value of INP.If the voltage on input INP is more than the voltage on terminal INM, then terminal S and R respectively by
Resolve to " 1 " and " 0 "；Conversely, when the voltage on the input on INP is less than the voltage on terminal INM, terminal S and R difference
Resolve to " 0 " and " 1 ".In addition, transistor Q9 according to clock signal clk by differential pair Q7 and Q8 and ground potential（Power supply rail）Connection
Connect and disconnect.
It is its " time constant " for describing the behavioural trait of read-out amplifier 50, it indicates that the propagation in input amplitude is prolonged
Late（Or " clock to Q postpones "）Correlation.It is less generally, due to the magnitude of the difference of voltage between terminal INM and INP,
Therefore there is longer delay for parsing the value on terminal R and S.This relation can be expressed as below：
(1)TPROP=max(tFIXED,tFIXED-τ*ln(|VIN|))
Wherein TPROPIt is propagation delay, tFIXEDBe with（For example）Voltage on change in process, temperature and power supply rail VDD has
The fixed comparator of pass postpones, and τ is time constant, and | VIN| it is the value for holding the voltage difference between INM and INP（It leads to
It is often differential signal）.Generally, equation（1）Suitable for about 100mV or the signal of less magnitude, once and the difference foot
It is enough big, propagation delay TPROPIt is saturated to fixed comparator and postpones tFIXED.Therefore, for some applications it is desirable to reduce this propagation
Postpone TPROP, so as to quickly parse comparative result for value signal by a narrow margin.
Some examples of conventional system are：U.S. Patent number 4,274,013；U.S. Patent number 4,604,533；United States Patent (USP)
Numbers 5,627,789；U.S. Patent number 5,901,088；U.S. Patent number 7,688,125；With Payandehnia's et al.
“A4mW3-tap10Gb/s Decision Feedback Equalizer”2011IEEE54th International
Midwest Symposium on Circuits and Systems(MWSCAS),September23,2011,pp.1-4。
The content of the invention
Therefore, The embodiment provides device.The device includes CMOS read-out amplifiers, and it has the first input
End, the second input, the first output end and the second output end；First output circuit, with the first load capacitance；Second output
Circuit, with the second load capacitance；And isolation circuit, it is connected in the first output end of CMOS read-out amplifiers and first defeated
Go out between circuit, and the second output of its second output end for being connected in CMOS read-out amplifiers and CMOS read-out amplifiers
Between end, wherein isolation circuit isolates the first and second load capacitances with CMOS read-out amplifiers.
Embodiments in accordance with the present invention, the first and second output circuits further include respectively the first and second phase inverters.
Embodiments in accordance with the present invention, CMOS read-out amplifiers are by clock signal control, and wherein the isolation circuit is entered
One step is included：Pre-charge circuit, it is coupled to the first and second phase inverters, and by clock signal control；With the first isolation
Element, it is connected between the first output end of CMOS read-out amplifiers and the first phase inverter；With the second isolation element, its quilt
It is connected between the second output end of CMOS read-out amplifiers and the second phase inverter.
Embodiments in accordance with the present invention, the pre-charge circuit is further included：First MOS transistor, it drains at it
It is coupled to the first phase inverter；With the second MOS transistor, it is coupled to the second phase inverter in its drain electrode.
Embodiments in accordance with the present invention, the first and second isolation elements respectively, further include the first and second resistance
Device.
Embodiments in accordance with the present invention, the clock signal further includes the first clock signal, and wherein first and the
Two isolation elements further include respectively the first and second switches controlled by second clock signal, and by clock signal reality
Exist between the activation of existing CMOS read-out amplifiers and the activation of the first and second switches realized by second clock signal non-
Overlaid periodic.
Embodiments in accordance with the present invention, the read-out amplifier is further included：Clock circuit, it is configured so as to receive
One clock signal；Differential input transistor pair, it is configured so as to receive differential input signal；First pair of cross-join crystal
Pipe, it is connected to differential input transistor pair；With second pair of cross-join transistor, it is connected to first pair of cross-join crystal
Pipe.
Embodiments in accordance with the present invention, there is provided device.The device is included：AFE(analog front end)（AFE）；Analog-digital converter
（ADC）, it is coupled to AFE, and wherein AFE has multiple dispensers（slicer）, and wherein each dispenser includes：CMOS
Read-out amplifier, it has first input end, the second input, the first output end and the second output end；First output circuit, tool
There is the first load capacitance；Second output circuit, it has the second load capacitance；Isolation circuit, it is connected in CMOS readings and puts
Between first output end and the first output circuit of big device, and its be connected in CMOS read-out amplifiers the second output end and
Between second output end of CMOS read-out amplifiers, wherein the first and second load capacitances and CMOS are read and are amplified by isolation circuit
Device is isolated；And decision zeedback equalizer（DFE）, it is coupled to ADC.
Embodiments in accordance with the present invention, there is provided device.The device includes serializer；Transmitter, it is coupled to the string
Row device；Communication media, it is coupled to the transmitter；Receiver, it has：AFE；ADC, it is coupled to AFE, wherein ADC
With multiple dispensers, and wherein each dispenser includes：Read-out amplifier, it has：First power supply rail；Second power supply
Track；First output end；Second output end；Cross-join PMOS transistor pair, it is defeated that each of which is all coupled to first and second
Go out and hold and be coupled to the first power supply rail；Cross-join nmos pass transistor pair, each of which is all coupled to first and second
Output end；Nmos pass transistor Differential Input pair, each of which is all connected to communication channel and cross-join nmos pass transistor pair；First
Clock nmos pass transistor, it is connected between the first power supply rail and the first output end, and it is when being configured so as to receive
Clock signal；Second clock nmos pass transistor, it is connected between the first power supply rail and the second output end, and it is configured
So as to receive clock signal；With the 3rd clock nmos pass transistor, it is connected in nmos pass transistor Differential Input pair and second and supplies
Between electric rail, and it is configured so as to receive clock signal；First output circuit, it has the first load capacitance；Second
Output circuit, it has the second load capacitance；Isolation circuit, it is connected in the first output end of read-out amplifier and first defeated
Go out between circuit, and it is connected between the second output end of read-out amplifier and the second output end of read-out amplifier,
Wherein isolation circuit isolates the first and second load capacitances with read-out amplifier；And DFE, it is coupled to ADC；With unstring
Device, it is coupled to DFE.
Embodiments in accordance with the present invention, isolation circuit is further included：Pre-charge circuit, it is coupled to first and second
Phase inverter, and by clock signal control；With the first isolation element, it is connected in the first output end of read-out amplifier and
Between one phase inverter；With the second isolation element, it is connected between the second output end of read-out amplifier and the second phase inverter.
Embodiments in accordance with the present invention, the pre-charge circuit is further included：First precharge PMOS transistor, its
Its drain electrode is coupled to the first phase inverter；With the second precharge PMOS transistor, it is coupled to the second phase inverter in its drain electrode.
In order to detailed description of the invention, the above-mentioned device for quite widely having summarized the present invention can be best understood from below
Part and technological merit.The present invention it is extra the characteristics of and advantage can be described below, which form the present invention claim
Theme.It should be appreciated by those skilled in the art that disclosed concept and specific embodiment can easily be utilized as repairing
The basis of the other structures for changing or being designed for carry out identical purpose of the invention.Those skilled in the art it should also be appreciated that this
A little equivalent constructions are without departing from the spirit and scope of the invention proposed in claim.
Description of the drawings
In order to more completely understand the present invention and its advantage, with reference now to the following description associated with accompanying drawing, wherein：
Fig. 1 is the diagram of the example of conventional cmos read-out amplifier；
Fig. 2 is the diagram of the example according to the system of embodiments of the invention；
Fig. 3 is the diagram of the example of at least a portion ADC of Fig. 2；
Figure 4 and 5 are the diagrams of the example of the dispenser of Fig. 3；With
Fig. 6 is the example of the sequential chart of the dispenser of Fig. 5.
Specific embodiment
With reference now to accompanying drawing, wherein for the sake of clarity the element is not necessarily drawn to scale and wherein in several figures
In be similar to or similar element indicated by same reference numbers.
As described above, expecting to reduce propagation delay T in some applicationsPROP.This can be complete by regulating time constant, τ
Into.The example of this application is the serializer/de-serializers that can be found out from Fig. 2 and 3（SERDES）Based on reading in system 100
The dispenser of amplifier.In operation, parallel data stream is converted to serial data stream by serializer 102.Then, this serial number
Pass through channel 106 according to device 104 is launched（It typically is communication media, such as twisted-pair feeder）It is transmitted into receiver 108.Then receiver
108 AFE(analog front end)（AFE）112 can recover signal from channel 106, and then the signal can be by ADC114（It is generally adopted
Dispenser 202-1 to 202-N, and it can be several ADC）Digitlization.Then DFE116 is filtered and equalized digitalization is believed
Number（That is, intersymbol interference or ISI are compensated）, and deserializer 110 makes the output parallelization from DFE116.In this system
In 100, dispenser 202-1 to 202-N using the comparator based on read-out amplifier so that dispenser can to benefit from the time normal
The adjustment of number τ.
Fig. 1 is returned to, timeconstantτ is relevant with electric capacity.Specifically, this constant, τ with divided by transistor Q2 to Q5 across electricity
Lead gmLoad capacitance CLOAD（That is, τ α CLOAD/gm）It is proportional.This load capacitance CLOADTypically read-out amplifier 50 is intrinsic
Or internal capacitance CINTWith external capacitive C on terminal R and SEXTSum.In order to reduce timeconstantτ, it should reduce load capacitance
CLOAD, and increase transconductance gm.Increase transconductance gmCan mean that transistor Q1 to Q9 should increase size, but the increasing of size
Plus limited, because internal capacitance CINTIt is proportional to the size of transistor Q1 to Q9.Therefore, transistor Q1 to Q9 is only increased
Size will not obtain the effect wanted, therefore dispenser 202-1 to 202-N is using the comparator based on read-out amplifier, its
Middle external capacitive CEXTWith internal capacitance CINTDisconnect or isolate, so as to load capacitance CLOADIt is approximately equal to internal capacitance CINT。
In the diagram it can be seen that the example of this dispenser 202-1 to 202-N（It is 202-A by label）.Such as this reality
Shown in example, external capacitive CEXTCome from output circuit（In this example it is generally made up of phase inverter 206 and 208）It is negative
Carry.Isolation circuit 204-A is connected between terminal R and S and phase inverter 206 and 208.This isolation circuit 204-A generally by
Pre-charge circuit（That is PMOS transistor Q10 and Q11）With resistor R1 and R2 composition.The pre-charge circuit（It is by clock signal
CLK is controlled）It is normally used for being pre-charged external capacitive C provided by phase inverter 206 and 208EXT, and resistor R1 and R2（Its
As isolation element）By external capacitive CEXTWith internal capacitance CINTIsolation.In addition, because transistor Q10 and Q11 are external capacitive
CEXTPrecharge is provided, so transistor Q1 and Q6 can reduce driving intensity（That is size）, this reduces internal capacitance CINTGo forward side by side
One step reduces timeconstantτ.
Figure 5 illustrates another example of dispenser 202-1 to 202-N（It is 202-B by label）.Dispenser 202-
B is replaced similar to dispenser 202-A except isolation circuit 204-A is isolated circuit 204-B.In isolation circuit 204-B, open
Close SW1 and SW2 and be adopted as isolation element.These switch SW1 and SW2 by clock signal clk ' control.As shown in fig. 6, raw
Into clock signal clk ', so as to the activation of the read-out amplifier 50 realized by clock signal clk and by clock signal clk ' it is real
There is non-overlapping period between SW1 and the activation of SW2 in existing switch.During these non-overlapping periods, isolate the external capacitive
CEXT, this allows timeconstantτ by internal capacitance CINTSetting.Output circuit（That is phase inverter 206 and 208）Time point after
（Once read-out amplifier 50 has parsed the value on terminal R and S）It is coupled to terminal R and S.
Due to using these dispensers 202-1 to 202-N, several advantages can be realized.First, the propagation delay of shortening permits
Perhaps dispenser 202-1 to 202-N runs at a relatively high speed（I.e. clock frequency CLK is higher）.Second, comparator can be reduced sub-
Stability.And the 3rd, improve the bit error rate (BER) of ADC114 and whole transceiver system（BER）.
Therefore by reference to some preferred embodiments description present invention of the present invention, it shall be noted that the disclosed embodiments reality
It is illustrative on border rather than limits, and in the various changes of middle expection disclosed above, modification, change and replacement,
And some devices of the present invention can be adopted in some cases without accordingly using other devices.Therefore, it is suitable
It is that claim is widely interpreted and consistent with protection scope of the present invention.
Claims (10)
1. a kind of device, comprising：
CMOS read-out amplifiers, it has first input end, the second input, the first output end and the second output end；
First output circuit, it has the first load capacitance；
Second output circuit, it has the second load capacitance；With
Isolation circuit, it is connected between the first output end of the CMOS read-out amplifiers and first output circuit,
And it is connected between the second output end of the CMOS read-out amplifiers and second output circuit, wherein it is described every
First load capacitance and second load capacitance are isolated with the CMOS read-out amplifiers from circuit；
Wherein described first and second output circuit respectively, further includes the first phase inverter and the second phase inverter, wherein described
CMOS read-out amplifiers are controlled by the first clock signal, and wherein described isolation circuit is further included：
Pre-charge circuit, it is coupled to first phase inverter and second phase inverter, and it is by first clock
Signal is controlled；With
First isolation element, its be connected in the first output end of the CMOS read-out amplifiers and first phase inverter it
Between；With
Second isolation element, its be connected in the second output end of the CMOS read-out amplifiers and second phase inverter it
Between；
Wherein described pre-charge circuit is further included：
First MOS transistor, its drain electrode is coupled to first phase inverter；With
Second MOS transistor, its drain electrode is coupled to second phase inverter；
Wherein described first isolation element and second isolation element further include respectively what is controlled by second clock signal
First switch and second switch, and wherein in the activation of the CMOS read-out amplifiers realized by first clock signal
There is non-overlapping period and the first switch by second clock signal realization and the activation of the second switch between.
2. a kind of device, comprising：
CMOS read-out amplifiers, it has first input end, the second input, the first output end and the second output end；
First output circuit, it has the first load capacitance；
Second output circuit, it has the second load capacitance；With
Isolation circuit, it is connected between the first output end of the CMOS read-out amplifiers and first output circuit,
And it is connected between the second output end of the CMOS read-out amplifiers and second output circuit, wherein it is described every
First load capacitance and second load capacitance are isolated with the CMOS read-out amplifiers from circuit；
Wherein described first and second output circuit respectively, further includes the first phase inverter and the second phase inverter, wherein described
CMOS read-out amplifiers are by clock signal control, and wherein described isolation circuit is further included：
Pre-charge circuit, it is coupled to first phase inverter and second phase inverter, and it is by the clock signal
Control；With
First isolation element, its be connected in the first output end of the CMOS read-out amplifiers and first phase inverter it
Between；With
Second isolation element, its be connected in the second output end of the CMOS read-out amplifiers and second phase inverter it
Between,
Wherein described pre-charge circuit is further included：
First MOS transistor, its drain electrode is coupled to first phase inverter；With
Second MOS transistor, its drain electrode is coupled to second phase inverter；
Wherein described read-out amplifier is further included：
Clock circuit, it is configured so as to receive the clock signal；
Differential input transistor pair, it is configured so as to receive differential input signal；
First pair of cross-join transistor, it is coupled to the differential input transistor pair；With
Second pair of cross-join transistor, it is coupled to first pair of cross-join transistor.
3. a kind of device, comprising：
AFE(analog front end) is AFE；
Analog-digital converter is ADC, and it is coupled to the AFE, wherein the ADC has multiple dispensers, and wherein each
Dispenser includes：
CMOS read-out amplifiers, it has first input end, the second input, the first output end and the second output end；
First output circuit, it has the first load capacitance；
Second output circuit, it has the second load capacitance；
Isolation circuit, it is connected between the first output end of the CMOS read-out amplifiers and first output circuit,
And it is connected between the second output end of the CMOS read-out amplifiers and second output circuit, wherein it is described every
First load capacitance and second load capacitance are isolated with the CMOS read-out amplifiers from circuit；With
Decision zeedback equalizer is DFE, and it is coupled to the ADC；
Wherein described first output circuit and second output circuit are further anti-phase comprising the first phase inverter and second respectively
Device, wherein the CMOS read-out amplifiers are controlled by the first clock signal, and wherein described isolation circuit is further included：
Pre-charge circuit, it is coupled to first phase inverter and second phase inverter, and it is by first clock
Signal is controlled；With
First isolation element, its be connected in the first output end of the CMOS read-out amplifiers and first phase inverter it
Between；With
Second isolation element, its be connected in the second output end of the CMOS read-out amplifiers and second phase inverter it
Between；
Wherein described pre-charge circuit is further included：
First MOS transistor, its drain electrode is coupled to first phase inverter；With
Second MOS transistor, its drain electrode is coupled to second phase inverter,
Wherein described first isolation element and second isolation element further include respectively what is controlled by second clock signal
First switch and second switch, and wherein in the activation of the CMOS read-out amplifiers realized by first clock signal
There is non-overlapping period and the first switch by second clock signal realization and the activation of the second switch between.
4. a kind of device, comprising：
AFE(analog front end) is AFE；
Analog-digital converter is ADC, and it is coupled to the AFE, wherein the ADC has multiple dispensers, and wherein each
Dispenser includes：
CMOS read-out amplifiers, it has first input end, the second input, the first output end and the second output end；
First output circuit, it has the first load capacitance；
Second output circuit, it has the second load capacitance；
Isolation circuit, it is connected between the first output end of the CMOS read-out amplifiers and first output circuit,
And it is connected between the second output end of the CMOS read-out amplifiers and second output circuit, wherein it is described every
First load capacitance and second load capacitance are isolated with the CMOS read-out amplifiers from circuit；With
Decision zeedback equalizer is DFE, and it is coupled to the ADC；
Wherein described first output circuit and second output circuit are further anti-phase comprising the first phase inverter and second respectively
Device, wherein the CMOS read-out amplifiers are by clock signal control, and wherein described isolation circuit is further included：
Pre-charge circuit, it is coupled to first phase inverter and second phase inverter, and it is by the clock signal
Control；With
First isolation element, its be connected in the first output end of the CMOS read-out amplifiers and first phase inverter it
Between；With
Second isolation element, its be connected in the second output end of the CMOS read-out amplifiers and second phase inverter it
Between,
Wherein described pre-charge circuit is further included：
First MOS transistor, its drain electrode is coupled to first phase inverter；With
Second MOS transistor, its drain electrode is coupled to second phase inverter；
Wherein described read-out amplifier is further included：
Clock circuit, it is configured so as to receive the clock signal；
Differential input transistor pair, it is configured so as to receive differential input signal；
First pair of cross-join transistor, it is coupled to the differential input transistor pair；With
Second pair of cross-join transistor, it is coupled to first pair of cross-join transistor.
5. a kind of device, comprising：
Serializer；
Transmitter, it is coupled to the serializer；
Communication media, it is coupled to the transmitter；
Receiver, it has：
AFE(analog front end) is AFE；
Analog-digital converter is ADC, and it is coupled to the AFE, wherein the ADC has multiple dispensers, and wherein each
Dispenser includes：
Read-out amplifier, has：
First power supply rail；
Second power supply rail；
First output end；
Second output end；
Cross-join PMOS transistor pair, each of which is all coupled to first output end and second output end and quilt
It is connected to first power supply rail；
Cross-join nmos pass transistor pair, each of which is all coupled to first output end and second output end；
Differential Input nmos pass transistor pair, each of which is all coupled to the communication media and the cross-join nmos pass transistor
It is right；
First clock nmos pass transistor, it is connected between first power supply rail and first output end, and its
It is configured so as to receive the first clock signal；
Second clock nmos pass transistor, it is connected between first power supply rail and second output end, and its
It is configured so as to receive first clock signal；With
3rd clock nmos pass transistor, its be connected in the Differential Input nmos pass transistor pair and second power supply rail it
Between, and it is configured so as to receive first clock signal；
First output circuit, it has the first load capacitance；
Second output circuit, it has the second load capacitance；
Isolation circuit, it is connected between the first output end of the read-out amplifier and first output circuit, and
It is connected between the second output end of the read-out amplifier and second output circuit, wherein the isolation circuit will
First load capacitance and second load capacitance are isolated with the read-out amplifier；With
Decision zeedback equalizer is DFE, and it is coupled to the ADC；With
Deserializer, it is coupled to the DFE.
6. device according to claim 5, wherein first output circuit and second output circuit enter respectively
Step includes the first phase inverter and the second phase inverter.
7. device according to claim 6, wherein the isolation circuit is further included：
Pre-charge circuit, it is coupled to first phase inverter and second phase inverter, and it is by first clock
Signal is controlled；With
First isolation element, it is connected between the first output end of the read-out amplifier and first phase inverter；With
Second isolation element, it is connected between the second output end of the read-out amplifier and second phase inverter.
8. device according to claim 7, wherein the pre-charge circuit is further included：
First precharge PMOS transistor, its drain electrode is coupled to first phase inverter；With
Second precharge PMOS transistor, its drain electrode is coupled to second phase inverter.
9. device according to claim 8, wherein first isolation element and second isolation element enter respectively
Step includes first resistor device and second resistance device.
10. device according to claim 8, wherein first isolation element and second isolation element enter respectively
Step includes the first switch and second switch controlled by second clock signal, and is wherein being realized by first clock signal
The read-out amplifier activation and the first switch realized by the second clock signal and the second switch
There is non-overlapping period between activation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310067310.0A CN104036812B (en) | 2013-03-04 | 2013-03-04 | Comparator with improved time constant |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310067310.0A CN104036812B (en) | 2013-03-04 | 2013-03-04 | Comparator with improved time constant |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104036812A CN104036812A (en) | 2014-09-10 |
| CN104036812B true CN104036812B (en) | 2017-04-12 |
Family
ID=51467553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310067310.0A Active CN104036812B (en) | 2013-03-04 | 2013-03-04 | Comparator with improved time constant |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104036812B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI815373B (en) * | 2021-05-24 | 2023-09-11 | 聯發科技股份有限公司 | Dynamic comparator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937702A (en) * | 2010-09-10 | 2011-01-05 | 上海宏力半导体制造有限公司 | Read amplifier with bit line capacitance detection |
| CN1774766B (en) * | 2003-04-11 | 2012-07-04 | 飞思卡尔半导体公司 | Memory device with sense amplifier and self-timed latch and operation method |
| CN102595063A (en) * | 2011-01-10 | 2012-07-18 | 三星电子株式会社 | Sense amplifier including negative capacitance circuit and apparatuses including same |
| US8258819B2 (en) * | 2010-10-25 | 2012-09-04 | Texas Instruments Incorporated | Latched comparator having isolation inductors |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4928290B2 (en) * | 2007-01-31 | 2012-05-09 | キヤノン株式会社 | Differential signal comparator |
| US20130002350A1 (en) * | 2011-06-29 | 2013-01-03 | Globalfoundries Inc. | Differential Comparator |
| US9071243B2 (en) * | 2011-06-30 | 2015-06-30 | Silicon Image, Inc. | Single ended configurable multi-mode driver |
-
2013
- 2013-03-04 CN CN201310067310.0A patent/CN104036812B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1774766B (en) * | 2003-04-11 | 2012-07-04 | 飞思卡尔半导体公司 | Memory device with sense amplifier and self-timed latch and operation method |
| CN101937702A (en) * | 2010-09-10 | 2011-01-05 | 上海宏力半导体制造有限公司 | Read amplifier with bit line capacitance detection |
| US8258819B2 (en) * | 2010-10-25 | 2012-09-04 | Texas Instruments Incorporated | Latched comparator having isolation inductors |
| CN102595063A (en) * | 2011-01-10 | 2012-07-18 | 三星电子株式会社 | Sense amplifier including negative capacitance circuit and apparatuses including same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI815373B (en) * | 2021-05-24 | 2023-09-11 | 聯發科技股份有限公司 | Dynamic comparator |
| US11777482B2 (en) | 2021-05-24 | 2023-10-03 | Mediatek Inc. | Gain-boosted comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104036812A (en) | 2014-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8624632B2 (en) | Sense amplifier-type latch circuits with static bias current for enhanced operating frequency | |
| US8604838B2 (en) | Comparator with improved time constant | |
| US7868663B2 (en) | Receiver circuit for use in a semiconductor integrated circuit | |
| KR100801055B1 (en) | Data receiver and semiconductor device having same | |
| KR102378304B1 (en) | Device with data receiver with real time clock decoding decision feedback equalizer | |
| TWI558135B (en) | Power and area efficient receiver equalization architecture with relaxed dfe timing constraint | |
| US20150312060A1 (en) | Decision feedback equalization slicer with enhanced latch sensitivity | |
| EP3238340B1 (en) | Linear equalizer with variable gain | |
| KR100945788B1 (en) | Data Receivers in Semiconductor Integrated Circuits | |
| KR100897282B1 (en) | Receiver circuit | |
| US10128965B1 (en) | Coupled inverter with auto-calibration | |
| WO2022095297A1 (en) | Decision feedback equalizer and data acquisition and correction method | |
| US8958501B2 (en) | Quasi-digital receiver for high speed SER-DES | |
| US7482843B2 (en) | Signal amplifier | |
| US20140159807A1 (en) | Multiple-clock, noise-immune slicer with offset cancellation and equalization inputs | |
| WO2023034332A1 (en) | Method and apparatus for low latency charge coupled decision feedback equalization | |
| US8878585B2 (en) | Slicer and method of operating the same | |
| CN104036812B (en) | Comparator with improved time constant | |
| US10715359B1 (en) | Decision feedback equalizer | |
| KR100873626B1 (en) | Data Receivers in Semiconductor Integrated Circuits | |
| US20180198413A1 (en) | Semiconductor integrated circuit, sensor reader, and sensor readout method | |
| Bae et al. | A 2-Gb/s CMOS integrating two-tap DFE receiver for four-drop single-ended signaling | |
| KR102777146B1 (en) | A analog front-end receiver and a electronic device including the same receiver | |
| US20240313708A1 (en) | Reduction of Charge Injection Noise in Sense Amplifiers of High-Speed Data Interfaces | |
| CN104917509A (en) | Data driving circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |