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CA2466153A1 - Integrated transistor/memory structures and a matrix-addressable array thereof - Google Patents

Integrated transistor/memory structures and a matrix-addressable array thereof Download PDF

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Publication number
CA2466153A1
CA2466153A1 CA002466153A CA2466153A CA2466153A1 CA 2466153 A1 CA2466153 A1 CA 2466153A1 CA 002466153 A CA002466153 A CA 002466153A CA 2466153 A CA2466153 A CA 2466153A CA 2466153 A1 CA2466153 A1 CA 2466153A1
Authority
CA
Canada
Prior art keywords
electrode
recess
source
electrodes
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002466153A
Other languages
French (fr)
Other versions
CA2466153C (en
Inventor
Hans Gude Gudesen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ensurge Micropower ASA
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2466153A1 publication Critical patent/CA2466153A1/en
Application granted granted Critical
Publication of CA2466153C publication Critical patent/CA2466153C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

comprises one or more layers (1) of semiconducting material, two or more electrode layers, and memory material (11) contacting electrodes (2,6, 10) i n the latter. At least one layer of a semiconducting material and two electrod e layers form transistor structures such that the electrodes of the first electrode layer forms source/drain electrode pairs and those of a second electrode layer form the gate electrodes thereof. The source and drain electrodes (2;6) of a single transistor/memory structure are separated by a narrow recess (3) extending down to the semiconducting (1) layer wherein the transistor channel (8) is provided beneath the recess and with extremely sma ll width, while the source and drain regions are provided beneath the respectiv e source and drain electrodes (2;6) on either side of the transistor channel(8 ). Memory material (11) is provided in the recess (3) and contacts the electrod es (2,6,10) of the transistor. This arrangement defines the transistor channel (8) with a length L corresponding to the width of the recess (3) and a width W corresponding to the width of the gate electrode (10), L being a fraction of W, and three memory cells in the memory material (11) formed respectively between the source electrode (2) and the gate electrode (10), the drain electrode (6) and the gate electrode (10) and in the recess between the sour ce and drain electrodes (2;6).
CA002466153A 2001-12-10 2002-11-18 Integrated transistor/memory structures and a matrix-addressable array thereof Expired - Fee Related CA2466153C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
NO20016041A NO20016041A (en) 2001-12-10 2001-12-10 Matrix addressable group of integrated transistor / memory structures
NO20016041 2001-12-10
PCT/NO2002/000426 WO2003050814A1 (en) 2001-12-10 2002-11-18 A matrix-addressable array of integrated transistor/memory structures

Publications (2)

Publication Number Publication Date
CA2466153A1 true CA2466153A1 (en) 2003-06-19
CA2466153C CA2466153C (en) 2007-01-23

Family

ID=19913138

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002466153A Expired - Fee Related CA2466153C (en) 2001-12-10 2002-11-18 Integrated transistor/memory structures and a matrix-addressable array thereof

Country Status (11)

Country Link
EP (1) EP1451825B1 (en)
JP (1) JP2005512338A (en)
KR (1) KR100556089B1 (en)
CN (1) CN1602531A (en)
AT (1) ATE357045T1 (en)
AU (1) AU2002366675A1 (en)
CA (1) CA2466153C (en)
DE (1) DE60218887D1 (en)
NO (1) NO20016041A (en)
RU (1) RU2287205C2 (en)
WO (1) WO2003050814A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8120082B2 (en) 2005-09-12 2012-02-21 University of Seoul, Foundation of Industry-Academic Cooperation Ferroelectric memory device and method for manufacturing the same
KR100988227B1 (en) * 2005-09-12 2010-10-18 서울시립대학교 산학협력단 Ferroelectric memory device and manufacturing method thereof
EP1808863A1 (en) * 2006-01-16 2007-07-18 Deutsche Thomson-Brandt Gmbh Method and apparatus for recording high-speed input data into a matrix of memory devices
KR101245293B1 (en) * 2006-01-19 2013-03-19 서울시립대학교 산학협력단 Ferrodielectric material for ferrodielectric memory
US10163917B2 (en) * 2016-11-01 2018-12-25 Micron Technology, Inc. Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
CN112908368B (en) * 2021-02-04 2023-03-21 清华大学 Three-state content addressing memory based on monolithic three-dimensional heterogeneous integration

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4952031A (en) * 1987-06-19 1990-08-28 Victor Company Of Japan, Ltd. Liquid crystal display device
RU2054753C1 (en) * 1993-03-19 1996-02-20 Институт физики полупроводников СО РАН Reading set based on charge-coupled devices for two-dimension image receivers
JPH07106450A (en) * 1993-10-08 1995-04-21 Olympus Optical Co Ltd Ferroelectric gate transistor memory
DE69739045D1 (en) * 1997-08-27 2008-11-27 St Microelectronics Srl Manufacturing method for electronic memory devices with virtual ground
US6072716A (en) * 1999-04-14 2000-06-06 Massachusetts Institute Of Technology Memory structures and methods of making same
US6473388B1 (en) * 2000-08-31 2002-10-29 Hewlett Packard Company Ultra-high density information storage device based on modulated cathodoconductivity

Also Published As

Publication number Publication date
WO2003050814A1 (en) 2003-06-19
EP1451825A1 (en) 2004-09-01
KR100556089B1 (en) 2006-03-03
JP2005512338A (en) 2005-04-28
CN1602531A (en) 2005-03-30
AU2002366675A1 (en) 2003-06-23
NO20016041D0 (en) 2001-12-10
CA2466153C (en) 2007-01-23
ATE357045T1 (en) 2007-04-15
KR20040064733A (en) 2004-07-19
NO314736B1 (en) 2003-05-12
EP1451825B1 (en) 2007-03-14
DE60218887D1 (en) 2007-04-26
RU2287205C2 (en) 2006-11-10
NO20016041A (en) 2003-05-12
RU2004120776A (en) 2005-09-20

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Effective date: 20081118