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CA2203378A1 - Traitement simultane par elements multiples - Google Patents

Traitement simultane par elements multiples

Info

Publication number
CA2203378A1
CA2203378A1 CA 2203378 CA2203378A CA2203378A1 CA 2203378 A1 CA2203378 A1 CA 2203378A1 CA 2203378 CA2203378 CA 2203378 CA 2203378 A CA2203378 A CA 2203378A CA 2203378 A1 CA2203378 A1 CA 2203378A1
Authority
CA
Canada
Prior art keywords
data transfer
data
cpu
switch means
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2203378
Other languages
English (en)
Inventor
Hitoshi Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FLAMEPOINT Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2203378A1 publication Critical patent/CA2203378A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

Système de traitement simultané de flux de données multiples par des éléments multiples d'un système informatique. Le système accélère l'acquisition, le traitement, l'affichage, le transfert, l'extraction et la mémorisation simultanés dans un agencement présentant une UC (10), des dispositifs E/S (18, 22), des connexions de rebouclage ainsi que des blocs de mémoire multiples optionnels (26, 28, 30, 32) connectés à une matrice de commutateurs à barres croisées (16). Un disque système (14) est connecté séparément à l'UC (10) sur un bus (12) de UC et est isolé physiquement et électriquement des autres éléments. Pendant le transfert de données vers n'importe lequel des dispositifs, et inversement, connectés à la matrice de commutateurs à barres croisées (16), l'UC (10) exécute les opérations de servitude d'un système de sous-programme périodiques sans interrompre le flux de données vers d'autres dispositifs, et à partir de ceux-ci, du fait que l'UC (10) présente un bus (12) UC séparé assurant une connexion au disque système ainsi qu'à d'autres éléments du système. Ainsi, les opérations de transfert de données continuent sans interruption et sont achevées de manière accélérée.
CA 2203378 1994-10-26 1995-10-13 Traitement simultane par elements multiples Abandoned CA2203378A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32970794A 1994-10-26 1994-10-26
US08/329,707 1994-10-26

Publications (1)

Publication Number Publication Date
CA2203378A1 true CA2203378A1 (fr) 1996-05-09

Family

ID=23286639

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2203378 Abandoned CA2203378A1 (fr) 1994-10-26 1995-10-13 Traitement simultane par elements multiples

Country Status (3)

Country Link
AU (1) AU4002095A (fr)
CA (1) CA2203378A1 (fr)
WO (1) WO1996013775A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5941968A (en) * 1997-04-14 1999-08-24 Advanced Micro Devices, Inc. Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
US6057862A (en) * 1997-07-01 2000-05-02 Memtrax Llc Computer system having a common display memory and main memory
US6118462A (en) * 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
US6381247B1 (en) * 1998-12-17 2002-04-30 Nortel Networks Limited Service independent switch interface
DE19936080A1 (de) * 1999-07-30 2001-02-15 Siemens Ag Multiprozessorsystem zum Durchführen von Speicherzugriffen auf einen gemeinsamen Speicher sowie dazugehöriges Verfahren
US6950893B2 (en) 2001-03-22 2005-09-27 I-Bus Corporation Hybrid switching architecture

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
US5339396A (en) * 1987-11-18 1994-08-16 Hitachi, Ltd. Interconnection network and crossbar switch for the same
US4979100A (en) * 1988-04-01 1990-12-18 Sprint International Communications Corp. Communication processor for a packet-switched network
US5163131A (en) * 1989-09-08 1992-11-10 Auspex Systems, Inc. Parallel i/o network file server architecture
US5226125A (en) * 1989-11-17 1993-07-06 Keith Balmer Switch matrix having integrated crosspoint logic and method of operation

Also Published As

Publication number Publication date
AU4002095A (en) 1996-05-23
WO1996013775A1 (fr) 1996-05-09

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Legal Events

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