[go: up one dir, main page]

CA2283776A1 - Combining hardware and software to provide an improved microprocessor - Google Patents

Combining hardware and software to provide an improved microprocessor Download PDF

Info

Publication number
CA2283776A1
CA2283776A1 CA002283776A CA2283776A CA2283776A1 CA 2283776 A1 CA2283776 A1 CA 2283776A1 CA 002283776 A CA002283776 A CA 002283776A CA 2283776 A CA2283776 A CA 2283776A CA 2283776 A1 CA2283776 A1 CA 2283776A1
Authority
CA
Canada
Prior art keywords
host
speculation
state
execute
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002283776A
Other languages
French (fr)
Other versions
CA2283776C (en
Inventor
Robert F. Cmelik
David R. Ditzel
Edmund J. Kelly
Colin B. Hunter
Douglas A. Laird
Malcolm John Wing
Gregorz B. Zyner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intellectual Ventures Holding 81 LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2283776A1 publication Critical patent/CA2283776A1/en
Application granted granted Critical
Publication of CA2283776C publication Critical patent/CA2283776C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/52—Binary to binary
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45554—Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

A microprocessor for a host computer designed to execute target application programs including the combination of code morphing software, and morph host hardware designed to execute instructions of a host instruction set, the combination translating a target instruction set into a host instruction set, optimizing the host instruction set speculating upon the occurrence of a condition, determining under control of the code morphine software official state of the target computer, updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, detecting failure of the condition during execution, updating state from the state of the target computer when a set of host instruction fails to execute in accordance with the speculation, and translating a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.
CA002283776A 1997-06-25 1997-06-25 Combining hardware and software to provide an improved microprocessor Expired - Fee Related CA2283776C (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1997/011616 WO1998059292A1 (en) 1997-06-25 1997-06-25 Improved microprocessor

Publications (2)

Publication Number Publication Date
CA2283776A1 true CA2283776A1 (en) 1998-12-30
CA2283776C CA2283776C (en) 2003-11-11

Family

ID=22261203

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002283776A Expired - Fee Related CA2283776C (en) 1997-06-25 1997-06-25 Combining hardware and software to provide an improved microprocessor

Country Status (5)

Country Link
EP (1) EP0991994A4 (en)
JP (1) JP3776132B2 (en)
KR (1) KR100443759B1 (en)
CA (1) CA2283776C (en)
WO (1) WO1998059292A1 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69924857T2 (en) 1998-10-10 2006-03-02 Transitive Ltd., Hanging Ditch PROGRAM CODE CONVERSION
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6978462B1 (en) 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
JP5520326B2 (en) * 1999-01-28 2014-06-11 エーティーアイ・テクノロジーズ・ユーエルシー Method and computer for referencing computer memory
AU4580300A (en) * 1999-04-27 2000-11-10 Transitive Technologies Limited Exception handling method and apparatus for use in program code conversion
US7353163B2 (en) 1999-04-27 2008-04-01 Transitive Limited Exception handling method and apparatus for use in program code conversion
US6549959B1 (en) 1999-08-30 2003-04-15 Ati International Srl Detecting modification to computer memory by a DMA device
US6751583B1 (en) 1999-10-29 2004-06-15 Vast Systems Technology Corporation Hardware and software co-simulation including simulating a target processor using binary translation
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US6627564B1 (en) * 2000-08-31 2003-09-30 Kimberly-Clark Worldwide, Inc. Composite elastic in one direction and extensible in another direction
FR2814257B1 (en) * 2000-09-20 2002-12-06 Palmware MULTI-PLATFORM VIRTUAL MICROPROCESSOR ARCHITECTURE AND ITS COMPLEMENTARY OPERATING SYSTEM, PARTICULARLY FOR THE EMBEDDED AND MOBILE COMPUTER AREA
WO2002052409A2 (en) * 2000-11-13 2002-07-04 Sun Microsystems, Inc. Method and apparatus for increasing performance of an interpreter
EP1313012A1 (en) * 2001-11-15 2003-05-21 Texas Instruments France Java DSP acceleration by byte-code optimization
US7805710B2 (en) * 2003-07-15 2010-09-28 International Business Machines Corporation Shared code caching for program code conversion
US7353499B2 (en) 2003-09-25 2008-04-01 Sun Microsystems, Inc. Multiple instruction dispatch tables for application program obfuscation
US7424620B2 (en) 2003-09-25 2008-09-09 Sun Microsystems, Inc. Interleaved data and instruction streams for application program obfuscation
US7415618B2 (en) 2003-09-25 2008-08-19 Sun Microsystems, Inc. Permutation of opcode values for application program obfuscation
US7363620B2 (en) 2003-09-25 2008-04-22 Sun Microsystems, Inc. Non-linear execution of application program instructions for application program obfuscation
US8220058B2 (en) 2003-09-25 2012-07-10 Oracle America, Inc. Rendering and encryption engine for application program obfuscation
US8020152B2 (en) * 2005-02-24 2011-09-13 Microsoft Corporation Code morphing
US7882336B2 (en) 2007-02-01 2011-02-01 International Business Machines Corporation Employing a buffer to facilitate instruction execution
KR100968376B1 (en) * 2009-01-13 2010-07-09 주식회사 코아로직 Device and method for processing application between different processor, and application processor(ap) communication system comprising the same device
US9525586B2 (en) 2013-03-15 2016-12-20 Intel Corporation QoS based binary translation and application streaming
US9703562B2 (en) * 2013-03-16 2017-07-11 Intel Corporation Instruction emulation processors, methods, and systems
CN118093017A (en) * 2022-11-22 2024-05-28 上海兆芯集成电路股份有限公司 Efficient instruction translation method and processor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574927A (en) * 1994-03-25 1996-11-12 International Meta Systems, Inc. RISC architecture computer configured for emulation of the instruction set of a target computer
US5751982A (en) * 1995-03-31 1998-05-12 Apple Computer, Inc. Software emulation system with dynamic translation of emulated instructions for increased processing speed
US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor

Also Published As

Publication number Publication date
JP2001519953A (en) 2001-10-23
EP0991994A4 (en) 2001-11-28
EP0991994A1 (en) 2000-04-12
WO1998059292A1 (en) 1998-12-30
KR100443759B1 (en) 2004-08-09
CA2283776C (en) 2003-11-11
JP3776132B2 (en) 2006-05-17
KR20010014094A (en) 2001-02-26

Similar Documents

Publication Publication Date Title
CA2283776A1 (en) Combining hardware and software to provide an improved microprocessor
US4791557A (en) Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system
US4974159A (en) Method of transferring control in a multitasking computer system
US6219796B1 (en) Power reduction for processors by software control of functional units
TW337006B (en) Apparatus for detecting and excuting traps in a superscalar processor
WO2002054194A3 (en) Adaptive software installation process supporting multiple layers of security-related attributes
WO2000019317A8 (en) Protection of boot block code while allowing write accesses to the boot block
WO1994009433A3 (en) A system for operating application software in a safety critical environment
EP0849671A3 (en) A method for utilizing a multi-word instruction register during debugging of a data processing system
WO2006113167A3 (en) Secure boot
CA2102089A1 (en) Recompilation of Computer Programs for Enhanced Optimization
WO2004006060A3 (en) Statically speculative compilation and execution
WO1999026132A3 (en) Processor configured to generate lookahead results from collapsed moves, compares and simple arithmetic instructions
EP1089170A3 (en) Processor architecture and method of processing branch control instructions
EP1096386A3 (en) Interrupt control apparatuses and methods
HK1046969A1 (en) System management memory for system management interrupt handler is integrated into memory controller, independent of bios and operating system
SG74590A1 (en) Computer system and method for executing threads of execution with reduce run-time memory space requirements
WO2004059472A3 (en) Method and apparatus for generating prefetches
WO2004086220A3 (en) Controlled execution of a program used for a virtual machine on a portable data carrier
WO1996008762A3 (en) Processing system with word-aligned branch target
EP1387259A3 (en) Inter-processor control
WO2004079513A3 (en) System and method for determining when an ejb compiler needs to be executed
EP1230594A4 (en) A method for translating instructions in a speculative microprocessor
GB2376097A (en) Configuration control within data processing systems
US20040122800A1 (en) Method and apparatus for hardware assisted control redirection of original computer code to transformed code

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed