CA2273223C - Chip-size package using a polyimide pcb interposer - Google Patents
Chip-size package using a polyimide pcb interposer Download PDFInfo
- Publication number
- CA2273223C CA2273223C CA002273223A CA2273223A CA2273223C CA 2273223 C CA2273223 C CA 2273223C CA 002273223 A CA002273223 A CA 002273223A CA 2273223 A CA2273223 A CA 2273223A CA 2273223 C CA2273223 C CA 2273223C
- Authority
- CA
- Canada
- Prior art keywords
- chip
- integrated circuit
- printed circuit
- circuit board
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920001721 polyimide Polymers 0.000 title claims abstract description 20
- 239000004642 Polyimide Substances 0.000 title claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 239000000853 adhesive Substances 0.000 claims abstract description 5
- 230000001070 adhesive effect Effects 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 claims description 2
- 229920006332 epoxy adhesive Polymers 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 claims description 2
- 238000012545 processing Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 241000168096 Glareolidae Species 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A chip-size package formed using a printed circuit board, preferably comprising polyimide. The chip-size package comprises an integrated circuit chip having a plurality of peripheral bond pads. The printed circuit board h as a plurality of solder bumps formed on its top surface and a plurality of bon d pads around its periphery. A layer of adhesive is used to secure the printed circuit board and the integrated circuit chip together. A plurality of wire bonds electrically connected between selected bond pads of the integrated circuit chip and the printed circuit board. An encapsulant encapsulates the wire bonds and bond pads of the integrated circuit chip and the printed circuit board.
Description
CHIP-SIZE PACKAGE USING A POLYIMIDE PCB INTERPOSER
BACKGROUND
The present invention relates generally to integrated circuit packages and methods, and more particularly, to a chip-size integrated circuit package formed using a polyimide printed circuit board interposer.
The closest form of art to the present invention is a chip-size package made by a company called Tessera. The Tessera chip-size package uses formed tape automated bonded (TAB) lead frames on a polyimide film. It would be desirable to have a chip-size package that has fewer processing steps, is less expensive to build, and that employs commonly available processing equipment.
Furthermore, most chip size package designs are larger than the die itself. It would therefore be desirable to have a chip-size package that packages the integrated circuit chip within the internal surface area of the bare die.
Accordingly, it is an objective of the present invention to provide for an improved chip-size package formed using a polyimide printed circuit board interposer.
SUMMARY OF THE INVENTION
To meet the above and other objectives, the present invention provides for a chip-size package formed using a polyimide printed circuit board interposer. In accordance with one aspect of the present invention there is provided a chip-size integrated circuit package comprising:
an integrated circuit chip having a plurality of peripheral bond pads;
a polyimide printed circuit board having a plurality of solder bumps formed on a top surface thereof and a plurality of bond pads around its periphery;
a layer of adhesive disposed between the polyimide printed circuit board and the integrated circuit chip to secure them directly together;
a plurality of wire bonds electrically connected between selected bond pads of the integrated circuit chip and the polyimide printed circuit board; and an encapsulant for encapsulating the wire bonds and bond pads of the integrated circuit chip and the polyimide printed circuit board.
It is believed that the present invention may be built for a lower cost than the Tessera or other prior art chip-size package because the present invention has fewer processing steps and has a lower material cost. The present invention also uses more common and lower cost processing equipment than does the Tessera or other prior art process.
WO 99/17364 " PCT/US98/20467 The present invention converts a single, unpackaged bare silicon chip into a packaged chip no larger in area than the bare chip. 'the present invention uses readily available printed circuit board materials and technology. This chip size packaging scheme of the present invention is novel in that it uses a low cost printed circuit board interposes with exposed. lower layers incorporating wire bond pads. The wire bond pads are sufficiently lower than the solder bumps on the cog layer of the interposes. and as such. wire bonds to the wire bond pads can be encapsulated without exceeding the height of the top printed circuit board layer which rnust remain flat for soldering.
The present invention converts a bare chip into a chip size package. The chip size package may be assembled in a manner similar to surface mount devices which are soldered to printed ciccuit boards. Chip size packages, however, take up only 10-20%
of the area of conventionally packaged chips fabricated as surface mount devices.
Development of the chip size package of the present invention is an important step in achieving miniaturization of microelectronics.
Most chip size packages are lamer than the; die itself. The present invention however, packages the chip within the internal surface area of the bare die.
Because the present chip size package takes up no additional area than the bare die, it is believed to be the smallest two-dimensional integrated circuit package that has yet been developed.
The oenefit of converting a bare die into a surface mount device is chat it provides mechanical and environmental protection for the fragile silicon integrated circuit chip. The present invention also converts a fine pitch peripheral pad integrated circuit into a packaged. courser pitch area array device. permitting it to be easily tested.
burned in, and assembled to standard printed circuit boards using existing.
common equipment used in the industry. The ability to us,e "known good" tested devices while utilizing industry standard and accepted equipment and processes is a key element in obtaining the absolute lowest product cost.
The present invention permits silicon integrated circuiu to be packaged in the smallest area possible. which is no larger than the size of the integrated circuit itself.
Incorporating such low cost integrated circuit packages into various microelectronic applications will provide for smaller product sizes, lower weight, and lower assembly and testing costs. The present invention provides for a robust packaging structure that is suitable for a variety of commercial and milit~uy applications. including automotive electronics, for example.
BRIEF DESCRIPTION OF THE DRAWINGS
The various features and advantages of the present invention may be more readily understood with reference to the following detailed description taken in WO 99117364 " PCT/US98/20467 conjunction with the accompanying drawings, wherein Iike reference numerals represent like structural elements. and in which:
Fig. 1a-lc illustrate formation of a chip-size; integrated circuit packase in accordance with the principles of the present inventuon:
Fig. 2 is a perspective view of a fully assembled chip-size integrated circuit package; and Fig. 3 illustrates the chip-size integrated circuit package assembled to a printed circuit board.
DETrIILED DESCRIP'CION
Referring to the drawing figures. Fig. la-lc illustrate formation of a chip-size integrated circuit package 10 in accordance with tb~e principles of the present invention.
Referring to Fib. la, the chip-size integrated circuit package LO comprises an integrated circuit chip 11, which may be a silicon integrated circuit chip 11. for example, having a plurality of peripheral bond pads 13. A printed circuit board 14, or interposer 14.
which is preferably comprised of polyimide. is formed having a plurality of solder bumps 16 (or an area array of solder bumps 16) formed on a top surface. and a plurality of bond pads 15 around its periphery. The polyirnide printed circuit board 14, or interposer 14. is attached to the integrated circuit chip 11 using a layer of adhesive 12.
such as a layer of epoxy adhesive 12. for example.
Fig. 1b shows an assembled chip-size package 10 wherein the polyimide printed circuit board 14 is electrically attached to the integrated circuit chip 1 t using a plurality of wire bonds 18 coupled between the respective pluralities of bond pads 13.
15. Referring to Fig. 1 c. after the wire bonds 18 are formed between the polyimide printed circuit board 14 and the integrated circuit chip I 1. the wire bonds 18 are encapsulated using an encapsulant 17, such as flexible epoxy or silicone, for example.
Fig. 2 is a perspective view of a fully assembled chip-size integrated circuit package 10. The encapsulant 17 is shown in ph,uttom. The chip-size integrated circuit package 10 has the area array of solder bumps 16 exposed for reflow soldering.
Fig. 3 illustrates the chip-size integrated circuit package 10 of Fig. 2 assembled to a printed circuit board 21. The printed circuit board 21 has an area array of solder bumps 22 that matches the area array of solder bumps 16 on the chip-size integrated circuit package 10. The chip-size integrated circuit package 10 and the printed circuit board 21 are electrically connected together by reflowing the solder bumps 16.
22 to form the electrical interconnections therebetween.
Thus, the present invention provides for a chip-size package 10 formed using a polyimide printed circuit board interposer 14. Lt is believed that the present invention may be built for a relatively low cost than prior art chip-size packages because the present invention has fewer processing steps and has lower material costs. The present invention also uses more common and lower cost processing equipment than is used to produce prior art chip-size packages.
The present invention converts a single, unpackaged bare integrated circuit chip 11, for example, into a packaged chip 20 no larger in area than the bare chip 1 I. The present invention uses readily available printed cirt:uit board materials and technology.
The chip size package 10 uses the low cost printed circuit board interposer l4 with exposed, lower layers having wire bond pads 13, 15. The wire bond pads 13. I5 are sufficiently lower than the solder bumps 16 on top of the interposer i4, and therefore, wire bonds 18 to the wire bond pads 13, 15 are encapsulated without exceeding the height of the top printed circuit board 14 which must remain flat for soldering.
The present invention thus converts a bare chip 11 into a chip size package I0.
The chip size package 10 may be assembled in a manner similar to surface mount devices which are soldered to printed circuit boards. The chip size package 10.
however, takes up only 10-20% of the area of conventionally packaged chips 11 fabricated as surface mount devices.
The present invention packages the chip L :l within the internal surface area of the bare chip 11. Because the chip size package 1~0 takes up no additional area than the bare chip 11, it is believed to be the smallest two-dimensional integrated circuit package 10 that has yet been developed.
The chip size package LO provides mecharucal and environmental protection for the fragile integrated circuit chip 1 I . The chip size package 10 also converts a fine pitch peripheral pad integrated circuit 11 into a packaged, courser pitch area array device.
permitting it to be easily tested, burned in, and assembled to standard printed circuit boards 21 ustng existing, common equipment used in the industry.
The present invention permits integrated circuits to be packaged in the smallest area possible, which is no larger than area of the integrated circuit 11. The chip size package 10 provides for a robust packaging structure that is suitable for a variety of commercial and military applications, including automotive electronics, for example.
Thus, a chip-size package formed using a polyimide printed circuit board intetposer has been disclosed. It is to be understood that the described embodiment is merely illustrative of some of the many specific embodiments which represent applications of the principles of the present invention. Clearly, numerous and other arrangements can be readily devised by those skililed in the art without departing from the scope of the invention.
BACKGROUND
The present invention relates generally to integrated circuit packages and methods, and more particularly, to a chip-size integrated circuit package formed using a polyimide printed circuit board interposer.
The closest form of art to the present invention is a chip-size package made by a company called Tessera. The Tessera chip-size package uses formed tape automated bonded (TAB) lead frames on a polyimide film. It would be desirable to have a chip-size package that has fewer processing steps, is less expensive to build, and that employs commonly available processing equipment.
Furthermore, most chip size package designs are larger than the die itself. It would therefore be desirable to have a chip-size package that packages the integrated circuit chip within the internal surface area of the bare die.
Accordingly, it is an objective of the present invention to provide for an improved chip-size package formed using a polyimide printed circuit board interposer.
SUMMARY OF THE INVENTION
To meet the above and other objectives, the present invention provides for a chip-size package formed using a polyimide printed circuit board interposer. In accordance with one aspect of the present invention there is provided a chip-size integrated circuit package comprising:
an integrated circuit chip having a plurality of peripheral bond pads;
a polyimide printed circuit board having a plurality of solder bumps formed on a top surface thereof and a plurality of bond pads around its periphery;
a layer of adhesive disposed between the polyimide printed circuit board and the integrated circuit chip to secure them directly together;
a plurality of wire bonds electrically connected between selected bond pads of the integrated circuit chip and the polyimide printed circuit board; and an encapsulant for encapsulating the wire bonds and bond pads of the integrated circuit chip and the polyimide printed circuit board.
It is believed that the present invention may be built for a lower cost than the Tessera or other prior art chip-size package because the present invention has fewer processing steps and has a lower material cost. The present invention also uses more common and lower cost processing equipment than does the Tessera or other prior art process.
WO 99/17364 " PCT/US98/20467 The present invention converts a single, unpackaged bare silicon chip into a packaged chip no larger in area than the bare chip. 'the present invention uses readily available printed circuit board materials and technology. This chip size packaging scheme of the present invention is novel in that it uses a low cost printed circuit board interposes with exposed. lower layers incorporating wire bond pads. The wire bond pads are sufficiently lower than the solder bumps on the cog layer of the interposes. and as such. wire bonds to the wire bond pads can be encapsulated without exceeding the height of the top printed circuit board layer which rnust remain flat for soldering.
The present invention converts a bare chip into a chip size package. The chip size package may be assembled in a manner similar to surface mount devices which are soldered to printed ciccuit boards. Chip size packages, however, take up only 10-20%
of the area of conventionally packaged chips fabricated as surface mount devices.
Development of the chip size package of the present invention is an important step in achieving miniaturization of microelectronics.
Most chip size packages are lamer than the; die itself. The present invention however, packages the chip within the internal surface area of the bare die.
Because the present chip size package takes up no additional area than the bare die, it is believed to be the smallest two-dimensional integrated circuit package that has yet been developed.
The oenefit of converting a bare die into a surface mount device is chat it provides mechanical and environmental protection for the fragile silicon integrated circuit chip. The present invention also converts a fine pitch peripheral pad integrated circuit into a packaged. courser pitch area array device. permitting it to be easily tested.
burned in, and assembled to standard printed circuit boards using existing.
common equipment used in the industry. The ability to us,e "known good" tested devices while utilizing industry standard and accepted equipment and processes is a key element in obtaining the absolute lowest product cost.
The present invention permits silicon integrated circuiu to be packaged in the smallest area possible. which is no larger than the size of the integrated circuit itself.
Incorporating such low cost integrated circuit packages into various microelectronic applications will provide for smaller product sizes, lower weight, and lower assembly and testing costs. The present invention provides for a robust packaging structure that is suitable for a variety of commercial and milit~uy applications. including automotive electronics, for example.
BRIEF DESCRIPTION OF THE DRAWINGS
The various features and advantages of the present invention may be more readily understood with reference to the following detailed description taken in WO 99117364 " PCT/US98/20467 conjunction with the accompanying drawings, wherein Iike reference numerals represent like structural elements. and in which:
Fig. 1a-lc illustrate formation of a chip-size; integrated circuit packase in accordance with the principles of the present inventuon:
Fig. 2 is a perspective view of a fully assembled chip-size integrated circuit package; and Fig. 3 illustrates the chip-size integrated circuit package assembled to a printed circuit board.
DETrIILED DESCRIP'CION
Referring to the drawing figures. Fig. la-lc illustrate formation of a chip-size integrated circuit package 10 in accordance with tb~e principles of the present invention.
Referring to Fib. la, the chip-size integrated circuit package LO comprises an integrated circuit chip 11, which may be a silicon integrated circuit chip 11. for example, having a plurality of peripheral bond pads 13. A printed circuit board 14, or interposer 14.
which is preferably comprised of polyimide. is formed having a plurality of solder bumps 16 (or an area array of solder bumps 16) formed on a top surface. and a plurality of bond pads 15 around its periphery. The polyirnide printed circuit board 14, or interposer 14. is attached to the integrated circuit chip 11 using a layer of adhesive 12.
such as a layer of epoxy adhesive 12. for example.
Fig. 1b shows an assembled chip-size package 10 wherein the polyimide printed circuit board 14 is electrically attached to the integrated circuit chip 1 t using a plurality of wire bonds 18 coupled between the respective pluralities of bond pads 13.
15. Referring to Fig. 1 c. after the wire bonds 18 are formed between the polyimide printed circuit board 14 and the integrated circuit chip I 1. the wire bonds 18 are encapsulated using an encapsulant 17, such as flexible epoxy or silicone, for example.
Fig. 2 is a perspective view of a fully assembled chip-size integrated circuit package 10. The encapsulant 17 is shown in ph,uttom. The chip-size integrated circuit package 10 has the area array of solder bumps 16 exposed for reflow soldering.
Fig. 3 illustrates the chip-size integrated circuit package 10 of Fig. 2 assembled to a printed circuit board 21. The printed circuit board 21 has an area array of solder bumps 22 that matches the area array of solder bumps 16 on the chip-size integrated circuit package 10. The chip-size integrated circuit package 10 and the printed circuit board 21 are electrically connected together by reflowing the solder bumps 16.
22 to form the electrical interconnections therebetween.
Thus, the present invention provides for a chip-size package 10 formed using a polyimide printed circuit board interposer 14. Lt is believed that the present invention may be built for a relatively low cost than prior art chip-size packages because the present invention has fewer processing steps and has lower material costs. The present invention also uses more common and lower cost processing equipment than is used to produce prior art chip-size packages.
The present invention converts a single, unpackaged bare integrated circuit chip 11, for example, into a packaged chip 20 no larger in area than the bare chip 1 I. The present invention uses readily available printed cirt:uit board materials and technology.
The chip size package 10 uses the low cost printed circuit board interposer l4 with exposed, lower layers having wire bond pads 13, 15. The wire bond pads 13. I5 are sufficiently lower than the solder bumps 16 on top of the interposer i4, and therefore, wire bonds 18 to the wire bond pads 13, 15 are encapsulated without exceeding the height of the top printed circuit board 14 which must remain flat for soldering.
The present invention thus converts a bare chip 11 into a chip size package I0.
The chip size package 10 may be assembled in a manner similar to surface mount devices which are soldered to printed circuit boards. The chip size package 10.
however, takes up only 10-20% of the area of conventionally packaged chips 11 fabricated as surface mount devices.
The present invention packages the chip L :l within the internal surface area of the bare chip 11. Because the chip size package 1~0 takes up no additional area than the bare chip 11, it is believed to be the smallest two-dimensional integrated circuit package 10 that has yet been developed.
The chip size package LO provides mecharucal and environmental protection for the fragile integrated circuit chip 1 I . The chip size package 10 also converts a fine pitch peripheral pad integrated circuit 11 into a packaged, courser pitch area array device.
permitting it to be easily tested, burned in, and assembled to standard printed circuit boards 21 ustng existing, common equipment used in the industry.
The present invention permits integrated circuits to be packaged in the smallest area possible, which is no larger than area of the integrated circuit 11. The chip size package 10 provides for a robust packaging structure that is suitable for a variety of commercial and military applications, including automotive electronics, for example.
Thus, a chip-size package formed using a polyimide printed circuit board intetposer has been disclosed. It is to be understood that the described embodiment is merely illustrative of some of the many specific embodiments which represent applications of the principles of the present invention. Clearly, numerous and other arrangements can be readily devised by those skililed in the art without departing from the scope of the invention.
Claims (5)
1. A chip-size integrated circuit package comprising:
an integrated circuit chip having a plurality of peripheral bond pads;
a polyimide printed circuit board having a plurality of solder bumps formed on a top surface thereof and a plurality of bond pads around its periphery;
a layer of adhesive disposed between the polyimide printed circuit board and the integrated circuit chip to secure them directly together;
a plurality of wire bonds electrically connected between selected bond pads of the integrated circuit chip and the polyimide printed circuit board; and an encapsulant for encapsulating the wire bonds and bond pads of the integrated circuit chip and the polyimide printed circuit board.
an integrated circuit chip having a plurality of peripheral bond pads;
a polyimide printed circuit board having a plurality of solder bumps formed on a top surface thereof and a plurality of bond pads around its periphery;
a layer of adhesive disposed between the polyimide printed circuit board and the integrated circuit chip to secure them directly together;
a plurality of wire bonds electrically connected between selected bond pads of the integrated circuit chip and the polyimide printed circuit board; and an encapsulant for encapsulating the wire bonds and bond pads of the integrated circuit chip and the polyimide printed circuit board.
2. The package of claim 1 wherein the integrated circuit chip comprises a silicon integrated circuit chip.
3. The package of claim 1 wherein the layer of adhesive comprises a layer of epoxy adhesive.
4. The package of claim 1 wherein the encapsulant comprises flexible epoxy.
5. The package of claim 1 wherein the encapsulant comprises silicone.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US93983297A | 1997-09-29 | 1997-09-29 | |
| US08/939,832 | 1997-09-29 | ||
| PCT/US1998/020467 WO1999017364A1 (en) | 1997-09-29 | 1998-09-29 | Chip-size package using a polyimide pcb interposer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2273223A1 CA2273223A1 (en) | 1999-04-08 |
| CA2273223C true CA2273223C (en) | 2003-11-11 |
Family
ID=25473815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002273223A Expired - Lifetime CA2273223C (en) | 1997-09-29 | 1998-09-29 | Chip-size package using a polyimide pcb interposer |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA2273223C (en) |
| WO (1) | WO1999017364A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7531643B2 (en) | 1997-09-11 | 2009-05-12 | Chugai Seiyaku Kabushiki Kaisha | Monoclonal antibody inducing apoptosis |
| US7696325B2 (en) | 1999-03-10 | 2010-04-13 | Chugai Seiyaku Kabushiki Kaisha | Polypeptide inducing apoptosis |
| CN1308448C (en) | 2000-10-20 | 2007-04-04 | 中外制药株式会社 | Low molecular weight TPO agonist antibody |
| JP2004279086A (en) | 2003-03-13 | 2004-10-07 | Konica Minolta Holdings Inc | Radiation image conversion panel and method for manufacturing it |
| WO2006106903A1 (en) | 2005-03-31 | 2006-10-12 | Chugai Seiyaku Kabushiki Kaisha | sc(Fv)2 STRUCTURAL ISOMERS |
| CN101237890A (en) | 2005-06-10 | 2008-08-06 | 中外制药株式会社 | Stabilizer for protein preparation comprising meglumine and use thereof |
| US9241994B2 (en) | 2005-06-10 | 2016-01-26 | Chugai Seiyaku Kabushiki Kaisha | Pharmaceutical compositions containing sc(Fv)2 |
| US7659151B2 (en) * | 2007-04-12 | 2010-02-09 | Micron Technology, Inc. | Flip chip with interposer, and methods of making same |
Family Cites Families (3)
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|---|---|---|---|---|
| JP3487524B2 (en) * | 1994-12-20 | 2004-01-19 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
| US5633785A (en) * | 1994-12-30 | 1997-05-27 | University Of Southern California | Integrated circuit component package with integral passive component |
| US5714800A (en) * | 1996-03-21 | 1998-02-03 | Motorola, Inc. | Integrated circuit assembly having a stepped interposer and method |
-
1998
- 1998-09-29 CA CA002273223A patent/CA2273223C/en not_active Expired - Lifetime
- 1998-09-29 WO PCT/US1998/020467 patent/WO1999017364A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| CA2273223A1 (en) | 1999-04-08 |
| WO1999017364A1 (en) | 1999-04-08 |
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