CA2019795A1 - Digital notch filter - Google Patents

Abstract

Abstract of the Invention A method and apparatus for removing an unwanted steady-state "carrier frequency" signal component from samples of an information signal by sampling the information signal at a sampling rate having a frequency twice that of the carrier frequency to form a series of information signal samples, summing each of the information signal samples with its immediately preceding one of the information signal samples, and dividing each of the sample summations by two to form a corresponding series of carrier frequency filtered information signal samples.

Description

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DIGITAL NOTCH FILTE~
ack~round Of The Invention The present invention relates to feedback control signal processing for closed-loop automatic process control systems, and par~i~ularly to a method and apparatu~ for convenien~ly filtering a steady-state fre~uenc/ component out of the feedback control ~i~nal to improve clo~ed-loop automatic process con~rol stability.
Closed-loop automatic process control systems are used in a wide variety of applications where a high degree o~ con~rolled ~lement ac~uracy is desirabl~ and a ~uitable feedback signal is available, such as in continuou~ly va~iabl~ transmission (~VT) contr~l systems.
Various application~ and con3truction for continuously variable transmi sion ~y~tems are set ~orth in the following relat~d patent~ and paten~ applica~ion~:
"Continuously Variable Transmission Clu~ch Control Syst~m," Patent No. 4,793,454; "Special S~art Technique for Continuously Variable Transmis~ion Clutch Control,"
Patent No. 4,811,225; "Temperature Compensatio~ Technique for a Continuously Variable Transmis~ion Control Sys~em,"
Serial No. 25,392; "~atio Control Technique for Continuously Variable Transmi3sion Sy~tem~," Serial No.
25,391; and l'Pulse Width Modulation Technique," Serial ~o.
25,477, all own~d by the assignee of thi~ invention and appli~ation. The ~eachings of the above identiied application~ are incorporated herein by reference.

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201g ~5 Although many dif~erent methods are ap~lied for such closed-loop control systems, one promising system of recent develooment which is particularly suited for use in CVT clutch pr~ssure control systems uses a controller signal having a pulsed output of constant frequency but variable duty cycle. The controller can be modulated by using an input signal to chanqe the position of the leading edge, trailing edge, or both edges of each pulse o~ the controller output, thus genera~ing a pulse width modulation (PWM) output o constant pulse fre~uenc~
However, in the systems described, ~ince the leading and trailin~ edges are individually variable at a rate corresponding to twice the controller output pulse rate, the control system frequency response iq improved compared 15 tP pulse width modulation ystems which only mo~ulate one edge o~ the controller output pul~e3. Alterna~ively, a system using such a double edge modulation technique can offer the sam~ frequency respon~e as a single edge modulated ~ystem, but using a much lower controller output pulse frequency, which improves control loop stability.
~ owever, the feedback control signal which is generally derlved with a leading and trailing edge P~M
control 9y. tem a~ de~cribed above ha~ a ~ubstan~ial controller output pulse frequency, or "carrier ~re~uency.' component. This component contain~ no u eful feedback information, and usually ~a3 such a pha~e ~hift that it will cause system in~tability if f~d back to the input o~
the controller.
However, it has been ~ound that the system re~ponse can be enhanced when th~ carrier frequency is sufficiently attenu~ted with a sharp no~ch filter tuned :~
the carrier frequency. Such filters can have a variet~ _' . :.: ~ .
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configurations, one of the ~implest and least expensive being a so-called "twin-T" type, analog notch filter.
However, like most analog notch filterl;, thi~ filter requires not only tight ~olerance components, but its performance is particularly sensitive to changes in operating condition~, such a~ temperature and humidity changes, which can change the values of its components, and therefoce change the notch attenuation frequency.
~ecause the feedback signal is generally converted to a digital code format before being applied to the controller in the systems described above, it has been found advantageous to process the digitally coded feedback signal to remove th~ carrier frequency component.
biect3 Of The Invention lS Accordingly, one obje~t of the invention is to remove the steady ~tate carrier frequency component present in a control si~nal.
Another o~ject i~ to remove the carrier frequency component without removing information frequency components in the con~rol signal.
Yet another object is to effectively remove the carrier fre~uen~y componen~ regardle ~ of changes in operating conditionR.
Still another object is to remove th~ carrier frequ~ncy component regardle~s of variation~ in frequency of the carrier frequency component.
A further object i to remove the carriec frequency componen~ with a minimum of expens~.

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Summary Of The Invention The present invention achieve~ the above stated objects and other advantages set forth herein by using a carrier frequency filtration system which provides remarkably effective filtration by operating after the feedback control signal is converted to digital fc mat, and utilizing th~ relationship of the digital conversion sampling frequency to the carrier frequency component to effectively null this component.
More specifically, the present invention achieves these objects by sampling the feedback control ~ignal at twice the frequency of the carrier signal to establish a ~eries o~ control signal samplings; summing each one of the samplings with its p~ereding sampling to form a corre~ponding serie~ of sampling sum~ations, and dividing each one of the sampling ~ummation3 by two to form a corre~ponding serie~ of caErier frequency filtered feedback control ~ignal ~ampling~ which may be u ed to operate the controller.
Since th~ sampling rate is easily locked in at twice th~ carrier frequency with method~ well known in t~.e art, the pre~ent inven~ion operates efectively even wit~
cha~ge in operating condition~, such a~ chanqes in temperature and humidi~y, and regardless of drift in the carrier frequency.
In control ~y~t~ms wherein the feedback ~ignal is converted to a digital coded signal be~ore b~ing ~ed tO
the controller, the present invention i9 eagily implemented at low co~t, since i~ only raquires the addition o~ a ~impl~ digital delay, summation, and division program.

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2019 ~95 Further advantages an~ impr~vements will be recognized by those skilled in the art in connection with the deqcription oE the preEerred embodiment described below.

Description Of The Drawinqs Figure 1 is a functional block diagram of a typical process control system f~r a CVT clutch pressure control application u~ing a double edge pulse width modulated controller according to the prior art.
~igure 2 is a schematic diagram o~ a typical analog notch filter of the "twin-T" type which is ~ generally used in t~e system shown in Figure lo : Figure 3 ic a graphical represe~tation of typical frequency response and phase hift curve~ fo~ the analog notch filter shown in Figure 2.
Figure 4 i~ a functional block diagram of a proces~ control ystem for a CVT clutch pressure control application which is adapted to incorporate the present inv~ntion.
~igure 5 is a functional block diagram of a digital filter ~ystem according to the pre ent inventi~n.
~igure 6 shows one implementation of the digital filter sy~tem hown in Pigure 5.
~igu~e 7 is a graphical represen~ation of ~ypical Erequency response and phase ~hift curves for the digital notch filter system shown in ~igures 5 and 6.

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Descri~tion O~ The Preferred Embodimen~

The present invention may be used in any application where a signal contains an unwanted steady-state frequency component and the signal contains no necessary information signal frequency component3 above the frequency of the unwanted steady-state component. The present invention is most useful in applications where the ~ignal to be Eiltered must be normally converted to a digital code format as part of the applications' signal processing operations.
In the above described double edge modulation system, the PWM signal is updated a~ twice the PWM output pulse rate. As indicated above, when such a control ~ystem has a feedback signal~ the feedback signal has a signiEicant fr~quency component correspondinq to the pulse rate of the PWM con~roller signal. Thi~ steady-state, "ca~rier frequency" ~ignal component has no useful information, and can cause control ~ystem in~tability due to phase ~hift if it i~ not attenuated before the feedback ~ignal i~ returned to the controller input.
A functional block diagram of a typical closed-loop proces~ control ~ystem for a CVT clutch pre~sure application i~ shown in Figure 1. ~ clo~ed loop, double-edge modulated PWM control system 2 comprise~ a digital PWM controller 4 which drive~ an operator, in thi~ case an electro-hydraulic valve system 6, a tran~ducer whlch produces a feedback control signal r~pre~entative oE
changes of the controlled variab}e by the electro-hydraulic valve sys~em 6, in thls case a clutch pressure transducer 8l an analog anti-aliasing filter 10, which condition~ ~he feedback control signal to re~ove unwante~

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high frequency components, and an ana].og notch filter 12, which removes the steady-state carrier signal component which i~ introduce~ due to the pulse rate of the PWM
controller output signal~ O~ course, any type o operator may be employed for the electro-hydraulic valve system 6, such a~ electrical, mechanical, or pneumatic, a.s well as electro-hydraulic, as long as a double-edge modulated PW.~
controL signal is used. Likewise, the controlled variable may be of any type, such as position, temperature, flow, or velocity, as well as pre~sure. Furthermore, the feedback sensor for the pressure ~ransducer 8 may be of any type, such as electrical, hydraulic, mechanical or pneumatic.
The digital PWM controller 4 samples the filtered analog clutch pressure feedback ignal fed to its analog input from the analog notch filter 12 at a regular interval. Since th~ output pulse of the digital controller 4 i~ updated at twice its pulse rate, at leas~
~wo samples fro~ the analog notch filter 12 must be made fo~ each output pu}se. Each sample i5 ~easured in amplitude, and then the measurement is converted into a digitally coded equivalent in a code ~uc~ as the binary coded deci~al ~BCD~ format. If more than two samplings are made per controller output pulse, the mea~urements of two or more ~ampling~ may be averaged, and then the average value i converted to a digitally coded equivalent. Thi~ measurement o~ the filtered clutch pre~sure feedback qignal analog notch fil~er 12 output and conversion to digital coded equivalent value~ is done by an analog to digi~al (A/D~ converter 14, which is part o~
thP digital con~roller 4.

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~8--The digLtally coded equivalent values of the clutch pressure feedback signal sampling~ produced by the A/D converter 14 are fed to a digital pressure-loop process controller 16 within the digital controller 4.
This proces~ controller 16 generally responds to the difference between at l~ast one reference level, such as a setpoint, and at least one input variable. In this ~ase, the digltally encoded clutch pressure feedback signal from the output oE the A/D convertor 1~ is one input variable for the pressure loop controller 16. The digitally encoded value of this feedback signal i~ compared to the : digitally encoded value of a setpoint in the pressure loop controller 16. Any tifference in value between the feedback signal and the se~point produces a digitally encoded output signal from the pressure loop controller with a value representative of the difference between them. The digitally enc~ded output from the pressure loop controller 16 may have a ~CD format, as well.
The digitally encoded output ~rom the pressure loop controlle~ 16 i5 fed to a double edge modulated PWM
generator 18, as described above, which is also wi~hin the digital controller 4. The PWM generator 18 change~ the relative po#itions of the leading and trailing edges o~
its constant frequency output pulse train ~ignal, thereby : 25 changing it duty cycle in response to the output of the ^~
pres~ure loop controller 16. Speci~ically, each digitally encoded valu~ of the pressure loop controller 16 shifts th~ po~ition of either a leading edge or a trailing edge of the cons~ant rate output pu~se o~ the PWM generator 1~.
If the output pulse train of the ~W~ modulator i~ integrated to substantially filter its pulse train frequency ccmponents, the integrated output control sigr.a' : , ~ . - . ; .

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_g_ is primarily a low frequency control s:ignal which has a rate which is pcoportioned to the rate of change in duty cycle of the PWM generator 18 output and an amplitude proportional to the amount of duty cyc:le change of the PWM
modulator 18 output. But in fact, the response time of the electro-hydraulic valve system 6 i~ low enough to provide an effective integrating action, leaving only a small degree of high frequency "ripple" in the ~ystem which has no effect on it~ operation. ~owever, the pressure transducer 8 responds to the system ripple, and so the ripple must be filtered out of this signal if stable closed loop control i5 to be maintained. Although the analog anti-aliasing low pas~ filter lO i~ helpful in reducing the ripp}e component of the feedback signal from lS the pres~ure tran~du~er ~, there i3 inadequate ~uppression of the ripple with a lo~ pa~s filter alone. Thu~, a notch filter must be utilized to prevent system instability.
A~ explained above, the digital controller 4 update~ the PWM controller output signal ~wice per output 20 puls2, thereby independe~ly modulating the position of the l~adinq and ~railing edges of each pulse~ and con~equently modula~ing the duty cycle of th output pulse~, which have a ~ub~tantially con~tant repetition rate. Therefore, if th~ controller output signal has a pul~e fr~quency of 100 hertzt the ~ignal may be updated a~
a rate of 200 hertz. For ~he purpose of updating the co~troller output signal, th~ digital controller must analyze the Eeedback control signal after filtration from the notch filter 12. If the controller ou~put 3ignal has a pulse frequency of lO0 hertz, and therefore a pulse width modulation update rat~ oE 200 hertz, then the feedback signal qhould be sampled and analyzed at a rate . .
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of not less than 200 hertz to achieve th~ maximum possible rate of response for the sy~tem, as wlll be appreciated by those skilled in the art. It i~ convenient in this case to sample the feedback control signal at the rate corresponding to the update rate of 200 hertz, which is twice the controller output pulse rate of 100 hertz.
A~ indicated above, the anti-aliasing filter 10, a well ~nown is the art, iq desig~ed to attenuate unwanted high frequency componen~s in the feedback control signal that would otherwise cause false responses in the sampling circuit. Thi~ happen3 when a signal is ~ampled at less than approximately twi~e the highest frequency of interest in the signal to be sampled. For instance, if a 180 hertz signal i~ sampled at a 200 hertz rate, the samplin~ will indicate a 20 hertz ~ignal, which iq false.
Therefore, in the cas~ of the controller ~y~tem described above wi~h a 200 hertz sampling rate, all freguencies above slightly le s than 100 hertz ~hould be removed by the anti-aliasing filter 10. The frequenci~ of interest, .
which correspond to the duty cycle changes of the controller output pulse train, are all below thi~ 100 hertz cut-off frequency.
~ owever, the anti-aliasing filter 10 i~
generally of an analog low-pass design which i~ not able to attenuate the 100 hertz output pul~ "carrier frequency" component sufficiently without adjusting it to also ~everely attenua~e lower frequency information signal component3 which are of interest. Therefore, a sharply tuned filt~r tun~d to the 100 hertz requenoy, such as the analog notch filter 12, is required.

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~ i~ure 2 i~ a schematic diagram o~ a typical analog arrdngeme.~t which is used for the analog notch filter 12 shown in the system of Figure 1 described above.
The output from the anti-aliasing filter lO is ed to an input terminal 20. The siqnal is fed through two separate resistance-capacitance (R/C) networks, a primary network comprising a resistor 22, a resistor 24 and a capacitor 26, and a secondary network comprising a capaci~or 28, a resistor 30, and a capacitor 32. Their outputs are fed together at a terminal ~4. ~he values of each of the component~ in the two networks are established, using methods well known in the art, to put their respective outputs one hundred eighty degrees out oE phase at the frequency desired to be attenuated, in this case lO0 hertz, so that the lO0 hertz carrier si~nal component should be ~liminated at the terminal 34. Shown are a well known operational amplifier 36 a~d a feedback ne~work comprising re3i~tor~ 38 and 40. The opQrational amplifier 36 provides a buffered output on a ~erminal 42, and resi~tvrs 38 and 40 are selected to control the "sharpne ~" o the notch. The output of the networks on the ter~inal 34 i9 ed to the non-inverting input of the ope~ational a~plifier 36.
The operational amplifier 36 serves a3 a buffer, 25 so that a load placed on the output of the entire buffered notch filter 12 will not adv~rs~ly affect the fllter response characterlstic A typical graphical representation of the amplitude and phase characteristic3 of this type of filter is ~hown in Figure 3. A curve 44 represent the amplitude response of the filter 1~ as a function of frequency. A curve 46 represent~ the phase response of the filter 12 as a function of frequency.

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~ nfortunate}y, such a filter. a~ the analog notch filter 12 requires expensive, ti~ht tolerance components for its implementation, and changes in operating conditions, such a3 temperature and humidity changes, can shift the notch frequency sufficiently to make the filter 12 ineffectiv~, a~ can be appreciated by the steepness of the amplitude versus frequency cu~ve 44 shown in Figure 3.
The present invention is ea~ily incorporated in~o a system as des~ribed above with a minimum of alteration to the system configuration, as shown in Figure 4~ The electro-hydraulic valve system 6, transducer 8, and analog anti-aliasing filter 10 remain unchanged, and operate as described above in connection with the system of Figure 1. However, a digital controller 48 replaces the digi~al.controller 4, and it comprises a modified ver~ion of the digital controller 4, differing only in that a digital notch ~ilter 50 according to the pre~ent invention filters the 100 hertz car~ier signal component from th~ outpu~ of the A/D converter 14 and feed~ this carrier ~requency filter2d ~ignal ~o the input of the clo~ed-loop slgnal controller 16. The A/D converte~ 14, clo~ed-loop signal con~roller 16, and double edge PWM
generator 18 remain unchanged, and otherwise funct~on exactly as de~cribed above in connection with t~.e sy~tem ~hown in Figure 1.
The present invention a ~hown in Figure 4 also permits the elimination of the analog notch filter 12, so that th~ filtered output of ~he analog anti-alia~ing filter 10 can be fed directly into thc input of the A/~
converter 14. Although ~hi~ alteration means that the 100 hertz carrier frequency signal component may interact w.:~.
the sampling rate to produce an alia3 ignal, as explaiî.e~

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above, the alias frequency will correspond to the difference between the carrier frequency and the sampling rate frequency. ~owever, in the sy~tem described above, having a 100 hertz carrier frequency and a 200 hertz ~ampling rate frequency, the difference frequency i5 also 100 hertz. Therefore, in this case no corresponding alias signal i9 generated, 50 that the digital notch filter 50 need only filter out the carrier signal component that passe~ through the A~D converter itself, an added }0 advantage to ~his design.
A functional block diagram of the digital notch filter 50 according to the present invention i3 hown in Figure 5. The output of the A/D converter 14 is fed to a digital filter input terminal 52. As explained above, this digitally en~oded signal comprises a seri~ of digitally ~ncod~d ample3 r~presenting the amplitude of ~: the feedback con~rol signal which i3 low-pas3 fil~ered by the anti-aliasing ~ilter 10. ~he output of th~ A/D
converter 14 should orovide ample~ of the feedback control ~ignal a~ a rate of twice the carrier fte~uency to be a~tenuat~d. For instance, with the fe~dback signal including a 100 heftz carrier fr~quency described above, ~` the A/D conv~rter 14 hould provid~ digitally encoded samples of the f~edback ~ignal at a rat~ of 200 hertz.
: 25 The A/D converter output samples are ~imultaneou~ly fed from the t~rminal 52 directly to one input o~ a summing network 54 and the input o~ a d~lay network 56, both networks being designed according to convenience with method~ known in the art. The delay network S6 includes a d~lay which corre~pond~ to the period between ~onsecutive sample~, in thi~ case, 5 milliseconds. The output of the delay network 56 is fed to another input o~ the summing ,. ,: - :.:
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network S4 so that each samp}e which is ~ed directly to ~he summing network 54 i~ compared with its immediately preceding sample which arrives at the summing network 54 . at the same time from the output o~ the delay network 52, having been delayed by on~ sample period. Consequently, the output of the summing network 56 represents the sum of each A/D converter output ~ample combined with immediately preceding sample. The output from the summing network 54 is then fed to the input of a di~iding network 58, which network may be designed according to convenience with methods known in the art. The output of the dividing network 58 on a terminal 60 then represen~s a value oE one half of the summation of each AjD converter ou~put sample summed with it~ immediately preceding sample. Because the sampling rate, as explained above, is twic~ the carrier frequency, each ~ample of the carrier frequency will be out of phas~ with it~ immediately preceding one.
Therefore, the summation of such sam~le~ will be zero.
The summation of any other frequency will increa e both above and below the 100 hertz notch frequency in a proportlon tha~ i understandable by those skilled in the art.
Figu~e 6 i~ a flow chart representing the methodology of ~h~ invention of the digital notch filter 46 ~hown in Figure 5. After the Eil~ering operation is ~tarted, a "last" sample value, repr~ented a~ Pc(N-l), i3 ~et to 0. A "next" filter sampl~ value, r@presented as PC~N), i~ then acc~pted Ero~ the output of ~he A/D
converter 14. A "next" filter output sample, represented by P~f~N), is then determined by summing the last samp1e Pc(N-l) and the next sample PCtN), and then ~ividing the value of the summa~ion in half. The value of the last '. :
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sample Pc(N~ then set to th~ value of the next sample PC~N). The newly set value of the last sample P~(N-1) is then delayed for one sample period. The next ~ilter sample value PC(N) i5 then once again accepted from the output of the A/D converter 14~ The next filter sample value P~(N~ i~ then summed with the delayed la~t sample Pc(N-l), and the summation i9 divided in half to produce the next filter output sample PCf(N).
This process continues with each successive sample provided by the output of the A/D converter 14t so that the previou31y a~cepted ~ample i~ delayed by one sample period and then summed with th~ presently accepted sample, and the summation is divided in half to provide a signal frequency filtered output. ~ explained above, the ~ignal frequency 90 attenuated i one half of the sample rate.
Of cour e, in other application~ where a control ~ystem does not otherwi~e have the A/D converter 14, the digital notch filter sy~te~ according to the present invention can be u~ed by adding any w~11 known ~ampling ~y3tem to the input terminal 48 of the digital notch filter 46 shown in ~igure 5 to provide ignal samples with the de~ired sampling rate. Likewise, when a control sy~tem provide~ ~igna} samples at o~har than the de ired rate, a ~ell known sampling ~ys~em converter can be added to the input terminal 48 ~o convert the provided signal ~a~ple~ to 3ignal ~amples with the de~ire~ sampling rate.
Figure 7 show~ the ampli~ude and phase characteristic~ for a digital filter ~ys~em a~cording to th~ present i~vention.~ described above in connection with Figure~ 5 and 6. A curve 62 represents the ampli~ude re~pon~e of the filter 50 a~ a function of frequency. A

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curve sa represents the phase response of the filter 50 as a function o~ frequency. The perEo~mance oE the digital notch filter ~y~tem approximates that o the analog notch .:
filter qy~tem shown in Figure 3. However, well known clock syn hronization methodology may be used to : synchroni2e the digi~al components of the digital notch ~ilter 50 to a reference clock for loeking the 100 hz notch frequency. Therefore, a deep 100 hz notch i~
~ecured with fre~dom from frequency drift problems normally asRociated with analog filter components used in the analag filter 12.
Therefore, there has bean de~cribed herein a ~ methsd and apparatus for ~iltering a steady-sta~e : frequency component out of a signal u~ing a digital sampling technique. It will be understood that various changes in the detail3, arrangements and configuration~ of parts ~nd ~y~tems which have been herein deqcribed and illustrated in order to explain the nature of the invention may be made by tho~e skilled in ~h~ art within the principl~ and scope of the invention a~ expres~ed in the appended ~laim~.
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Claims (11)

1. In a system employing samples of an information signal having a steady-state, "carrier frequency" signal component, and information frequency signal components having frequencies different from the frequency of said carrier frequency signal component, a method for filtering said information signal to remove said carrier frequency signal component from said information signal samples, comprising the steps of:
sampling the amplitude of said information signal at a rate corresponding in frequency to twice that of said carrier frequency signal component to form a series of information signal samples;
summing each of said information signal samples with its preceding one of said information signal samples to form a corresponding series of information signal sample summations; and dividing each of said sample summations by two to form a corresponding series of carrier frequency filtered information signal samples.

2. The method recited in Claim 1, wherein said step of sampling comprises the steps of:
measuring the amplitude of said information signal at said sampling rate to form a series of information signal measurements; and converting each of said information signal measurements to a corresponding digital code measurement value to form aid series of information signal samples, each with a corresponding digital code measurement value.

3. The method recited in Claim 2, wherein the step of summing comprises the steps of:
reading the digital code measurement value of each one of aid series of information signal samples to form a series of corresponding sample readings; and summing each of said sample readings with its preceding sample reading to form said series of information signal sample summations.

4. The method recited in Claim 3, further comprising the step of attenuating signal components of said information signal having frequencies higher than the frequency of said carrier frequency signal component.

5. The method recited in Claim 4, wherein:
said step of attenuating comprises the step of low pass filtering a pulse width modulated information signal;
said step of sampling comprises the step of sampling said pulse width modulated information signal; and said step of dividing comprises the step of converting each of said control signal summations to a digital code measurement value after division to form said series of carrier frequency signal filtered information signal samples, each with a corresponding digital code measurement value.

6. In a system employing samples of an information signal having a steady-state, "carrier frequency," signal component, and information frequency signal components having frequencies different from the frequency of said carrier frequency signal component, an apparatus for filtering said information signal to remove said carrier frequency signal component from said information signal samples, comprising:
means for sampling the amplitude of said information signal at a rate corresponding in frequency to twice that of said carrier frequency signal component to form a series of information signal samples;
means for summing each of said control signal samples with its preceding one of said information signal samples to form a corresponding series of information signal sample summations; and means for dividing each of said sample summations by two to form a corresponding series of carrier frequency filtered information signal samples.

7. The apparatus recited in Claim 6, wherein said means for sampling comprises:
means for measuring the amplitude of said information signal at said sampling rate to form a series of information signal measurements; and means for converting each of said information signal measurements to a corresponding digital code measurement value to form said series of information signal samples, each with a corresponding digital code measurement value.

8. The apparatus recited in Claim 7, wherein said means for summing comprises:
means for reading the digital code measurement value of each one of said series of information signal samples to form a series corresponding sample readings; and means for summing each of said sample readings with its preceding sample reading to form said series of information signal sample summations.

9. The apparatus recited in Claim 8, further comprising means for attenuating signal components of said control signal having frequencies higher than the frequency of said carrier frequency signal component.

10. The apparatus recited in Claim 9, wherein:
said means for attenuating comprises means for low-pass filtering a pulse-width modulated information signal;
said means for sampling comprises means for sampling said pulse width modulated signal; and said means for dividing comprises means for converting each of said information signal summations to a digital code measurement value after division to form said series of carrier frequency filtered information signal samples, each with a corresponding digital code measurement value.

11. In a system employing samples of an information signal having a steady-state, "carrier frequency," signal component, and information frequency signal components, an apparatus for filtering said information signal to remove said carrier frequency signal component from said information signal samples, comprising:
an analog to digital converter having a sampling rate with a sampling frequency twice that of said carrier frequency signal component to form a series of information signal samples;
a delay network for delaying each one of said control signal samples by one sample period of said analog to digital converter to form a corresponding series of delayed information signal samples;
a summing network for summing each of said information signal sample from said analog to digital converter with its immediately preceding information signal sample from said delay network to form a corresponding series of information signal sample summations; and a dividing network for dividing each one of said information signal sample summations by two to form a corresponding series of carrier frequency filtered information signal samples.