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CA2008499A1 - Methode pour la formation d'une couche d'oxyde isolante - Google Patents

Methode pour la formation d'une couche d'oxyde isolante

Info

Publication number
CA2008499A1
CA2008499A1 CA2008499A CA2008499A CA2008499A1 CA 2008499 A1 CA2008499 A1 CA 2008499A1 CA 2008499 A CA2008499 A CA 2008499A CA 2008499 A CA2008499 A CA 2008499A CA 2008499 A1 CA2008499 A1 CA 2008499A1
Authority
CA
Canada
Prior art keywords
isolating oxide
formation
locations
layer
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2008499A
Other languages
English (en)
Other versions
CA2008499C (fr
Inventor
Alexander Kalnitsky
Sing Pin Tay
Joseph Paul Ellul
Roger Samuel Abbott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Publication of CA2008499A1 publication Critical patent/CA2008499A1/fr
Application granted granted Critical
Publication of CA2008499C publication Critical patent/CA2008499C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/911Differential oxidation and etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
CA002008499A 1989-06-22 1990-01-24 Methode pour la formation d'une couche d'oxyde isolante Expired - Fee Related CA2008499C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US370,319 1989-06-22
US07/370,319 US4968641A (en) 1989-06-22 1989-06-22 Method for formation of an isolating oxide layer

Publications (2)

Publication Number Publication Date
CA2008499A1 true CA2008499A1 (fr) 1990-12-22
CA2008499C CA2008499C (fr) 1993-08-17

Family

ID=23459150

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002008499A Expired - Fee Related CA2008499C (fr) 1989-06-22 1990-01-24 Methode pour la formation d'une couche d'oxyde isolante

Country Status (2)

Country Link
US (1) US4968641A (fr)
CA (1) CA2008499C (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2565213B2 (ja) * 1989-10-27 1996-12-18 ソニー株式会社 読み出し専用メモリ装置
US5075245A (en) * 1990-08-03 1991-12-24 Intel Corporation Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps
US5393647A (en) * 1993-07-16 1995-02-28 Armand P. Neukermans Method of making superhard tips for micro-probe microscopy and field emission
US5654227A (en) * 1996-01-23 1997-08-05 Micron Technology, Inc. Method for local oxidation of silicon (LOCOS) field isolation
JPH10284478A (ja) * 1997-04-07 1998-10-23 Miyazaki Oki Electric Co Ltd 半導体装置の製造方法
US5998277A (en) * 1998-03-13 1999-12-07 Texas Instruments - Acer Incorporated Method to form global planarized shallow trench isolation
KR100589490B1 (ko) * 2003-12-30 2006-06-14 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
KR100577607B1 (ko) * 2004-07-27 2006-05-10 삼성전자주식회사 반도체 장치용 웰 형성 방법 및 이를 포함하는 반도체장치의 제조 방법
US8350365B1 (en) * 2011-01-13 2013-01-08 Xilinx, Inc. Mitigation of well proximity effect in integrated circuits
US10515896B2 (en) 2017-08-31 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor device and methods of fabrication thereof

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA826343A (en) * 1969-10-28 Kooi Else Methods of producing a semiconductor device and a semiconductor device produced by said method
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
US3765935A (en) * 1971-08-10 1973-10-16 Bell Telephone Labor Inc Radiation resistant coatings for semiconductor devices
NL7706802A (nl) * 1977-06-21 1978-12-27 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.
JPS5587444A (en) * 1978-12-26 1980-07-02 Fujitsu Ltd Method of forming insulating film on semiconductor surface
US4277320A (en) * 1979-10-01 1981-07-07 Rockwell International Corporation Process for direct thermal nitridation of silicon semiconductor devices
JPS5737830A (en) * 1980-08-19 1982-03-02 Mitsubishi Electric Corp Manufacture of semiconductor device
NL187328C (nl) * 1980-12-23 1991-08-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
JPS58106846A (ja) * 1981-12-18 1983-06-25 Nec Corp 半導体装置の製造方法
US4528211A (en) * 1983-11-04 1985-07-09 General Motors Corporation Silicon nitride formation and use in self-aligned semiconductor device manufacturing method
US4569117A (en) * 1984-05-09 1986-02-11 Texas Instruments Incorporated Method of making integrated circuit with reduced narrow-width effect
US4551910A (en) * 1984-11-27 1985-11-12 Intel Corporation MOS Isolation processing
JPS61184833A (ja) * 1985-02-12 1986-08-18 Mitsubishi Electric Corp 半導体装置の製造方法
JPS61226942A (ja) * 1985-04-01 1986-10-08 Matsushita Electronics Corp 半導体集積回路の素子間分離方法
JPS62293728A (ja) * 1986-06-13 1987-12-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4707455A (en) * 1986-11-26 1987-11-17 General Electric Company Method of fabricating a twin tub CMOS device
US4740483A (en) * 1987-03-02 1988-04-26 Motorola, Inc. Selective LPCVD tungsten deposition by nitridation of a dielectric

Also Published As

Publication number Publication date
US4968641A (en) 1990-11-06
CA2008499C (fr) 1993-08-17

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