CA1227884A - Memory array - Google Patents

Abstract

ABSTRACT

A memory array includes a pair of memories of which the one is always synchronously addressable by a cyclical addressing means, the other memory being synchronously addressable during a read phase by the cyclical address in means, and asynchronously addressable by an externally connectable address bus during a write phase, the one memory being in a write phase writing data read from the other memory whilst the latter is in its read phase, and otherwise in a read phase, whereby one memory is always available for the cyclical reading of data.

Description

I

This invention relates -to a memory array which ma be used for example in conjunction with a digital processor for the synthesis of complex analog waveforms or their numerical representations.

The synthesis of complex waveforms finds its best known application in the field of musical performance as in electronic organs and synthesizers, although such wave-forms also have actual or potential applications for example in industrial robotics, navigational control soys-terms, computer aided design and manufacture, synthesis of acoustical phenomena, voice synthesis, telecommunica-lions, audio signal processing and environmental control systems. Typically a synthesizer for such purposes requires a multiple channel capability, and must be capable of producing waveforms with frequency components extending to and beyond the upper end of the audio ire-quench range.

Numerous proposals have been made for digital synthesis of such waveforms. problem common to these proposals is that multiple channel operation involves either plural synthesizers or some form of time division multiplexed operation. The first of these alternatives obviously entails added complexity and expense, whilst the latter I

requires a greatly increased system clock frequency according to the number of channels to be accommodated.
This in turn requires either compromises in performance to keep the system clock frequency down to a reasonable level, the development of special synthesis methods designed to operate at relatively lower clock frequencies, generally with a penalty in flexibility and complexity and requiring custom LSI for the implementation at reason-able cost (thus ruling out their use in relatively small volume applications), or the use of components capable of operating very high clock frequencies, with a penalty in expense and power consumption. A further problem arises when it is desired to implement the synthesis under con-trot of a conventional micro-computer, since available microprocessor chips are simply not fast enough to eye-cute high performance synthesis of multiplexed waveforms of the complexity contemplated by the present inventor.

There is described herein a coprocessor capable of operating under control of a computer, which is portico-laxly suited for the generation of digitized multiplexed complex waveforms using techniques which can be externally defined, and may include both a wide range of known techniques and any future technology which may be devil-owed within the capabilities of the processor, as well as permitting certain new techniques through the use of feedback within the processor itself.

The present invention relates to a memory array which allows transfer of data between a controlling computer and the coprocessor in an asynchronous manner.

Al 2;c~

According to the invention, a memory array comprises a first addressable read/write memory having data and address buses, a second similarly addressable read/write memory having data and address buses, a cyclical address cJerlera-ion connected to said second memory address bus, and control means operative in a first phase, in which said first memory is read enabled and said second memory is write enabled, to connect said first and second memory data buses, and to connect said first and second memory address buses, respectively, and in a second phase in which said first memory is write enabled and said second memory is read enabled, to connect said first memory address bus to a third address bus and said first memory data bus to a third data bus, whereby in said first phase data is read by said cyclical address generator from the first memory and is available on the second memory data bus, and is written by said cyclical address generator from said second memory data bus into said second memory, whereas during said second phase data may be written into said first memory from the third data bus at addresses appearing on the third address bus, and data is read by said cyclical address generator from the second memory and is available on the second memory data bus.

I

Further features of the invention will become apparent from the following description of a preferred embodiment with reference to the accompanying drawings in which:

Figure 1 is a block diagram of the processor; and Figure 2 is a more detailed bloc diagram of the block 4 in Figure 1, also showing certain adjacent blocks.

Referring to Figure 1, the processor comprises five main functional blocks, external data source interface control logic 1, a cycle address generator, control logic and timing bloc 2, an interpolator block 3, a sample genera-ion 4, and an output block 5, operating in conjunction with five principal memory blocks, an update memory a, a cycle memory _, a frequency derivation table memory c, a micro-code memory d and a waveform memory e, and eight buses, discussed further below.

Bus SD is a system data bus, transferring data between the processor and an external data source through a buffer Do, which may ye a muter used to control the processor, or a read only or other memory under suitable control. For the purposes of subsequent description, the external data source is assumed to be a computer. Communication is also had with the external data source by a system address bus So, via a buffer Al carrying address data from the ester-net data source. The five memories referred to above have addresses in the address space of the external data source, as do registers 12 and 13 referred to further below Come monkeyshine with the external data source is completed by conventional control lines 6, 7, 8, 9, for read and write, I synchronization and busy status signals.

I

These communications are controlled by the external data source interface control logic 1, and in order to provide the greatest versatility in a single processor design, this logic is preferably configured in a manner known per so selectively to receive or send data in 8 or 16 bit for mats and receive I 16 or 24 bit addresses, the control lines being polarity reversible. The data and addresses are reconfigured to the same formation the buses SD and SAY regardless of the data source format. In the example described, the bus So has a 16 bit format and the bus SPA
an 11 bit format. The bus SD also has access to an internal cycle address, control and status bus C, of 28 bits in the example described, which coordinates the opera-lions of the main functional blocs 1-5, this access being a control register 10 and a status register 11.

Outputs from the processor are handled by the block 5.
This block may contain the conventional circuits required to receive multiple channels of digital data from the sample generator 4 on a bus S, typically of 16 bit format, and to process this data under control of signals on bus C. Where analog outputs are required, the data will be passed through a digital/analog converter, de-glitches, demultiplexed using sample and hold circuit sand anti-aliasing filtered and the individual channels output-ted separately or combined in any desired manner.

The portions of the processor so far described represent its communications with the outside word and utilize essentially conventional technology. There will now be described those portions of the processor responsible for the generation of the sample appearing on the bus S.
Assuming for example that the processor is to produce 16 channels of output data, each with a frequency response extending to 16 kHz, then a sampling rate in each channel of 32 kHz is appropriate. The sample generator 4 must

2;2~ 34 therefore be capable of generating one 16 bit sample each 1.953 microseconds. Assuming a requirement for execution of any reasonable number of instructions for generation of a sample, this is well beyond the capability of any convent tonal microprocessor, and the problem is aggravated as the number of channels and frequency response required is extended. The processor of the invention is thus provided with a special architecture which takes advantage of the timing structure provided by the output sample rate to generate a number of samples in parallel with thy genera-lion of each such sample reaching a different stage at any particular moment in a coordinated production line type procedure. Operation of this production line procedure is coordinated by timing signals generated in the cycle address generator 2 and applied to the bus C. Assuming for the sake of example a 20.48 MHz clock signal produced by generator C, a single clock cycle is designated a "minor step" with a cycle time of 48.828 no, and the clock is divided down to provide timing signals for "major steps"
20 of 195.3125 no (four minor steps), "minor cycles" of 1.953 microseconds ten major steps), and "major cycles`' of 31.25 microseconds (sixteen minor cycles) corresponding to a repetition rate of 32 KHz. Further division down of the clock is used to provide a selectable "variable pane-meter update cycle rate" providing a timing signal every 8, 16, 32 or 64 major cycles.

It will be appreciated from the foregoing that a sample will be available on the bus S following each minor cycle, and during each major cycle a single sample for each chant not will have appeared successively on the bus S. It should also be appreciated that all of the timings set forth above are dependent upon the basic clock rate, and this may be varied to provide any desired sampling rate within the capabilities of the actual components employed to implement the processor. In the example described, the processor may be implemented using conventional industry standard TTL logic which at least in its higher speed families is capable of handling 20 MHz clock rates.

The sample available on the bus S is generated in the sample generator 4 during a minor cycle. Refer ring now also to Figure 2, this shows a simplified bloc diagram of the functional components of the generator 4 and their interconnections together with surrounding aegis-lens and memories from which the generator can call data. These external registers and memories include the waveform memory e, the scale and offset scale registers f, a, _, 1 and v, registers r, and receiving data from the interpolator 3, and a first-in fist out (FIFO)register 13 receiving data directly from the bus SD. An additional data input is provided from a white noise source in the form of a pseudo-random number generator 16. Internally the generator 4 comprises a 16 bit digital multiplier 14 receiving inputs from buses X and Y, and providing an out-put to a register whose output is connected to a bus B, and a 16 bit arithmetic logic unit Lyle) 15 receiving in-puts from buses A and B, and providing an output to register s whose output is connected to a bus S. Gus A is connected to bus S through register u, and bus S to bus A through registers k, _ and _. Bus B is connected to bus S through register t and bus S to bus B through aegis-ton I. Buy X is connected to bus A through register 1, and bus B to bus X through register a. sup Y is connected to bus B through register _ and bus S is connected to bus Y
through register x, Bus S is also connected to a bus F
through register by. Bus F addresses the waveform memory e through buffer A, and the waveform memory can thus receive address data from bus SPA through a buffer A, or from the outputs of registers z or by or from the selector 12. Data from the waveform memory is output to the bus Y, which can also transfer data in either direction between the waveform memory e and the system data bus SD via a buffer Do, and receive data from register I. Data appearing on bus S can be loaded into a register array cc which has a capacity to store two samples for each channel. Availability of such data is required in the implementation of certain digital filtering techniques.

The inputs and outputs of the various internal registers are enabled, the waveform memory is addressed, the outputs of the various external registers are enabled, and the functions of the multiplier and arithmetic logic unit are selected, all under control of a microprogram which in the example described is of forty steps, and which successively enables operations by the generator which result in genera-lion of a single sample from the data available in the ox-vernal registers and waveform memory. The content of these programs will depend upon the synthesis technique being utilized, and as such forms no part of the invention. Al-though the microprogram has a very limited number of steps, the large variety of external data sources available together with the numerous inter bus connections provided by the internal registers allows great versatility in the execution of known synthesis techniques and the development of new ones.

Microprogram are stored in the microprogram code memory d in the form of 32 bit words transferred at successive minor steps to the control bus C and thence to a decoder 20 with-in the sample generator 4 in which they are vertically de-coded into 52 control bits, each of which controls a part-cuter function in the sample generator. Thus some bits control the loading of registers, some the output of aegis-lens, and some the functions of multipliers 14 and the Ply. Connections between the decoder and the various combo-newts of the sample generator are omitted for the sake of clarity. The memory d is provided in fact with space for more than 40, typically 64 words in each microprogram so as to allow for conditional branches within a microprogram.

I

The microprogram are loaded into the memory from the system data bus SD under control of the system address bus SPA via buffer A and are selected under the control of selector 12 and control logic 2 via buffer A. It will be appreciated that any such 40 step microprogram can be executed within a single minor cycle, and the desired rate of sample sync thesis can thus be maintained. Depending upon the complex-fly of the operations to be carried out by a microprogram, it will be understood that it will often be desirable to arrange these operations so that more than one operation can be carried out in parallel in different parts of the generator, a capability which is provided by the internal architecture of the generator. The number of control bits makes possible a very large instruction set, in which a single instruction can in effect simultaneously enable separate operations in different areas of the generator.

The processor is disabled during writing into the memory d to prevent spurious outputs, and the same is true during writing into the memories c and e, for the same reason.
In most applications, these memories will be loaded during initial set up of the processor, and changes will not be necessary during waveform generation. It will however usually be necessary during waveform generation to update from the external data source data relating to variable parameters, and to preprocess some of this data. The memories a and b together form a memory array which enables updating of data relating to variable parameters in a man-nor transparent to the processor. Incoming data from the system data bus SD is applied via a buffer Do to the up-date memory a into which it is written under control of the system address bus A via buffer A. On development of an update timing signal by the block 2, as previously described, the block 2 generates address data which is applied to the cycle memory _ and also to the update memory a via a buffer A, and the data written into the memory a is read out, and transferred to and written into memory b through buffer Do. Typically the memories a and b have a lo or 2X x 16 bit capacity and the address cycle time of the generator 2 occupies one major cycle, i.e. it generates all of the cycle memory addresses in sequence during this period. During data transfer, the buffer Do isolates the update memory from the bus SD, and the buffer A isolates the system address bus from the update memory.
Thus access to the update memory by the external data source is blocked for only one major cycle in each update cycle. During this same period, data is supplied to a variable parameter data mu Do from the update memory a instead of the cycle memory b, and there is thus no inter-eruption of the flow of data to the bus D, which is usually provided from the cycle memory as the generator 2 cyclic-ally generates its addresses during the read phase of the latter memory.

Data in the memories a and _ is typically organized as in the examples shown in Table 1 and 2, in which Table 2 makes provision for possible 32 channel operation. Data from bus D is loaded into a series of registers including the aegis-lens f, I, h, i and 1 to which reference has already been made, the selector 12, and two registers 17 and 18 at in-puts to the interpolator 3. Of these registers, registers v and selector 12 are double buffered for reasons which will become apparent. During the major steps of each minor cycle, the registers are loaded in turn with successive words from the cycle memory in the following order 17, 18, 12, v, f, _, i&j, 17, 18 and this is repeated for success size minor cycles in a major cycle so as successively to load data pertaining to each channel. It will be noted that the registers 17 and 18 are each loaded twice during a minor cycle, the distribution of the data being as set forth in the following table.

REGISTER CHANNEL FORD (see DESTINATION
Table 2) _ _ 17 1 -> 16 0 - to Interpolator as delta value 18 1 -> 16 1 - to Interpolator as Center or Next value 12 1 -I 16 2 - to Register 12 v 1 -I 16 3 - to 'Offset' Register Sample Generator 17 1 -> 16 8 - to Interpolator as delta value 18 1 -> 16 9 - to Interpolator as Next Value f 1 -I 16 4 - to Scale A Register Sample Generator g 1 -> 16 5 - to Scale B Register Sample Generator h 1 -> 16 6 - to Scale C Register Sample Generator i & j 1 -> 16 7 - to Scale D Register Sample Generator It should be noted that the registers other than those delivering data to the interpolator 3 have an extra stage so as to delay the data supplied to them for one minor cycle whilst the interpolator operates as described below upon the data received from the registers 17 and 18 and delivers processed data to the registers r, and z also-elated with the sample generator 4.

It will be understood from the foregoing that during each minor cycle, two pairs each of two variables are supplied to the interpolator 3 sequentially. In the example under discussion, the first pair is related to frequency and the second pair to amplitude. On receipt of the first pair of variables, defining a center or end text) value of ire-quench, and an incremental or delta component of frequency which modifies or modulates that frequency, an arithmetic logic unit in the interpolator carries Owlet the necessary modification or modulation. It will be noted from Tale 2 that Ford O includes bits instructing the interpolator whether to modify or modulate or make no frequency variance (delta off), and instructing the sign of delta where mod-lotion is to be carried out. Once the necessary arithmetic operations have been carried out, an address in the ire-quench derivation table memory c is derived and the address is selected and accessed. During the time required for memory access, the second pair of variables is loaded and subjected to similar operation in the ALUM to derive amply-tune data, which together with frequency data looked up memory c is grated into the registers y and z and r respect lively for access by the simple generator during the following minor cycle. A register 19 makes available feed-back from the bus S in the sample generator, which in con-lo lain modes of operation may be used as amplitude pa in the interpolator 3.

From the foregoing, it will be appreciated that variable parameter data on the bus D is processed in two phases, each occupying one minor cycle. During the first phase, the interpolator 3 carries out preprocessing of frequency and amplitude information, while during the second phase, the sample generator 4 takes the preprocessed and other data and completes the generation of a sample. In the meanwhile, the interpolator preprocesses data for the following sample, and so on. The arrangement still further enhances the rate at which the processor can produce samples at a given rate and resolution, without decreasing the system clock frequency.

In use, the system is set up by selecting its configuration where selectable, e.g. to Suit the external data Sirius defining the method of synthesis to be used in each channel and the data required, defining for each channel the opera-lions to be carried out on that data by the interpolator 3 (amplitude and/or frequency modification or modulation) and by the sample generator 4, i.e. the operations to be carried I

out by the relevant microprogram, organizing these opera-lions into a practical sequence which can be executed by the sample generator whilst if necessary us g penal-lot execution of these operations, generating a suitable microprogram to control execution of these operations, down loading the microprogram from the external data source to the micro-code memory d, and loading the memories c and e if not in the form of read only memory. During operation, variable parameter data for the various channels is configured by the external data source and loaded into the update memory a, using the buses SD and SAY The memory a can be updated at any time except when its contents are being transferred to the cycle mimicry, and its operation is asynchronous except during this transfer operation, at which time it is synchronized with the cycle memory address sequence so as to allow uninterrupted access of the process son to the variable parameter data.

Claims (2)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A memory array comprising a first addressable read/
write memory having data and address buses, a second similarly addressable read/write memory having data and address buses, a cyclical address generator connected to said second memory address bus, and control means opera-live in a first phase, in which said first memory is read enabled and said second memory is write enabled, to connect said first and second memory data buses, and to connect said first and second memory address buses, rest pectively, and in a second phase in which said first memory is write enabled and said second memory is read enabled, to connect said first memory address bus to a third address bus and said first memory data bus to a third data bus, whereby in said first phase data is read by said cyclical address generator from the first memory and is available on the second memory data bus, and is written by said cyclical address generator from said second memory data bus into said second memory, whereas during said second phase data may be written into said first memory from the third data bus at addresses appearing on the third address bus, and data is read by said cyclical address generator from the second memory and is available on the second memory data bus.

2. A memory array as claimed in Claim 1, including means to transmit a busy signal during said first phase to a source of data and addresses on said third data and address buses.