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AU8298491A - Random access cache memory - Google Patents

Random access cache memory

Info

Publication number
AU8298491A
AU8298491A AU82984/91A AU8298491A AU8298491A AU 8298491 A AU8298491 A AU 8298491A AU 82984/91 A AU82984/91 A AU 82984/91A AU 8298491 A AU8298491 A AU 8298491A AU 8298491 A AU8298491 A AU 8298491A
Authority
AU
Australia
Prior art keywords
random access
cache memory
access cache
memory
random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU82984/91A
Other languages
English (en)
Inventor
Alfred K Chan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MOS Electronics Corp
Original Assignee
MOS Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/678,912 external-priority patent/US5488709A/en
Application filed by MOS Electronics Corp filed Critical MOS Electronics Corp
Publication of AU8298491A publication Critical patent/AU8298491A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU82984/91A 1990-06-27 1991-06-24 Random access cache memory Abandoned AU8298491A (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US678912 1984-12-06
US54607190A 1990-06-27 1990-06-27
US546071 1990-06-27
US67891491A 1991-04-01 1991-04-01
US07/678,912 US5488709A (en) 1990-06-27 1991-04-01 Cache including decoupling register circuits
US678914 1991-04-01

Publications (1)

Publication Number Publication Date
AU8298491A true AU8298491A (en) 1992-01-23

Family

ID=27415469

Family Applications (1)

Application Number Title Priority Date Filing Date
AU82984/91A Abandoned AU8298491A (en) 1990-06-27 1991-06-24 Random access cache memory

Country Status (2)

Country Link
AU (1) AU8298491A (fr)
WO (1) WO1992000590A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69327633T2 (de) * 1992-11-13 2000-08-10 National Semiconductor Corp., Richardson Mikroprozessor mit Adressbereichkonfigurationsystem und Verfahren zur Steuerung von Speichersystemoperationen mittels Adressbereichen
EP0782079A1 (fr) * 1995-12-18 1997-07-02 Texas Instruments Incorporated Accès à rafale en systèmes de traitement de données
US6947748B2 (en) 2000-12-15 2005-09-20 Adaptix, Inc. OFDMA with adaptive subcarrier-cluster configuration and selective loading
WO2004045228A1 (fr) 2002-11-07 2004-05-27 Broadstorm Telecommunications, Inc. Procede et appareil adaptatif d'attribution de porteuses et de gestion de la puissance pour systemes de telecommunications a porteuses multiples
US7573851B2 (en) 2004-12-07 2009-08-11 Adaptix, Inc. Method and system for switching antenna and channel assignments in broadband wireless networks
JP5462068B2 (ja) * 2010-05-12 2014-04-02 アダプティックス インコーポレイテッド マルチキャリヤ通信システム（ｍｕｌｔｉ−ｃａｒｒｉｅｒｃｏｍｍｕｎｉｃａｔｉｏｎｓｙｓｔｅｍ）における適応キャリヤ割り当てと電力コントロール方法及び装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403288A (en) * 1981-09-28 1983-09-06 International Business Machines Corporation Methods and apparatus for resetting peripheral devices addressable as a plurality of logical devices
US4577293A (en) * 1984-06-01 1986-03-18 International Business Machines Corporation Distributed, on-chip cache

Also Published As

Publication number Publication date
WO1992000590A1 (fr) 1992-01-09

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