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AU7550198A - Data processor and data processing method - Google Patents

Data processor and data processing method

Info

Publication number
AU7550198A
AU7550198A AU75501/98A AU7550198A AU7550198A AU 7550198 A AU7550198 A AU 7550198A AU 75501/98 A AU75501/98 A AU 75501/98A AU 7550198 A AU7550198 A AU 7550198A AU 7550198 A AU7550198 A AU 7550198A
Authority
AU
Australia
Prior art keywords
data
processing method
data processing
processor
data processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU75501/98A
Inventor
Kenji Kaneko
Hirotsugu Kojima
Nobuyuki Takei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of AU7550198A publication Critical patent/AU7550198A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Error Detection And Correction (AREA)
  • Optical Recording Or Reproduction (AREA)
AU75501/98A 1998-06-04 1998-06-04 Data processor and data processing method Abandoned AU7550198A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/002476 WO1999063540A1 (en) 1998-06-04 1998-06-04 Data processor and data processing method

Publications (1)

Publication Number Publication Date
AU7550198A true AU7550198A (en) 1999-12-20

Family

ID=14208340

Family Applications (1)

Application Number Title Priority Date Filing Date
AU75501/98A Abandoned AU7550198A (en) 1998-06-04 1998-06-04 Data processor and data processing method

Country Status (4)

Country Link
JP (1) JP3904138B2 (en)
AU (1) AU7550198A (en)
TW (1) TW436724B (en)
WO (1) WO1999063540A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3668673B2 (en) 2000-06-09 2005-07-06 株式会社日立コミュニケーションテクノロジー Error correction code configuration method, decoding method, transmission apparatus, network
US10380024B2 (en) * 2017-12-05 2019-08-13 Nanya Technology Corporation DRAM and method of operating the same in an hierarchical memory system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226930A (en) * 1985-07-26 1987-02-04 Nec Corp Error correction decoder
JPH097365A (en) * 1995-06-23 1997-01-10 Nec Corp Dram-address forming circuit for cd-rom
JPH09115244A (en) * 1995-10-20 1997-05-02 Hitachi Ltd Recording / reproducing apparatus and integrated circuit thereof
JPH09259261A (en) * 1996-03-22 1997-10-03 Toshiba Corp Memory address generator and method

Also Published As

Publication number Publication date
TW436724B (en) 2001-05-28
WO1999063540A1 (en) 1999-12-09
JP3904138B2 (en) 2007-04-11

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase