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AU2018248439C1 - General-purpose parallel computing architecture - Google Patents

General-purpose parallel computing architecture Download PDF

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Publication number
AU2018248439C1
AU2018248439C1 AU2018248439A AU2018248439A AU2018248439C1 AU 2018248439 C1 AU2018248439 C1 AU 2018248439C1 AU 2018248439 A AU2018248439 A AU 2018248439A AU 2018248439 A AU2018248439 A AU 2018248439A AU 2018248439 C1 AU2018248439 C1 AU 2018248439C1
Authority
AU
Australia
Prior art keywords
cores
reducer
coprocessor
computing
core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU2018248439A
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English (en)
Other versions
AU2018248439A1 (en
AU2018248439B2 (en
Inventor
Paul BURCHARD
Ulrich Drepper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Goldman Sachs and Co LLC
Original Assignee
Goldman Sachs and Co LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/481,201 external-priority patent/US11449452B2/en
Application filed by Goldman Sachs and Co LLC filed Critical Goldman Sachs and Co LLC
Publication of AU2018248439A1 publication Critical patent/AU2018248439A1/en
Application granted granted Critical
Publication of AU2018248439B2 publication Critical patent/AU2018248439B2/en
Priority to AU2021203926A priority Critical patent/AU2021203926B2/en
Publication of AU2018248439C1 publication Critical patent/AU2018248439C1/en
Ceased legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5072—Grid computing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/047—Probabilistic or stochastic networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/084—Backpropagation, e.g. using gradient descent
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/088—Non-supervised learning, e.g. competitive learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/09—Supervised learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/01—Probabilistic graphical models, e.g. probabilistic networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/082—Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Health & Medical Sciences (AREA)
  • Biophysics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Molecular Biology (AREA)
  • Computational Linguistics (AREA)
  • General Health & Medical Sciences (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computer Hardware Design (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Algebra (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Neurology (AREA)
  • Computational Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
AU2018248439A 2017-04-06 2018-04-04 General-purpose parallel computing architecture Ceased AU2018248439C1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2021203926A AU2021203926B2 (en) 2017-04-06 2021-06-14 General-purpose parallel computing architecture

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/481,201 US11449452B2 (en) 2015-05-21 2017-04-06 General-purpose parallel computing architecture
US15/481,201 2017-04-06
PCT/US2018/026108 WO2018187487A1 (fr) 2017-04-06 2018-04-04 Architecture informatique parallèle polyvalente

Related Child Applications (1)

Application Number Title Priority Date Filing Date
AU2021203926A Division AU2021203926B2 (en) 2017-04-06 2021-06-14 General-purpose parallel computing architecture

Publications (3)

Publication Number Publication Date
AU2018248439A1 AU2018248439A1 (en) 2019-10-17
AU2018248439B2 AU2018248439B2 (en) 2021-06-03
AU2018248439C1 true AU2018248439C1 (en) 2021-09-30

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
AU2018248439A Ceased AU2018248439C1 (en) 2017-04-06 2018-04-04 General-purpose parallel computing architecture
AU2021203926A Ceased AU2021203926B2 (en) 2017-04-06 2021-06-14 General-purpose parallel computing architecture

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU2021203926A Ceased AU2021203926B2 (en) 2017-04-06 2021-06-14 General-purpose parallel computing architecture

Country Status (6)

Country Link
EP (1) EP3607454A4 (fr)
JP (2) JP7173985B2 (fr)
CN (1) CN110720095A (fr)
AU (2) AU2018248439C1 (fr)
CA (1) CA3059105A1 (fr)
WO (1) WO2018187487A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102793518B1 (ko) * 2019-11-18 2025-04-11 에스케이하이닉스 주식회사 신경망 처리 회로를 포함하는 메모리 장치
CN113407238B (zh) * 2020-03-16 2024-09-24 北京灵汐科技有限公司 一种具有异构处理器的众核架构及其数据处理方法
CN112068942B (zh) * 2020-09-07 2023-04-07 北京航空航天大学 一种基于单节点模拟的大规模并行系统模拟方法
CN114356541B (zh) * 2021-11-29 2024-01-09 苏州浪潮智能科技有限公司 一种计算核心的配置方法及装置、系统、电子设备
EP4451044A1 (fr) 2023-04-20 2024-10-23 Black Semiconductor GmbH Dispositif de modulation des ondes électromagnetiques et son procédé de fabrication
EP4516736A1 (fr) 2023-09-01 2025-03-05 Black Semiconductor GmbH Structure en couches et procédé de production de graphène
EP4531115A1 (fr) 2023-09-27 2025-04-02 Black Semiconductor GmbH Composant optoélectronique doté d'un trou d'interconnexion électrique se connectant à une couche conductrice électrique par l'intermédiaire de deux couches diélectriques
EP4530709A1 (fr) 2023-09-27 2025-04-02 Black Semiconductor GmbH Procédé de fabrication de surfaces planarisées dans des structures en couches utilisées pour la fabrication de dispositifs optoélectroniques
CN118590497B (zh) * 2024-08-02 2024-10-11 之江实验室 一种基于异构通信的全归约通信方法及装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160342568A1 (en) * 2015-05-21 2016-11-24 Goldman, Sachs & Co. General-purpose parallel computing architecture

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
JPH0535867A (ja) * 1990-09-06 1993-02-12 Matsushita Electric Ind Co Ltd 画像処理装置
JPH05242065A (ja) * 1992-02-28 1993-09-21 Hitachi Ltd 情報処理装置及びシステム
JP2561028B2 (ja) * 1994-05-26 1996-12-04 日本電気株式会社 サイドローブキャンセラ
US6829697B1 (en) * 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
TWI234737B (en) * 2001-05-24 2005-06-21 Ip Flex Inc Integrated circuit device
US8756264B2 (en) * 2006-06-20 2014-06-17 Google Inc. Parallel pseudorandom number generation
JP5684704B2 (ja) * 2008-05-27 2015-03-18 スティルウォーター スーパーコンピューティング インコーポレイテッド 実行エンジン
JP5776688B2 (ja) * 2010-04-30 2015-09-09 日本電気株式会社 情報処理装置及びタスク切り替え方法
US8949577B2 (en) * 2010-05-28 2015-02-03 International Business Machines Corporation Performing a deterministic reduction operation in a parallel computer
US20150261535A1 (en) * 2014-03-11 2015-09-17 Cavium, Inc. Method and apparatus for low latency exchange of data between a processor and coprocessor
US9896124B2 (en) * 2014-05-30 2018-02-20 Mitsubishi Electric Corporation Steering control apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160342568A1 (en) * 2015-05-21 2016-11-24 Goldman, Sachs & Co. General-purpose parallel computing architecture

Also Published As

Publication number Publication date
AU2021203926B2 (en) 2022-10-13
EP3607454A1 (fr) 2020-02-12
JP2020517000A (ja) 2020-06-11
JP2023015205A (ja) 2023-01-31
EP3607454A4 (fr) 2021-03-31
CN110720095A (zh) 2020-01-21
WO2018187487A1 (fr) 2018-10-11
AU2018248439A1 (en) 2019-10-17
AU2021203926A1 (en) 2021-07-08
CA3059105A1 (fr) 2018-10-11
AU2018248439B2 (en) 2021-06-03
JP7173985B2 (ja) 2022-11-17

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FGA Letters patent sealed or granted (standard patent)
MK14 Patent ceased section 143(a) (annual fees not paid) or expired