AU2003214260A1 - Arithmetic unit and adding method - Google Patents

Arithmetic unit and adding method

Info

Publication number: AU2003214260A1
Authority: AU; Australia
Prior art keywords: arithmetic unit; adding method; arithmetic; unit
Prior art date: 2002-04-10
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU2003214260A

Inventor

Astrid Elbe

Norbert Janssen

Holger Sedlak

Jean-Pierre Seifert

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Infineon Technologies AG

Original Assignee

Infineon Technologies AG

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2002-04-10

Filing date

2003-04-01

Publication date

2003-10-20

2003-04-01 Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG

2003-10-20 Publication of AU2003214260A1 publication Critical patent/AU2003214260A1/en

Status Abandoned legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only

Landscapes

Physics & Mathematics (AREA)
General Physics & Mathematics (AREA)
Engineering & Computer Science (AREA)
Computational Mathematics (AREA)
Mathematical Analysis (AREA)
Pure & Applied Mathematics (AREA)
Theoretical Computer Science (AREA)
Computing Systems (AREA)
Mathematical Optimization (AREA)
General Engineering & Computer Science (AREA)
Complex Calculations (AREA)
Compression, Expansion, Code Conversion, And Decoders (AREA)

AU2003214260A 2002-04-10 2003-04-01 Arithmetic unit and adding method Abandoned AU2003214260A1 (en)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
DE10215785A DE10215785A1 (en)	2002-04-10	2002-04-10	Calculator and method for adding
DE10215785.5		2002-04-10
PCT/EP2003/003402 WO2003085499A1 (en)	2002-04-10	2003-04-01	Arithmetic unit and adding method

Publications (1)

Publication Number	Publication Date
AU2003214260A1 true AU2003214260A1 (en)	2003-10-20

Family

ID=28684911

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU2003214260A Abandoned AU2003214260A1 (en)	2002-04-10	2003-04-01	Arithmetic unit and adding method

Country Status (6)

Country	Link
US (1)	US6965910B2 (en)
EP (1)	EP1485779B1 (en)
AU (1)	AU2003214260A1 (en)
DE (2)	DE10215785A1 (en)
TW (1)	TW591520B (en)
WO (1)	WO2003085499A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE102005011374B3 (en) *	2005-03-11	2006-07-13	Infineon Technologies Ag	Computer drive for addition circuits of cryptographic processors, uses switching stage to switch computational potential through to output
US20140195817A1 (en) *	2011-12-23	2014-07-10	Intel Corporation	Three input operand vector add instruction that does not raise arithmetic flags for cryptographic applications

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4764887A (en) *	1985-08-02	1988-08-16	Advanced Micro Devices, Inc.	Carry-bypass arithmetic logic unit
DE3540800A1 (en) *	1985-11-16	1987-08-13	Standard Elektrik Lorenz Ag	Binary adding cell and fast adding and multiplying unit composed of such binary adding cells
DE3763872D1 (en) *	1986-03-05	1990-08-30	Holger Sedlak	CRYPTOGRAPHY METHOD AND CRYPTOGRAPHY PROCESSOR FOR IMPLEMENTING THE METHOD.
DE3631992A1 (en) *	1986-03-05	1987-11-05	Holger Sedlak	Cryptography method and cryptography processor to carry out the method
US4691124A (en) *	1986-05-16	1987-09-01	Motorola, Inc.	Self-compensating, maximum speed integrated circuit
US4851995A (en) *	1987-06-19	1989-07-25	International Business Machines Corporation	Programmable variable-cycle clock circuit for skew-tolerant array processor architecture
FR2628232B1 (en) *	1988-03-07	1994-04-08	Etat Francais Cnet	RECURSITIVE TYPE ADDITIONER FOR CALCULATING THE SUM OF TWO OPERANDS
US4905180A (en) *	1988-12-16	1990-02-27	Intel Corporation	MOS adder with minimum pass gates in carry line
US5337269A (en) *	1993-03-05	1994-08-09	Cyrix Corporation	Carry skip adder with independent carry-in and carry skip paths
KR100197354B1 (en) *	1995-06-28	1999-06-15	김영환	Carry-Up Adder Using Clock Phase
US6735612B1 (en) *	1997-06-24	2004-05-11	International Business Machines Corporation	Carry skip adder
JPH11143685A (en) *	1997-06-24	1999-05-28	Internatl Business Mach Corp <Ibm>	Carry skip adder
US6496846B1 (en) *	1999-07-13	2002-12-17	Hewlett-Packard Company	Conditional carry encoding for carry select adder
US7016932B2 (en) *	2000-10-26	2006-03-21	Idaho State University	Adders and adder bit blocks having an internal propagation characteristic independent of a carry input to the bit block and methods for using the same

2002
- 2002-04-10 DE DE10215785A patent/DE10215785A1/en not_active Withdrawn
2003
- 2003-04-01 AU AU2003214260A patent/AU2003214260A1/en not_active Abandoned
- 2003-04-01 WO PCT/EP2003/003402 patent/WO2003085499A1/en not_active Ceased
- 2003-04-01 EP EP03709821A patent/EP1485779B1/en not_active Expired - Lifetime
- 2003-04-01 DE DE50300875T patent/DE50300875D1/en not_active Expired - Lifetime
- 2003-04-02 TW TW092107560A patent/TW591520B/en active
2004
- 2004-10-06 US US10/959,907 patent/US6965910B2/en not_active Expired - Lifetime

Also Published As

Publication number	Publication date
TW591520B (en)	2004-06-11
US20050097157A1 (en)	2005-05-05
US6965910B2 (en)	2005-11-15
DE10215785A1 (en)	2003-10-30
WO2003085499A1 (en)	2003-10-16
DE50300875D1 (en)	2005-09-01
EP1485779A1 (en)	2004-12-15
TW200305819A (en)	2003-11-01
EP1485779B1 (en)	2005-07-27

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Legal Events

Date	Code	Title	Description
2005-01-06	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase