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AU2003251281A1 - Multilayer substrate metallization for ic interconnection - Google Patents

Multilayer substrate metallization for ic interconnection

Info

Publication number
AU2003251281A1
AU2003251281A1 AU2003251281A AU2003251281A AU2003251281A1 AU 2003251281 A1 AU2003251281 A1 AU 2003251281A1 AU 2003251281 A AU2003251281 A AU 2003251281A AU 2003251281 A AU2003251281 A AU 2003251281A AU 2003251281 A1 AU2003251281 A1 AU 2003251281A1
Authority
AU
Australia
Prior art keywords
interconnection
multilayer substrate
substrate metallization
metallization
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003251281A
Inventor
Li Ming
Fan Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agency for Science Technology and Research Singapore
Original Assignee
Institute of Materials Research and Engineering
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Materials Research and Engineering filed Critical Institute of Materials Research and Engineering
Publication of AU2003251281A1 publication Critical patent/AU2003251281A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
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    • H01L2924/01006Carbon [C]
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/01023Vanadium [V]
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    • H01L2924/01024Chromium [Cr]
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    • H01L2924/01046Palladium [Pd]
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    • H01L2924/01061Promethium [Pm]
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    • H01L2924/01076Osmium [Os]
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    • H01L2924/01079Gold [Au]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
AU2003251281A 2002-06-27 2003-06-26 Multilayer substrate metallization for ic interconnection Abandoned AU2003251281A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SG200203893-3 2002-06-27
SG200203893A SG107600A1 (en) 2002-06-27 2002-06-27 Multilayer substrate metallization for ic interconnection
PCT/SG2003/000154 WO2004004003A1 (en) 2002-06-27 2003-06-26 Multilayer substrate metallization for ic interconnection

Publications (1)

Publication Number Publication Date
AU2003251281A1 true AU2003251281A1 (en) 2004-01-19

Family

ID=29997744

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003251281A Abandoned AU2003251281A1 (en) 2002-06-27 2003-06-26 Multilayer substrate metallization for ic interconnection

Country Status (3)

Country Link
AU (1) AU2003251281A1 (en)
SG (1) SG107600A1 (en)
WO (1) WO2004004003A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US9227257B2 (en) 2012-04-24 2016-01-05 Seagate Technology Llc Laser subassembly metallization for heat assisted magnetic recording
US10692830B2 (en) * 2017-10-05 2020-06-23 Texas Instruments Incorporated Multilayers of nickel alloys as diffusion barrier layers
US11127704B2 (en) * 2017-11-28 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump structure and method of making semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5449955A (en) * 1994-04-01 1995-09-12 At&T Corp. Film circuit metal system for use with bumped IC packages
US6352634B1 (en) * 1998-06-10 2002-03-05 W. C. Heraeus Gmbh & Co. Kg Method for producing a lead-free substrate
US6445069B1 (en) * 2001-01-22 2002-09-03 Flip Chip Technologies, L.L.C. Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor

Also Published As

Publication number Publication date
WO2004004003A1 (en) 2004-01-08
WO2004004003A8 (en) 2004-04-15
SG107600A1 (en) 2004-12-29

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