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AU2002336896A1 - Method for debugging reconfigurable architectures - Google Patents

Method for debugging reconfigurable architectures

Info

Publication number
AU2002336896A1
AU2002336896A1 AU2002336896A AU2002336896A AU2002336896A1 AU 2002336896 A1 AU2002336896 A1 AU 2002336896A1 AU 2002336896 A AU2002336896 A AU 2002336896A AU 2002336896 A AU2002336896 A AU 2002336896A AU 2002336896 A1 AU2002336896 A1 AU 2002336896A1
Authority
AU
Australia
Prior art keywords
debugging
reconfigurable architectures
debugging reconfigurable
architectures
debugger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002336896A
Inventor
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PACT XPP Technologies AG
Original Assignee
PACT XPP Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/967,497 external-priority patent/US7266725B2/en
Application filed by PACT XPP Technologies AG filed Critical PACT XPP Technologies AG
Publication of AU2002336896A1 publication Critical patent/AU2002336896A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G06F11/3656—Debugging of software using additional hardware using a specific debug interface
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)

Abstract

The invention relates to a method for debugging reconfigurable hardware. According to the inventive method, all necessary debug information for each configuration cycle is written into a memory which is then evaluated by the debugger.
AU2002336896A 2001-09-03 2002-09-03 Method for debugging reconfigurable architectures Abandoned AU2002336896A1 (en)

Applications Claiming Priority (23)

Application Number Priority Date Filing Date Title
DE10142904.5 2001-09-03
DE10142894 2001-09-03
DE10142894.4 2001-09-03
DE10142904 2001-09-03
DE10144733.7 2001-09-11
DE10144733 2001-09-11
DE10145795 2001-09-17
DE10145795.2 2001-09-17
US09/967,497 US7266725B2 (en) 2001-09-03 2001-09-28 Method for debugging reconfigurable architectures
US09/967,497 2001-09-28
DE10154259.3 2001-11-05
DE10154259 2001-11-05
DE10202044.2 2002-01-19
DE10202044 2002-01-19
DE10202175 2002-01-20
DE10202175.9 2002-01-20
DE10206856.9 2002-02-18
DE10206856 2002-02-18
DE10207226 2002-02-21
DE10207226.4 2002-02-21
DE10240022 2002-08-27
DE10240022.9 2002-08-27
PCT/DE2002/003278 WO2003023616A2 (en) 2001-09-03 2002-09-03 Method for debugging reconfigurable architectures

Publications (1)

Publication Number Publication Date
AU2002336896A1 true AU2002336896A1 (en) 2003-03-24

Family

ID=45871926

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002336896A Abandoned AU2002336896A1 (en) 2001-09-03 2002-09-03 Method for debugging reconfigurable architectures

Country Status (4)

Country Link
EP (1) EP1449083B1 (en)
AT (1) ATE363098T1 (en)
AU (1) AU2002336896A1 (en)
WO (1) WO2003023616A2 (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
ATE476700T1 (en) 2000-06-13 2010-08-15 Richter Thomas PIPELINE CT PROTOCOLS AND COMMUNICATIONS
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
JP2004517386A (en) 2000-10-06 2004-06-10 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト Method and apparatus
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
EP1537486A1 (en) 2002-09-06 2005-06-08 PACT XPP Technologies AG Reconfigurable sequencer structure
JP7398438B2 (en) 2018-05-11 2023-12-14 ラティス セミコンダクタ コーポレーション Key provisioning system and method for programmable logic devices
EP3791304A4 (en) * 2018-05-11 2022-03-30 Lattice Semiconductor Corporation FAILURE CHARACTERIZATION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
CN112579460B (en) * 2020-12-24 2023-04-14 中国航空工业集团公司西安航空计算技术研究所 Multi-level debugging method based on multi-core embedded system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5425036A (en) * 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5754827A (en) * 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation

Also Published As

Publication number Publication date
WO2003023616A2 (en) 2003-03-20
WO2003023616A3 (en) 2003-12-18
EP1449083B1 (en) 2007-05-23
ATE363098T1 (en) 2007-06-15
WO2003023616A8 (en) 2003-08-21
EP1449083A2 (en) 2004-08-25

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase