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AU2001233226A1 - Memory module with hierarchical functionality - Google Patents

Memory module with hierarchical functionality

Info

Publication number
AU2001233226A1
AU2001233226A1 AU2001233226A AU3322601A AU2001233226A1 AU 2001233226 A1 AU2001233226 A1 AU 2001233226A1 AU 2001233226 A AU2001233226 A AU 2001233226A AU 3322601 A AU3322601 A AU 3322601A AU 2001233226 A1 AU2001233226 A1 AU 2001233226A1
Authority
AU
Australia
Prior art keywords
tier
memory
write
memory cells
redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001233226A
Inventor
Morteza Cyrus Afghahi
Mehdi Hatamian
Esin Terzioglu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/776,028 external-priority patent/US6417697B2/en
Priority claimed from US09/776,263 external-priority patent/US6745354B2/en
Priority claimed from US09/775,477 external-priority patent/US6937538B2/en
Priority claimed from US09/776,029 external-priority patent/US6611465B2/en
Priority claimed from US09/776,220 external-priority patent/US6492844B2/en
Application filed by Broadcom Corp filed Critical Broadcom Corp
Priority claimed from US09/775,701 external-priority patent/US6411557B2/en
Priority claimed from US09/775,475 external-priority patent/US6535025B2/en
Priority claimed from US09/775,476 external-priority patent/US6724681B2/en
Priority claimed from US09/776,262 external-priority patent/US6603712B2/en
Priority claimed from US09/775,478 external-priority patent/US6414899B2/en
Publication of AU2001233226A1 publication Critical patent/AU2001233226A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having <i>(n-1)</i>-tier memory modules, which are coupled with <i>(n)</i>-tier sense amplifiers and <i>(n)</i>-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.
AU2001233226A 2000-02-02 2001-02-02 Memory module with hierarchical functionality Abandoned AU2001233226A1 (en)

Applications Claiming Priority (45)

Application Number Priority Date Filing Date Title
US17986600P 2000-02-02 2000-02-02
US17971800P 2000-02-02 2000-02-02
US17976800P 2000-02-02 2000-02-02
US17977700P 2000-02-02 2000-02-02
US17976500P 2000-02-02 2000-02-02
US17976600P 2000-02-02 2000-02-02
US17986500P 2000-02-02 2000-02-02
US60/179,777 2000-02-02
US60/179,765 2000-02-02
US60/179,768 2000-02-02
US60/179,718 2000-02-02
US60/179,866 2000-02-02
US60/179,766 2000-02-02
US60/179,865 2000-02-02
US19360500P 2000-03-31 2000-03-31
US19360700P 2000-03-31 2000-03-31
US19360600P 2000-03-31 2000-03-31
US60/193,605 2000-03-31
US60/193,607 2000-03-31
US60/193,606 2000-03-31
US21574100P 2000-06-29 2000-06-29
US60/215,741 2000-06-29
US22056700P 2000-07-25 2000-07-25
US60/220,567 2000-07-25
US09/775,478 2001-02-02
US09/775,701 2001-02-02
US09/776,263 US6745354B2 (en) 2000-02-02 2001-02-02 Memory redundancy implementation
PCT/US2001/003342 WO2001057871A2 (en) 2000-02-02 2001-02-02 Memory module with hierarchical functionality
US09/775,475 2001-02-02
US09/775,477 US6937538B2 (en) 2000-02-02 2001-02-02 Asynchronously resettable decoder for a semiconductor memory
US09/775,477 2001-02-02
US09/776,220 2001-02-02
US09/776,029 US6611465B2 (en) 2000-02-02 2001-02-02 Diffusion replica delay circuit
US09/776,028 2001-02-02
US09/776,220 US6492844B2 (en) 2000-02-02 2001-02-02 Single-ended sense amplifier with sample-and-hold reference
US09/776,028 US6417697B2 (en) 2000-02-02 2001-02-02 Circuit technique for high speed low power data transfer bus
US09/775,701 US6411557B2 (en) 2000-02-02 2001-02-02 Memory architecture with single-port cell and dual-port (read and write) functionality
US09/776,262 2001-02-02
US09/776,029 2001-02-02
US09/775,475 US6535025B2 (en) 2000-02-02 2001-02-02 Sense amplifier with offset cancellation and charge-share limited swing drivers
US09/775,476 US6724681B2 (en) 2000-02-02 2001-02-02 Asynchronously-resettable decoder with redundancy
US09/776,263 2001-02-02
US09/775,476 2001-02-02
US09/776,262 US6603712B2 (en) 2000-02-02 2001-02-02 High precision delay measurement circuit
US09/775,478 US6414899B2 (en) 2000-02-02 2001-02-02 Limited swing driver circuit

Publications (1)

Publication Number Publication Date
AU2001233226A1 true AU2001233226A1 (en) 2001-08-14

Family

ID=27586642

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001233226A Abandoned AU2001233226A1 (en) 2000-02-02 2001-02-02 Memory module with hierarchical functionality

Country Status (4)

Country Link
EP (1) EP1264313B1 (en)
AT (1) ATE282887T1 (en)
AU (1) AU2001233226A1 (en)
WO (1) WO2001057871A2 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247479A (en) * 1991-05-23 1993-09-21 Intel Corporation Current sensing amplifier for SRAM
DE69520665T2 (en) * 1995-05-05 2001-08-30 Stmicroelectronics S.R.L., Agrate Brianza Arrangement of non-volatile EEPROM, in particular flash EEPROM
JP3569417B2 (en) * 1996-07-19 2004-09-22 株式会社ルネサステクノロジ Semiconductor memory
US5751648A (en) * 1997-01-31 1998-05-12 International Business Machines Corporation Two stage sensing for large static memory arrays
US6009024A (en) * 1997-03-27 1999-12-28 Matsushita Electric Industrial Co., Ltd. Semiconductor memory
KR100270959B1 (en) * 1998-07-07 2000-11-01 윤종용 Semiconductor memory device

Also Published As

Publication number Publication date
WO2001057871A3 (en) 2002-02-21
ATE282887T1 (en) 2004-12-15
WO2001057871A2 (en) 2001-08-09
EP1264313B1 (en) 2004-11-17
WO2001057871A9 (en) 2002-10-31
EP1264313A2 (en) 2002-12-11

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