AU2001226100A1 - Method for high yield reticle formation - Google Patents
Method for high yield reticle formationInfo
- Publication number
- AU2001226100A1 AU2001226100A1 AU2001226100A AU2610001A AU2001226100A1 AU 2001226100 A1 AU2001226100 A1 AU 2001226100A1 AU 2001226100 A AU2001226100 A AU 2001226100A AU 2610001 A AU2610001 A AU 2610001A AU 2001226100 A1 AU2001226100 A1 AU 2001226100A1
- Authority
- AU
- Australia
- Prior art keywords
- high yield
- reticle formation
- reticle
- formation
- yield
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/302—Controlling tubes by external information, e.g. programme control
- H01J37/3023—Programme control
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/62—Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/30—Electron or ion beam tubes for processing objects
- H01J2237/317—Processing objects on a microscale
- H01J2237/3175—Lithography
- H01J2237/31769—Proximity effect correction
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09676400 | 2000-09-29 | ||
| US09/676,400 US6557162B1 (en) | 2000-09-29 | 2000-09-29 | Method for high yield reticle formation |
| PCT/US2000/035653 WO2002029491A1 (en) | 2000-09-29 | 2000-12-30 | Method for high yield reticle formation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001226100A1 true AU2001226100A1 (en) | 2002-04-15 |
Family
ID=24714351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001226100A Abandoned AU2001226100A1 (en) | 2000-09-29 | 2000-12-30 | Method for high yield reticle formation |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6557162B1 (en) |
| EP (1) | EP1320784A1 (en) |
| JP (1) | JP3957631B2 (en) |
| KR (1) | KR100668192B1 (en) |
| AU (1) | AU2001226100A1 (en) |
| WO (1) | WO2002029491A1 (en) |
Families Citing this family (85)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6529621B1 (en) * | 1998-12-17 | 2003-03-04 | Kla-Tencor | Mechanisms for making and inspecting reticles |
| US6557162B1 (en) | 2000-09-29 | 2003-04-29 | Numerical Technologies, Inc. | Method for high yield reticle formation |
| US6505327B2 (en) | 2001-04-13 | 2003-01-07 | Numerical Technologies, Inc. | Generating an instance-based representation of a design hierarchy |
| JP4451575B2 (en) * | 2001-05-22 | 2010-04-14 | パナソニック株式会社 | WIRING BOARD DESIGN SUPPORT DEVICE, DESIGN SUPPORT METHOD, PROGRAM RECORDING MEDIUM, AND PROGRAM |
| US6721928B2 (en) | 2001-07-26 | 2004-04-13 | Numerical Technologies, Inc. | Verification utilizing instance-based hierarchy management |
| US6560766B2 (en) | 2001-07-26 | 2003-05-06 | Numerical Technologies, Inc. | Method and apparatus for analyzing a layout using an instance-based representation |
| US6735752B2 (en) | 2001-09-10 | 2004-05-11 | Numerical Technologies, Inc. | Modifying a hierarchical representation of a circuit to process features created by interactions between cells |
| US6738958B2 (en) | 2001-09-10 | 2004-05-18 | Numerical Technologies, Inc. | Modifying a hierarchical representation of a circuit to process composite gates |
| US7159197B2 (en) | 2001-12-31 | 2007-01-02 | Synopsys, Inc. | Shape-based geometry engine to perform smoothing and other layout beautification operations |
| US6709879B2 (en) * | 2002-01-02 | 2004-03-23 | United Microelectronics Corporation | Method for inspecting a pattern defect process |
| US7386433B2 (en) | 2002-03-15 | 2008-06-10 | Synopsys, Inc. | Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout |
| US6687895B2 (en) | 2002-07-03 | 2004-02-03 | Numerical Technologies Inc. | Method and apparatus for reducing optical proximity correction output file size |
| AU2003256531A1 (en) * | 2002-07-12 | 2004-02-02 | Cadence Design Systems, Inc. | Method and system for context-specific mask writing |
| US6792592B2 (en) | 2002-08-30 | 2004-09-14 | Numerical Technologies, Inc. | Considering mask writer properties during the optical proximity correction process |
| US7005215B2 (en) | 2002-10-28 | 2006-02-28 | Synopsys, Inc. | Mask repair using multiple exposures |
| US6996790B2 (en) * | 2003-01-30 | 2006-02-07 | Synopsys, Inc. | System and method for generating a two-dimensional yield map for a full layout |
| US7149999B2 (en) * | 2003-02-25 | 2006-12-12 | The Regents Of The University Of California | Method for correcting a mask design layout |
| JP4040515B2 (en) | 2003-03-26 | 2008-01-30 | 株式会社東芝 | Mask setting, mask data creating method and pattern forming method |
| US9002497B2 (en) * | 2003-07-03 | 2015-04-07 | Kla-Tencor Technologies Corp. | Methods and systems for inspection of wafers and reticles using designer intent data |
| JP4068541B2 (en) * | 2003-09-25 | 2008-03-26 | 株式会社東芝 | Integrated circuit pattern verification apparatus and verification method |
| US7315990B2 (en) * | 2004-01-12 | 2008-01-01 | International Business Machines Corporation | Method and system for creating, viewing, editing, and sharing output from a design checking system |
| WO2005081910A2 (en) * | 2004-02-26 | 2005-09-09 | Pdf Solutions, Inc. | Generalization of the photo process window and its application to opc test pattern design |
| US7275226B2 (en) * | 2004-04-21 | 2007-09-25 | International Business Machines Corporation | Method of performing latch up check on an integrated circuit design |
| US7117476B2 (en) * | 2004-06-04 | 2006-10-03 | Texas Instruments Incorporated | Determining feasibility of IC edits |
| US7307001B2 (en) * | 2005-01-05 | 2007-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer repair method using direct-writing |
| US7730432B1 (en) | 2005-03-30 | 2010-06-01 | Tela Innovations, Inc. | Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective |
| US8490043B2 (en) | 2005-05-06 | 2013-07-16 | Tela Innovations, Inc. | Standard cells having transistors annotated for gate-length biasing |
| US7441211B1 (en) | 2005-05-06 | 2008-10-21 | Blaze Dfm, Inc. | Gate-length biasing for digital circuit optimization |
| KR101407913B1 (en) * | 2005-09-26 | 2014-06-17 | 마이크로닉 마이데이터 아베 | Method and system for pattern generation based on multiple types of design data |
| US7266798B2 (en) * | 2005-10-12 | 2007-09-04 | International Business Machines Corporation | Designer's intent tolerance bands for proximity correction and checking |
| US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
| US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
| US7932545B2 (en) | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
| US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
| US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
| US8225261B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
| US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
| US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
| US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
| US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
| US7943967B2 (en) | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
| US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
| US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
| US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
| US7870517B1 (en) | 2006-04-28 | 2011-01-11 | Cadence Design Systems, Inc. | Method and mechanism for implementing extraction for an integrated circuit design |
| DE102006037162B4 (en) * | 2006-08-01 | 2008-08-21 | Qimonda Ag | Method and apparatus and their use for testing the layout of an electronic circuit |
| US8365107B2 (en) * | 2007-01-18 | 2013-01-29 | Nikon Corporation | Scanner based optical proximity correction system and method of use |
| US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
| US8286107B2 (en) | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
| US7888705B2 (en) | 2007-08-02 | 2011-02-15 | Tela Innovations, Inc. | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
| US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
| US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
| US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| US20090300572A1 (en) * | 2008-05-30 | 2009-12-03 | Martin Keck | Method of Correcting Etch and Lithographic Processes |
| MY152456A (en) | 2008-07-16 | 2014-09-30 | Tela Innovations Inc | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
| US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
| US8039176B2 (en) | 2009-08-26 | 2011-10-18 | D2S, Inc. | Method for fracturing and forming a pattern using curvilinear characters with charged particle beam lithography |
| US9323140B2 (en) | 2008-09-01 | 2016-04-26 | D2S, Inc. | Method and system for forming a pattern on a reticle using charged particle beam lithography |
| US20120219886A1 (en) | 2011-02-28 | 2012-08-30 | D2S, Inc. | Method and system for forming patterns using charged particle beam lithography with variable pattern dosage |
| US8057970B2 (en) | 2008-09-01 | 2011-11-15 | D2S, Inc. | Method and system for forming circular patterns on a surface |
| US9341936B2 (en) | 2008-09-01 | 2016-05-17 | D2S, Inc. | Method and system for forming a pattern on a reticle using charged particle beam lithography |
| US7901850B2 (en) | 2008-09-01 | 2011-03-08 | D2S, Inc. | Method and system for design of a reticle to be manufactured using variable shaped beam lithography |
| US8473875B2 (en) * | 2010-10-13 | 2013-06-25 | D2S, Inc. | Method and system for forming high accuracy patterns using charged particle beam lithography |
| US9164372B2 (en) | 2009-08-26 | 2015-10-20 | D2S, Inc. | Method and system for forming non-manhattan patterns using variable shaped beam lithography |
| US9448473B2 (en) | 2009-08-26 | 2016-09-20 | D2S, Inc. | Method for fracturing and forming a pattern using shaped beam charged particle beam lithography |
| US20120278770A1 (en) | 2011-04-26 | 2012-11-01 | D2S, Inc. | Method and system for forming non-manhattan patterns using variable shaped beam lithography |
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| US9612530B2 (en) | 2011-02-28 | 2017-04-04 | D2S, Inc. | Method and system for design of enhanced edge slope patterns for charged particle beam lithography |
| US9034542B2 (en) | 2011-06-25 | 2015-05-19 | D2S, Inc. | Method and system for forming patterns with charged particle beam lithography |
| US9038003B2 (en) | 2012-04-18 | 2015-05-19 | D2S, Inc. | Method and system for critical dimension uniformity using charged particle beam lithography |
| US9343267B2 (en) | 2012-04-18 | 2016-05-17 | D2S, Inc. | Method and system for dimensional uniformity using charged particle beam lithography |
| KR102154105B1 (en) | 2012-04-18 | 2020-09-09 | 디2에스, 인코포레이티드 | Method and system for forming patterns using charged particle beam lithograph |
| US8959463B2 (en) | 2012-11-08 | 2015-02-17 | D2S, Inc. | Method and system for dimensional uniformity using charged particle beam lithography |
| US9141746B1 (en) * | 2014-03-31 | 2015-09-22 | Cadence Design Systems, Inc. | System and method to drag instance master physical shell |
| CN107871034A (en) * | 2017-09-22 | 2018-04-03 | 湖北汽车工业学院 | Multi-objective optimization design method for tolerance allocation based on variable-scale teaching and learning algorithm |
| US10776277B2 (en) | 2017-10-31 | 2020-09-15 | Sandisk Technologies Llc | Partial memory die with inter-plane re-mapping |
| US10290354B1 (en) | 2017-10-31 | 2019-05-14 | Sandisk Technologies Llc | Partial memory die |
| EP4264372A4 (en) * | 2020-12-17 | 2024-09-25 | Applied Materials, Inc. | Use of adaptive replacement maps in digital lithography for local cell replacement |
| CN113420525B (en) * | 2021-08-23 | 2021-11-19 | 苏州贝克微电子有限公司 | Modeling method for establishing chip three-dimensional diffusion model in EDA (electronic design automation) software |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0043863B1 (en) | 1980-07-10 | 1984-05-16 | International Business Machines Corporation | Process for compensating the proximity effect in electron beam projection devices |
| US4520269A (en) * | 1982-11-03 | 1985-05-28 | International Business Machines Corporation | Electron beam lithography proximity correction method |
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| US4895780A (en) | 1987-05-13 | 1990-01-23 | General Electric Company | Adjustable windage method and mask for correction of proximity effect in submicron photolithography |
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-
2000
- 2000-09-29 US US09/676,400 patent/US6557162B1/en not_active Expired - Lifetime
- 2000-12-30 KR KR1020037004536A patent/KR100668192B1/en not_active Expired - Lifetime
- 2000-12-30 EP EP00989614A patent/EP1320784A1/en not_active Withdrawn
- 2000-12-30 AU AU2001226100A patent/AU2001226100A1/en not_active Abandoned
- 2000-12-30 JP JP2002533003A patent/JP3957631B2/en not_active Expired - Fee Related
- 2000-12-30 WO PCT/US2000/035653 patent/WO2002029491A1/en not_active Ceased
-
2003
- 2003-02-19 US US10/369,713 patent/US6968527B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040004385A (en) | 2004-01-13 |
| KR100668192B1 (en) | 2007-01-11 |
| US6557162B1 (en) | 2003-04-29 |
| WO2002029491A1 (en) | 2002-04-11 |
| JP3957631B2 (en) | 2007-08-15 |
| JP2004511013A (en) | 2004-04-08 |
| US6968527B2 (en) | 2005-11-22 |
| EP1320784A1 (en) | 2003-06-25 |
| US20030154461A1 (en) | 2003-08-14 |
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