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AU2001261316A1 - Intent-driven functional verification of digital designs - Google Patents

Intent-driven functional verification of digital designs

Info

Publication number
AU2001261316A1
AU2001261316A1 AU2001261316A AU6131601A AU2001261316A1 AU 2001261316 A1 AU2001261316 A1 AU 2001261316A1 AU 2001261316 A AU2001261316 A AU 2001261316A AU 6131601 A AU6131601 A AU 6131601A AU 2001261316 A1 AU2001261316 A1 AU 2001261316A1
Authority
AU
Australia
Prior art keywords
intent
functional verification
digital designs
driven functional
driven
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001261316A
Inventor
John M. Beardslee
Rajiv Kumar
Christopher R. Morrison
Prakash Narain
Rajeev K. Ranjan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Real Intent Inc
Original Assignee
Real Intent Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/566,683 external-priority patent/US6493852B1/en
Priority claimed from US09/566,682 external-priority patent/US6571375B1/en
Priority claimed from US09/566,692 external-priority patent/US6539523B1/en
Priority claimed from US09/566,684 external-priority patent/US6651228B1/en
Application filed by Real Intent Inc filed Critical Real Intent Inc
Publication of AU2001261316A1 publication Critical patent/AU2001261316A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Stored Programmes (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU2001261316A 2000-05-08 2001-05-08 Intent-driven functional verification of digital designs Abandoned AU2001261316A1 (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US09566682 2000-05-08
US09566692 2000-05-08
US09/566,683 US6493852B1 (en) 2000-05-08 2000-05-08 Modeling and verifying the intended flow of logical signals in a hardware design
US09/566,682 US6571375B1 (en) 2000-05-08 2000-05-08 Determining dependency relationships among design verification checks
US09566684 2000-05-08
US09566683 2000-05-08
US09/566,692 US6539523B1 (en) 2000-05-08 2000-05-08 Automatic formulation of design verification checks based upon a language representation of a hardware design to verify the intended behavior of the hardware design
US09/566,684 US6651228B1 (en) 2000-05-08 2000-05-08 Intent-driven functional verification of digital designs
PCT/US2001/014973 WO2001088765A2 (en) 2000-05-08 2001-05-08 Intent-driven functional verification of digital designs

Publications (1)

Publication Number Publication Date
AU2001261316A1 true AU2001261316A1 (en) 2001-11-26

Family

ID=27504852

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001261316A Abandoned AU2001261316A1 (en) 2000-05-08 2001-05-08 Intent-driven functional verification of digital designs

Country Status (2)

Country Link
AU (1) AU2001261316A1 (en)
WO (1) WO2001088765A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6651228B1 (en) 2000-05-08 2003-11-18 Real Intent, Inc. Intent-driven functional verification of digital designs
US6839884B1 (en) 2001-01-18 2005-01-04 Real Intent, Inc. Hierarchical functional verification
US7124383B2 (en) 2003-05-15 2006-10-17 Cadence Design Systems, Inc. Integrated proof flow system and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175946B1 (en) * 1997-10-20 2001-01-16 O-In Design Automation Method for automatically generating checkers for finding functional defects in a description of a circuit

Also Published As

Publication number Publication date
WO2001088765A2 (en) 2001-11-22
WO2001088765A3 (en) 2002-05-02

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AU2001261316A1 (en) Intent-driven functional verification of digital designs