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AU2001255791A1 - Staggered bitline strapping of a non-volatile memory cell - Google Patents

Staggered bitline strapping of a non-volatile memory cell

Info

Publication number
AU2001255791A1
AU2001255791A1 AU2001255791A AU5579101A AU2001255791A1 AU 2001255791 A1 AU2001255791 A1 AU 2001255791A1 AU 2001255791 A AU2001255791 A AU 2001255791A AU 5579101 A AU5579101 A AU 5579101A AU 2001255791 A1 AU2001255791 A1 AU 2001255791A1
Authority
AU
Australia
Prior art keywords
staggered
memory cell
volatile memory
bitline
strapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001255791A
Inventor
Pau-Ling Chen
Richard M. Fastow
Shane Charles Hollmer
Mark W. Randolph
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001255791A1 publication Critical patent/AU2001255791A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
AU2001255791A 2000-05-16 2001-05-01 Staggered bitline strapping of a non-volatile memory cell Abandoned AU2001255791A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US20440600P 2000-05-16 2000-05-16
US60204406 2000-05-16
US09721031 2000-11-22
US09/721,031 US6538270B1 (en) 2000-05-16 2000-11-22 Staggered bitline strapping of a non-volatile memory cell
PCT/US2001/014130 WO2001088986A2 (en) 2000-05-16 2001-05-01 Staggered bitline strapping of a non-volatile memory cell

Publications (1)

Publication Number Publication Date
AU2001255791A1 true AU2001255791A1 (en) 2001-11-26

Family

ID=26899449

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001255791A Abandoned AU2001255791A1 (en) 2000-05-16 2001-05-01 Staggered bitline strapping of a non-volatile memory cell

Country Status (3)

Country Link
US (1) US6538270B1 (en)
AU (1) AU2001255791A1 (en)
WO (1) WO2001088986A2 (en)

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US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
JP3506668B2 (en) * 2000-11-17 2004-03-15 沖電気工業株式会社 Method of manufacturing read-only nonvolatile memory
US6614692B2 (en) * 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6479348B1 (en) * 2002-03-27 2002-11-12 Advanced Micro Devices, Inc. Method of making memory wordline hard mask extension
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6649971B1 (en) * 2002-08-28 2003-11-18 Macronix International Co., Ltd. Nitride read-only memory cell for improving second-bit effect and method for making thereof
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7026216B2 (en) * 2002-11-15 2006-04-11 Macronix International Co., Ltd. Method for fabricating nitride read-only memory
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060036803A1 (en) * 2004-08-16 2006-02-16 Mori Edan Non-volatile memory device controlled by a micro-controller
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1686592A3 (en) 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
JP2007027760A (en) 2005-07-18 2007-02-01 Saifun Semiconductors Ltd High density nonvolatile memory array and manufacturing method
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US20070048936A1 (en) * 2005-08-31 2007-03-01 Jongoh Kim Method for forming memory cell and periphery circuits
CN100485906C (en) * 2005-09-07 2009-05-06 旺宏电子股份有限公司 Method for forming memory cell and peripheral circuit
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
JP4892215B2 (en) * 2005-09-28 2012-03-07 富士通セミコンダクター株式会社 Semiconductor memory device
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US20070255889A1 (en) * 2006-03-22 2007-11-01 Yoav Yogev Non-volatile memory device and method of operating the device
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US20080239599A1 (en) * 2007-04-01 2008-10-02 Yehuda Yizraeli Clamping Voltage Events Such As ESD
US7590001B2 (en) 2007-12-18 2009-09-15 Saifun Semiconductors Ltd. Flash memory with optimized write sector spares
US7935596B2 (en) * 2008-12-22 2011-05-03 Spansion Llc HTO offset and BL trench process for memory device to improve device performance
US9786719B2 (en) * 2012-03-07 2017-10-10 Micron Technology, Inc. Method for base contact layout, such as for memory

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US5168334A (en) 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5156991A (en) * 1988-02-05 1992-10-20 Texas Instruments Incorporated Fabricating an electrically-erasable, electrically-programmable read-only memory having a tunnel window insulator and thick oxide isolation between wordlines
US5071782A (en) * 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
US6243293B1 (en) * 1992-01-29 2001-06-05 Interuniversitair Micro-Elektronica Centrum Contacted cell array configuration for erasable and programmable semiconductor memories
US5693971A (en) * 1994-07-14 1997-12-02 Micron Technology, Inc. Combined trench and field isolation structure for semiconductor devices
US5801076A (en) * 1995-02-21 1998-09-01 Advanced Micro Devices, Inc. Method of making non-volatile memory device having a floating gate with enhanced charge retention
US5621697A (en) * 1995-06-23 1997-04-15 Macronix International Co., Ltd. High density integrated circuit with bank select structure
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US5768186A (en) * 1996-10-25 1998-06-16 Ma; Yueh Yale High density single poly metal-gate non-volatile memory cell
JP3225916B2 (en) 1998-03-16 2001-11-05 日本電気株式会社 Nonvolatile semiconductor memory device and method of manufacturing the same
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6091094A (en) * 1998-06-11 2000-07-18 Siemens Aktiengesellschaft Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips
US6275414B1 (en) * 2000-05-16 2001-08-14 Advanced Micro Devices, Inc. Uniform bitline strapping of a non-volatile memory cell

Also Published As

Publication number Publication date
WO2001088986A3 (en) 2002-03-21
WO2001088986A2 (en) 2001-11-22
US6538270B1 (en) 2003-03-25

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