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AU2001245511A1 - Method and apparatus for enhancing the performance of a pipelined data processor - Google Patents

Method and apparatus for enhancing the performance of a pipelined data processor

Info

Publication number
AU2001245511A1
AU2001245511A1 AU2001245511A AU4551101A AU2001245511A1 AU 2001245511 A1 AU2001245511 A1 AU 2001245511A1 AU 2001245511 A AU2001245511 A AU 2001245511A AU 4551101 A AU4551101 A AU 4551101A AU 2001245511 A1 AU2001245511 A1 AU 2001245511A1
Authority
AU
Australia
Prior art keywords
enhancing
performance
data processor
pipelined data
pipelined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001245511A
Inventor
Henry A. Davis
Paul Strong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARC International Ltd
Original Assignee
ARC International PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARC International PLC filed Critical ARC International PLC
Publication of AU2001245511A1 publication Critical patent/AU2001245511A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2001245511A 2000-03-10 2001-03-08 Method and apparatus for enhancing the performance of a pipelined data processor Abandoned AU2001245511A1 (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US18842800P 2000-03-10 2000-03-10
US60/188,428 2000-03-10
US18894200P 2000-03-13 2000-03-13
US60/188,942 2000-03-13
US18963400P 2000-03-14 2000-03-14
US60/189,634 2000-03-14
US18970900P 2000-03-15 2000-03-15
US60/189,709 2000-03-15
PCT/US2001/007360 WO2001069378A2 (en) 2000-03-10 2001-03-08 Method and apparatus for enhancing the performance of a pipelined data processor

Publications (1)

Publication Number Publication Date
AU2001245511A1 true AU2001245511A1 (en) 2001-09-24

Family

ID=27497757

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001245511A Abandoned AU2001245511A1 (en) 2000-03-10 2001-03-08 Method and apparatus for enhancing the performance of a pipelined data processor

Country Status (3)

Country Link
US (1) US20020032558A1 (en)
AU (1) AU2001245511A1 (en)
WO (1) WO2001069378A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030088892A (en) * 2001-02-06 2003-11-20 애더란트 테크놀로지스 비.브이. Method and apparatus for handling interrupts
US7313677B2 (en) 2002-12-12 2007-12-25 Arm Limited Processing activity masking in a data processing system
ES2395826T3 (en) * 2004-07-09 2013-02-15 Bae Systems Plc Collision avoidance system
CN100590592C (en) * 2005-01-13 2010-02-17 Nxp股份有限公司 Processor and its instruction issuing method
US9035957B1 (en) * 2007-08-15 2015-05-19 Nvidia Corporation Pipeline debug statistics system and method
US8352714B2 (en) * 2010-01-28 2013-01-08 Lsi Corporation Executing watchpoint instruction in pipeline stages with temporary registers for storing intermediate values and halting processing before updating permanent registers
US9152528B2 (en) * 2010-08-27 2015-10-06 Red Hat, Inc. Long term load generator
US9223714B2 (en) 2013-03-15 2015-12-29 Intel Corporation Instruction boundary prediction for variable length instruction set
JP6225554B2 (en) * 2013-08-14 2017-11-08 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
JP6183251B2 (en) * 2014-03-14 2017-08-23 株式会社デンソー Electronic control unit
GB2539428B (en) * 2015-06-16 2020-09-09 Advanced Risc Mach Ltd Data processing apparatus and method with ownership table
US11403096B2 (en) * 2020-05-11 2022-08-02 Micron Technology, Inc. Acceleration circuitry for posit operations
US11928445B2 (en) * 2022-01-20 2024-03-12 SambaNova Systems, Inc. Compiler for a fracturable data path in a reconfigurable data processor
CN114840371B (en) * 2022-05-07 2025-05-09 龙芯中科技术股份有限公司 Processor performance analysis method, device and electronic device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142633A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Preprocessing implied specifiers in a pipelined processor
JPH077356B2 (en) * 1989-05-19 1995-01-30 株式会社東芝 Pipelined microprocessor
JPH04106653A (en) * 1990-08-28 1992-04-08 Toshiba Corp Parallel processing system
JPH04172533A (en) * 1990-11-07 1992-06-19 Toshiba Corp Electronic computer
JP2943464B2 (en) * 1991-12-09 1999-08-30 松下電器産業株式会社 Program control method and program control device
GB2322210B (en) * 1993-12-28 1998-10-07 Fujitsu Ltd Processor having multiple instruction registers
JPH08171504A (en) * 1994-12-19 1996-07-02 Mitsubishi Denki Semiconductor Software Kk Emulation device
US5598362A (en) * 1994-12-22 1997-01-28 Motorola Inc. Apparatus and method for performing both 24 bit and 16 bit arithmetic
US5737547A (en) * 1995-06-07 1998-04-07 Microunity Systems Engineering, Inc. System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device
US6081885A (en) * 1996-12-20 2000-06-27 Texas Instruments Incorporated Method and apparatus for halting a processor and providing state visibility on a pipeline phase basis
US6012137A (en) * 1997-05-30 2000-01-04 Sony Corporation Special purpose processor for digital audio/video decoding
US6289300B1 (en) * 1998-02-06 2001-09-11 Analog Devices, Inc. Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit
US6658555B1 (en) * 1999-11-04 2003-12-02 International Business Machines Corporation Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline

Also Published As

Publication number Publication date
WO2001069378A2 (en) 2001-09-20
US20020032558A1 (en) 2002-03-14
WO2001069378A9 (en) 2003-01-16
WO2001069378A3 (en) 2002-07-25

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