AU2001243296A1 - Digital cancellation of d/a converter noise in pipelined a/d converters - Google Patents
Digital cancellation of d/a converter noise in pipelined a/d convertersInfo
- Publication number
- AU2001243296A1 AU2001243296A1 AU2001243296A AU4329601A AU2001243296A1 AU 2001243296 A1 AU2001243296 A1 AU 2001243296A1 AU 2001243296 A AU2001243296 A AU 2001243296A AU 4329601 A AU4329601 A AU 4329601A AU 2001243296 A1 AU2001243296 A1 AU 2001243296A1
- Authority
- AU
- Australia
- Prior art keywords
- pipelined
- converters
- digital cancellation
- converter noise
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0673—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using random selection of the elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0687—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using fault-tolerant coding, e.g. parity check, error correcting codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US18420500P | 2000-02-22 | 2000-02-22 | |
| US60184205 | 2000-02-22 | ||
| PCT/US2001/006169 WO2001067614A1 (en) | 2000-02-22 | 2001-02-22 | Digital cancellation of d/a converter noise in pipelined a/d converters |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001243296A1 true AU2001243296A1 (en) | 2001-09-17 |
Family
ID=22675962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001243296A Abandoned AU2001243296A1 (en) | 2000-02-22 | 2001-02-22 | Digital cancellation of d/a converter noise in pipelined a/d converters |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US6734818B2 (en) |
| AU (1) | AU2001243296A1 (en) |
| WO (1) | WO2001067614A1 (en) |
Families Citing this family (63)
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| US7016332B2 (en) * | 2000-12-05 | 2006-03-21 | Science Applications International Corporation | Method and system for a remote downlink transmitter for increasing the capacity of a multiple access interference limited spread-spectrum wireless network |
| US7061891B1 (en) | 2001-02-02 | 2006-06-13 | Science Applications International Corporation | Method and system for a remote downlink transmitter for increasing the capacity and downlink capability of a multiple access interference limited spread-spectrum wireless network |
| WO2002080382A1 (en) | 2001-03-30 | 2002-10-10 | Science Applications International Corporation | Multistage reception of code division multiple access transmissions |
| WO2002101931A2 (en) * | 2001-06-08 | 2002-12-19 | Koninklijke Philips Electronics N.V. | Pipeline ad converter |
| US7006461B2 (en) * | 2001-09-17 | 2006-02-28 | Science Applications International Corporation | Method and system for a channel selective repeater with capacity enhancement in a spread-spectrum wireless network |
| DE60113442T2 (en) * | 2001-10-31 | 2006-01-26 | Freescale Semiconductors, Inc., Austin | Incremental delta analog-to-digital converter |
| AU2003217890A1 (en) * | 2002-03-04 | 2003-09-22 | Stmicroelectronics, N.V. | Coder apparatus for resonant power conversion and method |
| JP2003271693A (en) * | 2002-03-19 | 2003-09-26 | Fujitsu Ltd | Analog-to-digital converter cell, simulation apparatus and simulation method |
| DE60312808D1 (en) * | 2003-01-24 | 2007-05-10 | St Microelectronics Srl | Method for correcting the error caused by a multi-bit DA converter in an AD converter |
| US6784814B1 (en) | 2003-03-07 | 2004-08-31 | Regents Of The University Of Minnesota | Correction for pipelined analog to digital (A/D) converter |
| US20040228545A1 (en) * | 2003-05-12 | 2004-11-18 | Kwang-Bo Cho | Multisampling with reduced bit samples |
| US7356424B2 (en) * | 2003-09-26 | 2008-04-08 | Texas Instruments Incorporated | Diagnostic compiler for pipeline analog-to-digital converter, method of compiling and test system employing the same |
| JP3861874B2 (en) * | 2003-12-16 | 2006-12-27 | 株式会社デンソー | AD converter failure detection device |
| US6861969B1 (en) * | 2004-03-03 | 2005-03-01 | Analog Devices, Inc. | Methods and structures that reduce memory effects in analog-to-digital converters |
| TWI227071B (en) * | 2004-04-13 | 2005-01-21 | Realtek Semiconductor Corp | Pipeline ADC calibrating method utilizing extra ADC module and apparatus thereof |
| US7091894B2 (en) * | 2004-06-12 | 2006-08-15 | L-3 Integrated Systems Company | Systems and methods for analog to digital conversion |
| US6956517B1 (en) * | 2004-06-12 | 2005-10-18 | L-3 Integrated Systems Company | Systems and methods for multi-channel analog to digital conversion |
| GB0423011D0 (en) * | 2004-10-16 | 2004-11-17 | Koninkl Philips Electronics Nv | Method and apparatus for analogue to digital conversion |
| US7187310B2 (en) * | 2005-03-04 | 2007-03-06 | Kamal El-Sankary | Circuit calibration using voltage injection |
| US7280064B2 (en) * | 2005-09-08 | 2007-10-09 | Realtek Semiconductor Corp. | Pipeline ADC with minimum overhead digital error correction |
| US7257040B2 (en) * | 2005-09-27 | 2007-08-14 | Macronix International Co., Ltd. | Fast pre-charge circuit and method of providing same for memory devices |
| US7327295B1 (en) | 2005-10-24 | 2008-02-05 | Cirrus Logic, Inc. | Constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus |
| US7167118B1 (en) | 2005-12-08 | 2007-01-23 | Cirrus Logic, Inc. | Centered-pulse consecutive edge modulation (CEM) method and apparatus |
| US7209067B1 (en) | 2005-12-08 | 2007-04-24 | Cirrus Logic, Inc. | Extended dynamic range consecutive edge modulation (CEM) method and apparatus |
| WO2007096920A1 (en) * | 2006-02-27 | 2007-08-30 | Stmicroelectronics S.R.L. | Multistage analog/digital converter and method for calibrating said converter |
| US7570191B2 (en) * | 2006-06-09 | 2009-08-04 | Cosmic Circuits Private Limited | Methods and systems for designing high resolution analog to digital converters |
| KR100845134B1 (en) * | 2006-11-06 | 2008-07-09 | 삼성전자주식회사 | Pipeline Analog-to-Digital Converters with Digital Automatic Calibration and Their Digital Calibration Methods |
| US7602323B2 (en) * | 2007-04-04 | 2009-10-13 | The Regents Of The University Of California | Digital background correction of nonlinear error ADC's |
| US7525464B2 (en) * | 2007-05-29 | 2009-04-28 | National Semiconductor Corporation | Sigma-delta modulator with DAC resolution less than ADC resolution |
| US9488478B2 (en) * | 2008-06-02 | 2016-11-08 | The Boeing Company | Methods and systems for visual flight rule (VFR) chart generation |
| US7786910B2 (en) * | 2008-08-12 | 2010-08-31 | Analog Devices, Inc. | Correlation-based background calibration of pipelined converters with reduced power penalty |
| US7719452B2 (en) * | 2008-09-23 | 2010-05-18 | Analog Devices, Inc. | Pipelined converter systems with enhanced linearity |
| WO2010041187A1 (en) | 2008-10-06 | 2010-04-15 | Nxp B.V. | A method of gain calibration of an adc stage and an adc stage |
| US8081946B2 (en) * | 2008-12-23 | 2011-12-20 | L-3 Communications Integrated Systems L.P. | Interference cancellation for reconfigurable direct RF bandpass sampling interference cancellation |
| US8078130B2 (en) | 2008-12-23 | 2011-12-13 | L-3 Communications Integrated Systems L.P. | Systems and methods for interference cancellation |
| TWI450500B (en) * | 2009-01-17 | 2014-08-21 | Univ Nat Taiwan | High-speed pipeline analog-to-digital converter at half clock rate |
| EP2237424B1 (en) * | 2009-03-30 | 2013-02-27 | Dialog Semiconductor GmbH | Tri-level dynamic element matcher allowing reduced reference loading and DAC element reduction |
| JP2010268080A (en) * | 2009-05-12 | 2010-11-25 | Canon Inc | Solid-state imaging device |
| US8068045B2 (en) * | 2010-03-01 | 2011-11-29 | Analog Devices, Inc. | Calibration methods and structures for pipelined converter systems |
| JP2011229128A (en) * | 2010-03-31 | 2011-11-10 | Asahi Kasei Electronics Co Ltd | Pipeline type a/d converter |
| US8269661B2 (en) * | 2010-10-14 | 2012-09-18 | Texas Instruments Incorporated | Pipelined ADC having a three-level DAC elements |
| US8368571B2 (en) | 2011-03-31 | 2013-02-05 | Analog Devices, Inc. | Pipelined ADC having error correction |
| US8791844B2 (en) | 2011-06-09 | 2014-07-29 | Microchip Technology Incorporated | Modified dynamic element matching for reduced latency in a pipeline analog to digital converter |
| US8497789B2 (en) | 2011-06-10 | 2013-07-30 | Microchip Technology Incorporated | Modified dynamic element matching for reduced latency in a pipeline analog to digital converter |
| CN102291145A (en) * | 2011-06-21 | 2011-12-21 | 北京交通大学 | Analogue-to-digital conversion method based on Gray encoding and absolute value algorithm |
| US8405537B2 (en) | 2011-08-11 | 2013-03-26 | Pixart Imaging Inc. | Systems, devices and methods for capacitor mismatch error averaging in pipeline analog-to-digital converters |
| US8441378B2 (en) | 2011-08-11 | 2013-05-14 | Pixart Imaging, Inc. | Capacitor mismatch error correction in pipeline analog-to-digital converters |
| US8723707B2 (en) | 2011-11-14 | 2014-05-13 | Analog Devices, Inc. | Correlation-based background calibration for reducing inter-stage gain error and non-linearity in pipelined analog-to-digital converters |
| US9800254B2 (en) | 2015-04-16 | 2017-10-24 | Maxlinear, Inc. | Digital-to-analog converter (DAC) with partial constant switching |
| US9762256B2 (en) * | 2015-04-16 | 2017-09-12 | Maxlinear, Inc. | Digital-to-analog converter (DAC) with enhanced dynamic element matching (DEM) and calibration |
| CN106788437B (en) * | 2015-11-20 | 2024-02-27 | 上海贝岭股份有限公司 | Pipelined analog-to-digital converter and method for increasing sampling rate of analog-to-digital converter |
| US9608655B1 (en) | 2016-02-09 | 2017-03-28 | Analog Devices, Inc. | ADC background calibration with dual conversions |
| US9882575B1 (en) | 2016-10-14 | 2018-01-30 | Analog Devices, Inc. | Analog-to-digital converter with offset calibration |
| US9859907B1 (en) | 2016-10-28 | 2018-01-02 | Analog Devices, Inc. | Systems and methods for removing errors in analog to digital converter signal chain |
| US9912343B1 (en) | 2016-12-07 | 2018-03-06 | Analog Devices, Inc. | Analog to digital converter with background calibration techniques |
| US10547319B2 (en) | 2017-11-01 | 2020-01-28 | Analog Devices, Inc. | Background calibration of reference, DAC, and quantization non-linearity in ADCS |
| US10505561B2 (en) * | 2018-03-08 | 2019-12-10 | Analog Devices Global Unlimited Company | Method of applying a dither, and analog to digital converter operating in accordance with the method |
| US10516408B2 (en) | 2018-03-08 | 2019-12-24 | Analog Devices Global Unlimited Company | Analog to digital converter stage |
| US10511316B2 (en) | 2018-03-08 | 2019-12-17 | Analog Devices Global Unlimited Company | Method of linearizing the transfer characteristic by dynamic element matching |
| US10608655B1 (en) * | 2018-12-06 | 2020-03-31 | Analog Devices, Inc. | Inter-stage gain calibration in double conversion analog-to-digital converter |
| CN110474641B (en) * | 2019-08-20 | 2022-09-20 | 合肥工业大学 | Digital coding circuit and method of analog-to-digital converter applied to ultrahigh-speed pipeline folding interpolation structure |
| GB2604334B (en) * | 2021-02-24 | 2024-04-10 | Satixfy Uk Ltd | Digital beamforming circuitry for trasmit path of electronically steerable antennas |
| CN115133928A (en) * | 2022-06-30 | 2022-09-30 | 中国科学技术大学 | DEM structure for improving dynamic performance of DAC at extremely low temperature |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5210537A (en) | 1991-02-08 | 1993-05-11 | Analog Devices, Incorporated | Multi-stage A/D converter |
| US5248973A (en) | 1991-10-24 | 1993-09-28 | The Mitre Corporation | High-speed, high-resolution analog to digital converter subranging architecture |
| GB9209498D0 (en) * | 1992-05-01 | 1992-06-17 | Univ Waterloo | Multi-bit dac with dynamic element matching |
| US5949361A (en) * | 1997-05-12 | 1999-09-07 | The United States Of America Represented By The Secretary Of The Navy | Multi-stage delta sigma modulator with one or more high order sections |
| US5892472A (en) * | 1997-06-30 | 1999-04-06 | Harris Corporation | Processor controlled analog-to-digital converter circuit |
| US6137431A (en) * | 1999-02-09 | 2000-10-24 | Massachusetts Institute Of Technology | Oversampled pipeline A/D converter with mismatch shaping |
| US6211805B1 (en) * | 1999-09-08 | 2001-04-03 | Texas Instruments Incorporated | Noise shaping dynamic element mismatch in analog to digital converters |
| US6266002B1 (en) * | 1999-09-10 | 2001-07-24 | Cirrus Logic, Inc. | 2nd order noise shaping dynamic element matching for multibit data converters |
| US6456223B1 (en) * | 1999-12-28 | 2002-09-24 | Texas Instruments Incorporated | Pipelined analog to digital converter using digital mismatch noise cancellation |
| US6515611B1 (en) * | 2001-11-06 | 2003-02-04 | Agere Systems Inc. | Multistage analog-to-digital converter with amplifier component swapping for improved linearity |
-
2001
- 2001-02-22 US US09/792,751 patent/US6734818B2/en not_active Expired - Lifetime
- 2001-02-22 WO PCT/US2001/006169 patent/WO2001067614A1/en not_active Ceased
- 2001-02-22 AU AU2001243296A patent/AU2001243296A1/en not_active Abandoned
-
2004
- 2004-05-11 US US10/844,047 patent/US7006028B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001067614A1 (en) | 2001-09-13 |
| US20020041248A1 (en) | 2002-04-11 |
| US7006028B2 (en) | 2006-02-28 |
| US6734818B2 (en) | 2004-05-11 |
| US20050156773A1 (en) | 2005-07-21 |
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