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NO20151297A1 - VHDL authentication component system - Google Patents

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Publication number
NO20151297A1
NO20151297A1 NO20151297A NO20151297A NO20151297A1 NO 20151297 A1 NO20151297 A1 NO 20151297A1 NO 20151297 A NO20151297 A NO 20151297A NO 20151297 A NO20151297 A NO 20151297A NO 20151297 A1 NO20151297 A1 NO 20151297A1
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Norway
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vhdl
commands
sequencer
verification component
dedicated
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NO20151297A
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Norwegian (no)
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Espen Tallaksen
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Bitvis As
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

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Description

Patentsøknad «uwm_patent_l», oppdatert versjon pr. 13.12.2016: Patent application "uwm_patent_l", updated version per 13/12/2016:

Søknadsnr.: 20151297: VHDL verifikasjonskomponentsystem Application no.: 20151297: VHDL verification component system

FAG-uttrykk FAG expression

VHDL- og FPGA-spesifikke uttrykk er brukt i sin opprinnelige form på engelsk og skrevet i kursiv ettersom motsvarende norske synonymer ikke er fullgode erstatninger eller hvor ordet er spesifikt for VHDL eller FPGA. VHDL- and FPGA-specific expressions are used in their original form in English and written in italics as corresponding Norwegian synonyms are not perfect substitutes or where the word is specific to VHDL or FPGA.

Forkortelser og Uttrykk Abbreviations and Expressions

• FPGA: Field Programmable Gate Array (Programmerbar hardware) • FPGA: Field Programmable Gate Array (Programmable hardware)

• VHDL: Very High Speed Integrated Circuit - Hardware Description Language • VHDL: Very High Speed Integrated Circuit - Hardware Description Language

• UVVM: Universal VHDL Verification Methodology • UVVM: Universal VHDL Verification Methodology

• WC: VHDL Verification Component • WC: VHDL Verification Component

• Shared Variable: Global delt variable • Shared Variable: Global shared variable

Beskrivelse Description

UVVM WC Framework er et system og metodikk som åpner for en sterk forbedring og effektivisering av verifikasjon av FPGA-kretser ved hjelp av VHDL testbenker. Dette systemet retter seg først og fremst inn på å detektere clock cycle relaterte designfeil i en FPGA. The UVVM WC Framework is a system and methodology that allows for a strong improvement and streamlining of verification of FPGA circuits using VHDL test benches. This system primarily focuses on detecting clock cycle related design errors in an FPGA.

I dag finnes det ikke noe system eller metodikk for dette - annet en ad-hoc, ustrukturerte, personlige metoder. Det nærmeste man finner et strukturert system er open source systemet "communication" https:// eithub. com/ LarsAsplund/ vunit/ blob/ master/ vhdl/ com/ user guide. md . Dette er et helt generelt og relativt komplekst system, med en høy brukerterskel uten en definert metodikk. Det er i tillegg lite gjenbruksvennlig og vanskelig å vedlikeholde. Alt dette også iberegnet at man selv må bygge mye funksjonalitet på toppen. Today there is no system or methodology for this - other than ad-hoc, unstructured, personal methods. The closest thing to a structured system is the open source system "communication" https:// eithub. com/ LarsAsplund/ vunit/ blob/ master/ vhdl/ com/ user guide. month This is a completely general and relatively complex system, with a high user threshold without a defined methodology. It is also not reusable and difficult to maintain. All of this also includes the fact that you yourself have to build a lot of functionality on top.

UVVM WC Framework har en helt annerledes angrepsvinkel på problemstillingen relatert til det å avdekke feil i en FPGA. I stedet for å sende generelle meldinger mellom forskjellige prosesser og komponenter i en testbenk, så distribuerer U WM WC Framework kommandoer fra en sentral sekvensator ut til autonome verifikasjonskomponenter for å bli utført der. Synkronisering skjer deretter ved at sekvensatoren kan vente på at gitte kommandoer er ferdig utført i en gitt verifikasjonskomponent (WC). Denne kommandodistribusjonen og synkroniseringen utgjør en stor positiv forskjell for brukeren, som får bedre oversikt og lettere kan endre og utvide funksjonaliteten. The UVVM WC Framework has a completely different angle of attack on the problem related to uncovering errors in an FPGA. Instead of sending general messages between different processes and components in a testbench, the U WM WC Framework distributes commands from a central sequencer out to autonomous verification components to be executed there. Synchronization then occurs by allowing the sequencer to wait for given commands to be completed in a given verification component (WC). This command distribution and synchronization makes a big positive difference for the user, who gets a better overview and can more easily change and expand the functionality.

Vi har allerede utviklet et lignende system med andre underliggende mekanismer. Dette har vært prøvd ut hos kunder, men ikke blitt en suksess ettersom det ikke var godt nok i forhold til brukervennlighet, vedlikehold, gjenbruk, osv. Vi har derfor tatt tak i disse problemområdene og funnet helt nye løsninger for UVVM WC Framework, som vil endre brukeropplevelsen vesentlig. Mekanismene og metodikken for de nye løsningene er ikke tidligere publisert. We have already developed a similar system with other underlying mechanisms. This has been tried out with customers, but was not a success as it was not good enough in terms of ease of use, maintenance, reuse, etc. We have therefore tackled these problem areas and found completely new solutions for the UVVM WC Framework, which will significantly change the user experience. The mechanisms and methodology for the new solutions have not previously been published.

I UVVM WC Framework tilbyr verifikasjonskomponentene både kommandoer som er felles for alle verifikasjonskomponenter, og kommandoer som er spesifikke for en gitt WC. I dette systemet er felles kommandoer definert sentralt, mens VVC-dedikerte kommandoer er definert lokalt, noe som ikke har vært praktisk gjennomførbart i forhold til gjenbruk tidligere på grunn av begrensninger i VHDL. UVVM WC Framework forenkler utvidelser og endringer, og gir en vesentlig bedre oversikt - gjennom en mer avansert implementasjon. In the UVVM WC Framework, the verification components offer both commands that are common to all verification components, and commands that are specific to a given WC. In this system, common commands are defined centrally, while VVC-dedicated commands are defined locally, which has not been practically feasible in relation to reuse in the past due to limitations in VHDL. The UVVM WC Framework simplifies extensions and changes, and provides a significantly better overview - through a more advanced implementation.

En annen viktig endring er å skille hardt mellom a) kommandoer som trenger direkte respons i en WC, b) konfigurasjon som ikke trenger direkte respons, og c) status, som kan aksesseres direkte. Den første kategorien (a) blir definert som kommandoer den sentrale sekvensatoren kan distribuere til VVCene via et kommunikasjonssystem, mens konfigurasjon og status (b og c) ikke distribueres som kommandoer, men som direkte signal-tilordninger fra sekvensator til WC eller omvendt. Dette reduserer arbeidet når man ønsker å introdusere mer fleksibilitet og konfigurerbarhet. Another important change is to make a hard distinction between a) commands that need a direct response in a WC, b) configuration that does not need a direct response, and c) status, which can be accessed directly. The first category (a) is defined as commands that the central sequencer can distribute to the VVCs via a communication system, while configuration and status (b and c) are not distributed as commands, but as direct signal assignments from the sequencer to the WC or vice versa. This reduces the work when you want to introduce more flexibility and configurability.

Siste nyvinning er selve kommunikasjonskanalene mellom sekvensator og WC. Det har tidligere vært en utfordring at brukerne ikke har forstått systemets bruk av komplekse signaler for all kommunikasjon. I det nye systemet brukes signaler kun til å indikere at en ny kommando kommer eller er akseptert, samt kommando-adressering. All annen kommunikasjon mellom sekvensator og WC baserer seg på shared variables. Dette er mulig fordi shared variables kun benyttes under en pågående kommunikasjon mellom sekvensator og en gitt WC, og dermed vil både WC og sekvensator vite hva som er kilden til en endring i en shared variable. På denne måten blir det enklere å forstå hva som skjer i systemet. Det vil også gjøre det enklere å gjøre endringer og legge til ny funksjonalitet. The latest innovation is the actual communication channels between sequencer and WC. It has previously been a challenge that users have not understood the system's use of complex signals for all communication. In the new system, signals are only used to indicate that a new command is coming or has been accepted, as well as command addressing. All other communication between sequencer and WC is based on shared variables. This is possible because shared variables are only used during an ongoing communication between sequencer and a given WC, and thus both WC and sequencer will know what is the source of a change in a shared variable. In this way, it becomes easier to understand what is happening in the system. It will also make it easier to make changes and add new functionality.

Claims (5)

1. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verifikasjonskomponentsystem der test-sekvensator kommandoer som er WC (VHDL Verification Component)-dedikerte er definert i en WC-dedikert VHDL-pakke. Selve kommunikasjonen mellom sekvensator og WC skjer via en kombinasjon av direkte signal-tilordning fra sekvensator til WC gjennom et globalt signal for å indikere at en ny kommando kommer, og all annen kommunikasjon fra sekvensator til WC gjennom shared variables. Dermed kan sekvensator sende kommandoer til en WC ved å kalle kommandoer i en WC-dedikert pakke, der denne kommandoen setter opp både det direkte signalet og shared variable. Når det direkte signalet er satt vil WCen se dette og hente all informasjon fra shared varible, og dermed er kommadoen overført til WC. Ettersom systemet bruker et globalt signal og en shared variable, som i VHDL da er synlig og styrbart både fra test-sekvensator og WC, så kan de overføre kommandoer og status seg i mellom via disse.1. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verification component system where test-sequencer commands that are WC (VHDL Verification Component)-dedicated are defined in a WC-dedicated VHDL package. The actual communication between sequencer and WC takes place via a combination of direct signal assignment from sequencer to WC through a global signal to indicate that a new command is coming, and all other communication from sequencer to WC through shared variables. Thus, the sequencer can send commands to a WC by calling commands in a WC-dedicated package, where this command sets up both the direct signal and the shared variable. When the direct signal is set, the WC will see this and retrieve all information from the shared variable, and thus the command is transferred to the WC. As the system uses a global signal and a shared variable, which in VHDL is then visible and controllable both from the test sequencer and WC, they can transfer commands and status between them via these. 2. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verifikasjonskomponentsystem der test-sekvensator kommandoer er tilgjengelig fra alle inkluderte WCer (VHDL Verification Component), samt fra en pakke med felles kommandoer for UVVM (Universal VHDL Verification Methodology) WC Framework. Dette fungerer på samme måte som i patentkrav 1, men i tillegg til VVC-dedikerte pakker som gir WC-dedikerte kommandoer, så er det også definert en pakke med kommandoer som er felles for alle WCer. Disse kommandoene kan kalles på samme måte som i patentkrav 1 og setter opp direkte-signal og shared variable på samme måte, men overfører jo da ikke WC-spesifikke kommandoer til en WC, men generelle felles kommandoer.2. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verification component system where test-sequencer commands are available from all included WCs (VHDL Verification Component), as well as from a package of common commands for UVVM (Universal VHDL Verification Methodology ) WC Framework. This works in the same way as in patent claim 1, but in addition to VVC-dedicated packages that provide WC-dedicated commands, a package of commands that are common to all WCs is also defined. These commands can be called in the same way as in patent claim 1 and set up direct signal and shared variable in the same way, but do not transfer WC-specific commands to a WC, but general common commands. 3. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verifikasjonskomponentsystem der test-sekvensator i tillegg til kommandoer kan konfigurere WC (VHDL Verification Component)-oppførsel gjennom direkte tilgang til en WC-dedikert shared variable ( global delt variabel). Ettersom shared variables er globalt delte variabler vil en shared variable med fullstendig WC-konfigurasjon kunne være WC dedikert, det vil si ligge inne i en WC, og samtidig være fult synlig for sekvensatoren, som dermed får direkte tilgang til denne og kan konfigurere WC-oppførsel direkte.3. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verification component system where the test sequencer in addition to commands can configure WC (VHDL Verification Component) behavior through direct access to a WC-dedicated shared variable (global shared variable). As shared variables are globally shared variables, a shared variable with complete WC configuration could be WC dedicated, i.e. located inside a WC, and at the same time be fully visible to the sequencer, which thus gets direct access to it and can configure the WC behavior directly. 4. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verifikasjonskomponentsystem der test-sekvensator i tillegg til kommandoer kan sjekke WC (VHDL Verification Component) status gjennom direkte tilgang til en WC-dedikert shared variable ( global delt variabel). Dette fungerer på samme måte som for patenkrav 3, men i den andre retningen. I dette tilfellet vil WC-status være direkte tilgjengelig for sekvensatoren, som dermed kan sjekke WC-status direkte.4. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verification component system where, in addition to commands, the test sequencer can check WC (VHDL Verification Component) status through direct access to a WC-dedicated shared variable (global shared variable ). This works in the same way as for patent claim 3, but in the other direction. In this case, the WC status will be directly available to the sequencer, which can thus check the WC status directly. 5. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verifikasjonskomponentsystem der kommunikasjonen mellom test-sekvensator og WCer (VHDL Verification Component) er delt i globale signaler for å trigge en aksjon, og bruk av shared variables ( global delt variabel) for alt annet. Det er denne fordelingen som muliggjør patentkrav 1 og 2, og som gjør hele systemet mer brukervennlig.5. VHDL (VHSIC (Very-High-Speed Integrated Circuit) Hardware Description Language) verification component system where the communication between test sequencer and WCer (VHDL Verification Component) is divided into global signals to trigger an action, and use of shared variables ( global shared variable) for everything else. It is this distribution that enables patent claims 1 and 2, and which makes the whole system more user-friendly.
NO20151297A 2015-10-01 2015-10-01 VHDL authentication component system NO20151297A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040015739A1 (en) * 2001-08-07 2004-01-22 Ulrich Heinkel Testbench for the validation of a device under test
US7505887B1 (en) * 2006-01-31 2009-03-17 Xilinx, Inc. Building a simulation of design block using a bus functional model and an HDL testbench
US7827510B1 (en) * 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US20140189622A1 (en) * 2012-10-19 2014-07-03 Altera Corporation Partitioning designs to facilitate certification

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040015739A1 (en) * 2001-08-07 2004-01-22 Ulrich Heinkel Testbench for the validation of a device under test
US7827510B1 (en) * 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US7505887B1 (en) * 2006-01-31 2009-03-17 Xilinx, Inc. Building a simulation of design block using a bus functional model and an HDL testbench
US20140189622A1 (en) * 2012-10-19 2014-07-03 Altera Corporation Partitioning designs to facilitate certification

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