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NO20081745L - Aritmetisk LLR-krets og -fremgangsmate, og sendeanordning og program - Google Patents

Aritmetisk LLR-krets og -fremgangsmate, og sendeanordning og program

Info

Publication number
NO20081745L
NO20081745L NO20081745A NO20081745A NO20081745L NO 20081745 L NO20081745 L NO 20081745L NO 20081745 A NO20081745 A NO 20081745A NO 20081745 A NO20081745 A NO 20081745A NO 20081745 L NO20081745 L NO 20081745L
Authority
NO
Norway
Prior art keywords
llr
circuit
decision bit
hard
coordinates
Prior art date
Application number
NO20081745A
Other languages
English (en)
Other versions
NO338913B1 (no
Inventor
Eisaku Sasaki
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Publication of NO20081745L publication Critical patent/NO20081745L/no
Publication of NO338913B1 publication Critical patent/NO338913B1/no

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/067—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Error Detection And Correction (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

For å redusere kretsstørrelsen og effektforbruket og for å oppnå en raskere beregning av logaritmisk sannsynlighetsforhold uavhengig av modulasjonsarrangementers flernivåantall er det foreslått en områdepåvisende krets (101) som mottar en hård-desisjonsbit for bitene som representerer P-aksekoordinatene for et mottatt signalpunkt og som på grunnlag av den mottatte hård-desisjonsbit påviser og avgir et område i faseplanet hvor koordinatene for det mottatte signalpunkt eksisterer. En LLR-krets (1 02) mottar en mykdesisjonsbit for biter som representerer koordinatene for det mottatte signalpunkt og på grunnlag av den mottatte myk-desisjonsbit beregner den et primært LLR. På grunnlag av avgivelsen fra den områdepåvisende krets (resultatet av områdepåvisningen) beregner en LLR-omformer (103, 104) et endelig LLR. Ved å benytte arrangementet beskrevet ovenfor begrenses det verdiområde innenfor hvilket verdien av det logaritmiske sannsynlighetsforhold varierer i samsvar med posisjonen av det mottatte signalpunkt bare mellom nabosignalpunkter som innbefatter hård-desisjonsterskelverdien for bitene, for derved å beregne det logaritmiske sannsynlighetsforhold.
NO20081745A 2006-09-29 2008-04-09 Aritmetisk LLR-krets og -fremgangsmåte, og sendeanordning og program NO338913B1 (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006266523 2006-09-29
PCT/JP2007/068925 WO2008038749A1 (fr) 2006-09-29 2007-09-28 circuit de calcul du logarithme de rapport de vraisemblance, appareil émetteur, procédé et programme de calcul du logarithme de rapport de vraisemblance

Publications (2)

Publication Number Publication Date
NO20081745L true NO20081745L (no) 2009-03-17
NO338913B1 NO338913B1 (no) 2016-10-31

Family

ID=39230183

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20081745A NO338913B1 (no) 2006-09-29 2008-04-09 Aritmetisk LLR-krets og -fremgangsmåte, og sendeanordning og program

Country Status (7)

Country Link
US (1) US8675771B2 (no)
EP (1) EP1936904A4 (no)
JP (1) JP4572982B2 (no)
CN (1) CN101356790B (no)
NO (1) NO338913B1 (no)
RU (1) RU2434350C2 (no)
WO (1) WO2008038749A1 (no)

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US20110150143A1 (en) * 2009-12-18 2011-06-23 Electronics And Telecommunications Research Institute Soft-decision demapping method for digital signal
JP5581930B2 (ja) * 2010-09-17 2014-09-03 富士通株式会社 受信装置および受信方法
CN103973630B (zh) * 2013-01-24 2017-03-15 晨星软件研发(深圳)有限公司 适用于数字电视广播系统的信号处理方法以及接收器
JP6075446B2 (ja) * 2013-04-23 2017-02-08 日本電気株式会社 復調装置、復調方法およびプログラム
JP6038340B2 (ja) * 2013-10-18 2016-12-07 三菱電機株式会社 尤度生成回路および尤度生成方法
CN106063216B (zh) * 2014-02-24 2018-06-19 三菱电机株式会社 软判定值生成装置以及软判定值生成方法
WO2017221926A1 (ja) * 2016-06-21 2017-12-28 日本電信電話株式会社 光受信機、光伝送装置及び光受信機のための方法
JP6675645B2 (ja) * 2016-11-02 2020-04-01 日本電信電話株式会社 中継装置及び中継方法
EP3926836B1 (en) 2019-03-11 2023-01-18 Mitsubishi Electric Corporation Optical transmission device and likelihood generation circuit
CN113055319B (zh) * 2019-12-27 2022-02-25 华为技术有限公司 一种信号均衡方法和装置
JP7563026B2 (ja) 2020-07-31 2024-10-08 富士通株式会社 通信装置および通信システム
WO2025009156A1 (ja) * 2023-07-06 2025-01-09 日本電信電話株式会社 受信装置及び推定方法
JP7763315B1 (ja) * 2024-10-21 2025-10-31 Ｎｔｔイノベーティブデバイス株式会社 誤り訂正方法および誤り訂正回路

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Also Published As

Publication number Publication date
JPWO2008038749A1 (ja) 2010-01-28
RU2008117109A (ru) 2009-11-10
CN101356790B (zh) 2013-08-14
RU2434350C2 (ru) 2011-11-20
WO2008038749A1 (fr) 2008-04-03
EP1936904A1 (en) 2008-06-25
CN101356790A (zh) 2009-01-28
EP1936904A4 (en) 2015-10-21
US20100150268A1 (en) 2010-06-17
US8675771B2 (en) 2014-03-18
NO338913B1 (no) 2016-10-31
JP4572982B2 (ja) 2010-11-04

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