MXPA99002511A - Digital qam modulator using post-filtr carrier recombination - Google Patents

Abstract

The present invention relates to the quadrature-efficient amplitude modulator of the present invention allows 6 to 8 independent compressed channels to occupy a 6 MHz bandwidth, while the processing power is reduced by 33% for 8 levels of modulation offered by 64 QAM and in 25% for 16 modulation levels offered by 256 QAM. The modulator achieves this efficiency by using an improved digital filter architecture that combines modulation and filtering with the combination of the post-filtered carrier. The presented QAM modulator is instrumented with a reduction in the total number of binary parallel multipliers. To increase operational performance, the speed of operation increases with the use of look-up tables (LUTs) that store the weighted and precomputed coefficients of the filter. The reduction in multipliers is also achieved by using the carrier combination after filtering, which also reduces the number of MAC multiplication and accumulation operations performed during filtering. The invention can also be constructed as a programmable door array per field (FPGA) or as an application-specific integrated circuit (ASI).

Description

DIGITAL QAM MODULATOR USING POST-FILTERED CARRIER RECOMBINATION BACKGROUND OF THE INVENTION Field of the Invention The present invention relates in general to digital filtering techniques by quadrature amplitude modulation. More specifically, the invention relates to an efficient quadrature amplitude modulator with a digital filter implementation that significantly decreases the processing power required.

Description of the Prior Art In current digital communications technology, one of the most common methods for compressing more bits of data within an allocated bandwidth is done using multilevel systems or M-ary techniques.

(Multinary). Because digital transmission significantly wastes the RF bandwidth, regulatory authorities usually require a minimum of bit compression. One of the most common techniques that combines both modulated amplitude and modulation per phase is the quadrature amplitude modulation (QAM) technique M-ary (Multinary). QAM modulates two different signals in the same bandwidth. This is achieved by creating a composite modulated amplitude signal 2064-16 / 6P using two carriers of the same frequency. The two carriers are distinguished by having a phase difference of 90 degrees. By convention, the cosine carrier is called an in-phase component and the sine carrier is called a quadrature component. As a prior art, the entire digital architecture 15 for a QAM modulator 17 is shown in Figure 1. The modulator 17 accepts a digital input 19, where 21 is converted, from a stream of serial bits to a parallel configuration to enter a encoder 23. The encoder 23 divides the incoming signal into a constellation of symbols corresponding to the components in phase (I) (xr (t? T)) and in quadrature (Q) (jx ± (nT)), while also performing front error correction (FEC) (in English called forward error correction) for further decoding when the signal is demodulated. The outputs of the converter are coupled to a QAM modulator 17 comprising paired Nyquist filters 25, 27, raised to the square root of identical finite impulse response (FIR). The filters Nyquist 25, 27 are a pair of low-pass, identical interpolation filters that receive signals I (xr (nT)) and Q (jx ± (nT)) from the encoder 23 and generate real and imaginary parts of the base band signal limited by complex band. Nyquist 25, 27 filters improve intersymbol interference (ISI) which is a byproduct of amplitude modulation with width 2064-16 / 6P limited band. After filtering, the in-phase (yr (nT)) and quadrature (jyi (nT)) components are modulated with mixers 29, 31 with the center frequencies IF 33, 35 and then added to 37, producing an output signal QAM (g (nT)) of IF limited in band, for conversion in 39 to an analog signal 41 and are transmitted. A paired 40-tap Nyquist filter would require forty (40) binary multipliers that would consume a considerable area of silicon and adversely affect the maximum processing speed due to multiplication and accumulation (MAC) operations. A multiplier instrumented in digital form is inefficient and expensive due to the number of logic gates. Binary adders are less expensive than binary multipliers, however their use must also be minimized. Implementing a design that uses binary multiplication and addition in an ASIC (Application Specific Integrated Circuit) would be expensive to manufacture and would result in more inefficient performance and a slower signal. The same would happen if an FPGA (programmable door arrangement per field, in English called field programmable gate array) was programmed. Therefore, a disadvantage of FIR filters is the computational complexity required for each output sample. A QAM modulator 2064-16 / 6P constructed in accordance with prior art teachings may require separate integrated circuits instead of full integration into an economical ASIC or FPGA. Consequently, there is a need for a QAM modulator that increases computational performance by using a filter together with a postfiltering carrier combination to reduce numerical operations and at the same time increase speed.

SUMMARY OF THE INVENTION The efficient quadrature amplitude modulator of the present invention allows a plurality of independent compressed channels to occupy a 6 MHz bandwidth while reducing the processing power by 33 percent, for 8 modulation levels offered by 64-QAM, and 25 percent for 16 modulation levels offered by 256-QAM. The modulator achieves this efficiency by using an improved digital filter architecture that combines modulation and filtering with the combination of the post-filtered carrier. The presented QAM modulator is instrumented with a reduction in the total number of parallel binary multipliers. To increase operational performance, the speed of the operation increases with the use of look-up tables (LUTs) 2064-16 / 6P look-up tables) that store precomputed filter weighting coefficients. The reduction in multipliers is also achieved using a post-filtering carrier combination that similarly reduces the number of MAC operations performed during filtering. The invention can also be constructed either as an FPGA or as an ASIC. The use of query tables (LUTs) produces significant savings in chip resources and manufacturing costs. Accordingly, the object of the present invention is to provide an efficient QAM modulator for multichannel applications. Another object of the invention is to provide a multi-channel QAM architecture with improved performance and reduced complexity. Other objects and advantages of this system will become apparent to those with expertise in this field after reading the detailed description of the preferred embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block-system diagram of a typical quadrature amplitude modulator of the prior art. Figure 2 is a block diagram of the system of the present invention. Figure 3A is a block diagram of 2064-16 / 6P Nyquist filter architecture system for the in-phase component. Figure 3B is a system block diagram of the Nyquist filter architecture for the quadrature component. Figure 3C is a block diagram of the mixing function showing the sine and cosine waveforms. Figure 4 is a graph of the signal input constellation back to zero. Figure 5 is a graph of the constellation of signal output from non-return to zero, after the combination of the carrier. Figure 6 is a diagram showing a displacement operation of the sub-filter and the assignment of the look-up table. Figure 7 is a system block diagram of an alternative embodiment of the present invention, DESCRIPTION OF THE PREFERRED MODALITIES A quadrature amplitude modulator is described in relation to the drawings, in which like reference numbers represent like elements in all the drawings. These modulators are used in multi-channel communication network heads in cable television (CATV), together with the transmission of a 2064-16 / 6P plurality of programming for the consumer. A system block diagram of the present invention 43 is shown in Figure 2. A front error correction encoder (FEC) produces data streams in phase (I) 45 and quadrature phase (Q) 47 for the modulator Digital QAM 49, according to a predetermined QAM constellation. The QAM modulator 49 performs the baseband filtering Nyquist, digital interpolation and quadrature amplitude modulation. The output of the QAM modulator is a digital signal of intermediate frequency. A digital to analog converter (D / A) 53 transforms the digital IF signal into an analog signal 55 for transmission. To simplify the processing of the digital signal that is carried out in the FIR filter and to facilitate the programming of an FPGA, the recombination of the carrier after filtering is used to reduce the overall complexity of the digital filter and to eliminate other sources of clock. high frequency. Unlike the prior art FIR filters that are based on many MAC operations, serial multipliers are used in the mixers of the present invention to exploit the high processing speed of the FPGA chip, without the overhead associated with multiplexers that are they use when multiplying in parallel. The savings you have when using the 2064-16 / 6P shift recorder and half-masters to perform multiplication is well understood in this technique. By way of antecedent, for 256-QAM, the input data I and Q are each comprised of 4 bits. 4 bits of the data can represent multi-level signals (16) from return to zero (RZ) with a discrete level 0 and levels from 1 to 15. However, when transmitting radio frequencies, a symmetric waveform is desired for the best signal ratio to noise (SNR) with a specific transmitter power. With a 4-bit modulation level waveform 16, a symmetric signal of non-return to zero (NRZ) can not be constructed since there are only two possible level assignments. -7 to +8 or -8 to +7, from the four bits that make an exact total of sixteen. The level 0 placed on the abscissa does not require the transmission of the carrier. If either of the two previous groups of waveforms are used to generate the RF signal, two problems will arise. First, the output level of the RF signal will not have a uniform distribution even when the probability of the input data for each level has a uniform distribution, thus reducing the overall efficiency of the channel. Second, the zero level data will generate zero carrier output. For a prolonged period of zero-level signaling, a receiver may lose 2064-16 / 6P synchronization of the incoming signal. Frequency resynchronization would make the system inoperative. To obtain a multilevel and symmetric NRZ signal, a one bit shifted to the original sampling data must be added. The 4-bit information can then be expressed by discrete levels of 15 to -15. These levels can be represented by a logical association of 4 to 5 bits where only the values of -15, -13, ...- 1, 1, ... 13, 15 are used. For digital signal processing, an additional bit represents a 25% increase in the speed of the input data for 256-QAM. For 64-QAM, the additional bit represents a 33% increase in the input data rate. A cost consideration for a digital modulator is determined by the complexity of the digital filter needed to process an input data rate. A 33% increase in the net speed of the input data results in a significant increase in hardware cost for the digital filter and the clock source. The present invention efficiently implements a Nyquist filter using serial multipliers and query tables for the weighting coefficients, in order to effect the digital signal processing. Series multipliers require N times (Nx) the clock source for multipliers 2064-16 / 6P (mixers), where N is the number of bits of the input data. As an example, for 256-QAM, without recombination of the post-filtered carrier, a multiplier in series requires 5x the clock source. This requires an additional phase lock loop (PLL) with a controllable voltage oscillator (VCO), a phase comparator and a loop filter. In this invention, the use of post-filtering carrier recombination causes only the original 4 bits of the signal data to be processed during filtering. With 4 bits of the input data, the serial multipliers require 4x the clock, which is easily available from the input data or can be easily derived from the harmonics of the input data, without the PLL circuitry. To show the commutative property of the sum of the carrier displacement after filtering, an NRZ signal g (n) can be characterized as: g (n) = f (n) + c (n), Equation 1 where / (n) represents a multilevel RZ signal of data streams of input I and Q with discrete levels -7 to +8, and c (n) is a bit offset, a constant of -0.5 is achieved by the logical correlation from 4 bits to 5. The output of the Nyquist filter is: 2064-16 / 6P e (n) = g (n) * h (n), Equation 2 = f (n) * h (n) + c (n) * h (n); Equation 3 where * denotes the convolution operator, h (n) is the low-pass filter Nyquist and e (n) is the output of the filter. Using a ratio of 1: 8 interpolation (eight times) and a Nyquist filter of 320 shots as in the preferred embodiment, the 320-shot filter can be reduced to eight 40-shot filters using a carrier frequency equal to one quarter (T / 4). ) of the sampling frequency. Making the substitution, the above equation results in: 40 40 e (-i-j) =? g (i -n) * h (S-n-j) +? c (i - «) * A (8 •« - j), Equation 4 n = 0 n = 0 40 40 = S g (i -n) * h ($ - n- j) - 0.5? h • n - j); Equation 5 n = 0 «= 0 where g (n) represents the input data I and Q before the interpolation and j = l, 2.3 ... 8 represents each sub-filter. Equation 4 shows that the Nyquist filtering, interpolation and modulation for each I and Q bit stream can be divided into eight sub-filter banks I and Q, as shown in Figures 3A and 3B, respectively. 2064-16 / 6P Figure 3A shows the Nyquist filter in phase (I) for the modulator 43 incorporating the postfiltered carrier combination. As it was derived before, the Nyquist filter of 320 takes is reduced to 8 banks of discrete filters 61i, 63i, 65i, 67i, 69i, 71i, 73i, 75i, of 40 shots each. The output of each filter bank is mixed 79i, 81i, 83i, 85i, 87i, 89i, 91i, 93i with offset 95 of the cosine carrier and is multiplexed to 96 and output with the carrier shift phase. Figure 3B shows the same reduction in the Nyquist filter for the quadrature phase data (Q). Eight 40-outlet Nyquist filters 61q, 63q, 65q, 67q, 69q, 71q, 73q, 75q. The output of each filter bank is mixed 79q, 81q, 83q, 85q, 87q, 89q, 91q, 93q with the displacement 101 of the sine carrier and multiplexed 103 and output at 104 with the displacement phase of the carrier When the center frequency IF of the modulator QAM is equal to the symbol rate 1 / T, the cosine waveforms 95 and sine 101 shown in Figure 3C, required for the mixing function, can also be sampled in each quadrant of 360 degrees , or at 0, 90, 180 and 270 degrees. The corresponding value therefore equals 1 (95a), 0 (95b), -1 (95c), 0 (95d) for cosine 95 and 0 (101a), 1 (101b), 0 (101c), -1 (lOld), for the waveforms of sine 101. As can be seen, when any of the waveforms has a 2064-16 / 6P magnitude O, the other waveform has a value of 1 or -1. As half of the cosine samples 95 and sin 101 are 0, when sampled at 4 / T, the two FIR filters of 320 identical taps, which are shown in Figures 3A and 3B for the I and Q bitstreams, can be replaced by a 320-shot FIR filter, which simultaneously processes the two I and Q bit streams, as shown in Figure 2, sampling each I and Q bit stream at a rate of 2 / T and not at a speed of 4 / T, thus eliminating the zero magnitude value. With an interpolation ratio of 1: 8, the FIR filter of 320 taps processes the I and Q bit streams in parallel, synchronized at a clock speed equal to the symbol rate 1 / T. The detailed data flow for a sub-filter of 40 taps is shown in Figure 6. The input data streams I and Q (only one is shown) are transformed from 4-bit word chains parallel to 4-bit word chains serial, using an offset clock 109 and registers 111. The serial 4-bit data is segmented and stored in RAM-based shift registers for all values of 160 takes. As already described, the incoming bit stream for the phase and quadrature data is divided into groups 113 of 40-tap values corresponding to its 4 sub-filters, respectively. The data is further divided into groups of four 115, corresponding to 4x4 query tables (LUTs) and 2064-16 / 6P displace as a 4-bit magnitude. The function of the query tables is as follows. A mathematical function / of an argument x with a result of y is expressed as y = / (x). The function develops a logical correlation of all the values of x in another space of values y. A look-up table (LUT) develops this logical correlation for the values of interest in the preferred modality. The LUT memory device is presented with an address of a location within the memory circuit. The value previously stored in that location is supplied to the memory output data bus. The interest values of x, which are discrete, are correlated in a binary number. Since signals are represented by logical levels zero or one, they are used as bits to form a binary number. Any possible combination of values is assigned to a state number. This operation is represented as M- \ A =? X V = xu, 2M "'+ ... x32 + x222 + x121 + x02 ° Equation 7 J = o = xM_, 2w, + ... x38 + x24 + xI2 + x0 Equation 8 Each state is a binary number that refers to an address in the LUT. The output value of the LUT is the precomputing value of the resultant of the function that would occur given the argument corresponding to 2064-16 / 6P that address. This is illustrated as a tabular representation of the content of the LUT. The function to be developed is the weighted sum of the multiple channels for a single specific take of the FIR structure. For example, in an application that uses 4 bits (M = 4), the content of the LUT located in the second socket (j-2) would be as shown in Table 1.

Table 1 The words in the LUT 56 memory contain 2064-16 / 6P precomputed values corresponding to the value of the current input address, as shown in Figure 8B. The memory can be implemented in either ROM or RAM, depending on the application. In the preferred mode, a ROM is used (read only memory) to store the permanent LUT values. This is efficiently implemented as an integrated circuit. The ROM is suitable for systems that do not vary with time, where the required channel weights and filter coefficients are known a priori. RAM (random access memory) allows new values to be written over old values. The LUT values can be computed and loaded to achieve adaptivity. RAM is not as efficient in space as ROM, but it is still efficient considering its greater flexibility. For 256-QAM, 80 LUTs are required. The output of each of the LUTs is multiplied in series with the outputs of the other LUTs that belong to a sub-filter. The product is modulated with the carrier, producing an IF signal modulated with NRZ. The output of each sub-filter is input to a mixer and mixed with the respective displacement of the carrier. The output of each mixer is input to a multiplexer 107 of 8: 1 ratio. The output of the mixer is coupled to a synchronization function 109, X / sine (x) that compensates for the distortion 2064-16 / 6P in amplitude introduced during digital-to-analog conversion. The output of the synchronization function is input to a digital to analog converter 53 for conversion to analog signal and is filtered at 57 to avoid distortion of the frequencies due to sampling, ie, to avoid toothing (aliasing). The output 59 is transmitted. The first term of Equation 4 is the digital filtering and the modulation of the input data RZ. The second term is a constant for each filter bank. The displaced carrier will match the filter data carrier, as long as the displacement for each filter bank output is equal to the sum of 40 -0.5Y h - n - j) Equation 6 n = 0 j = 1, 2, 3. . , 8 for each corresponding sub-filter. It has been shown that by recombining the carrier component for each data bitstream I and Q after digital filtering, the RZ to NRZ transformation process of the input data before filtering has been eliminated. The filtering and modulation process is simplified because the digital processor that performs the filtering operation requires an operand for only 4 data bits, for the 256-QAM modulation, and 2064-16 / 6P 3 bits of data, for 64-QAM modulation. A constellation diagram for 256-QAM using a RZ signal input (without the 1-bit shift of the carrier) is plotted in Figure 4. The constellation of the corrected output carrier signal is plotted in Figure 5. The present invention combines the filtered output of the Nyquist filter with a shifted carrier. The final signal is an IF signal modulated by NRZ with a precise carrier displacement. An alternative embodiment of the present invention is shown in Figure 7. The difference between the preferred and alternative modalities is the place where the carrier combination is executed after filtering. In the alternative modality, the displacement of the carrier is mixed downstream of multiplexer 8: 1. This mode reduces the number of post-filtered mixers and the elimination of two oscillators that require a more complex array, where the carrier shift is changing between the cosine and sine function, depending on when the multiplexer selects a sub-filter in quadrature or a sub-filter in phase, corresponding. The alternative modality presents a more elegant approach that adds complexity in the change or commutation. While the present invention has been described in terms of the preferred embodiment, it will be apparent to those skilled in the art other 2064-16 / 6P variations that fall within the scope of the invention, as outlined in the appended claims 2064 -. 2064 -16 / 6P

Claims (24)

1. CLAIMS 1. A digital quadrature amplitude modulator (QAM) comprising: a first QAM input for receiving in-phase data bit streams from a front error correction encoder (FEC); a second QAM input for receiving bit streams of quadrature phase data from the FEC encoder; a QAM output; a plurality of first sub-filters, each of which has an input coupled to the first QAM input and an output coupled to a single input of a multiplexer; a plurality of second sub-filters equal in number to the plurality of first sub-filters; each second sub-filter has an input coupled to the second QAM input and an output coupled to an individual input of the multiplexer; a first modulator means that provides the displacement of the post-filtered carrier and that is coupled to the outputs of the first sub-filter; a second modulator means that provides the displacement of the post-filtered carrier and that is coupled to the outputs of the second sub-filter; the inputs of the multiplexer are arranged in series so that the coupling of the inputs Successive 2064-16 / 6P of the multiplexer are alternated between a coupling with an output of the first sub-filter and a coupling with an output of the second sub-filter; and the multiplexer has an output coupled to the QAM output.
2. 2. A digital quadrature amplitude modulator (QAM) according to claim 1, wherein the first modulator means further comprises: a plurality of mixers corresponding to each of the first sub-filters, each mixer having a first and a second input and an exit; and a plurality of cosine generators corresponding to the number of the first sub-filters, each of the generators having an output coupled to the respective mixers of the first sub-filters; the second modulator means further comprises: a plurality of mixers corresponding to each of the second sub-filters, each mixer having a first and a second inputs and an output; and a plurality of sinus generators corresponding to the number of the second sub-filters, each having an output coupled to the respective mixers of the second sub-filters.
3. 3. A digital quadrature amplitude modulator (QAM) according to claim 1, wherein the sub-filter is a look-up table (LUT).
4. 4. A digital modulator by amplitude in 2064-16 / 6P quadrature (QAM) according to claim 1, wherein the data bits in phase and in quadrature phase represent a constellation of 64 QAM.
5. 5. A digital quadrature amplitude modulator (QAM) according to claim 1, wherein the data bits in phase and in quadrature phase represent a constellation of 256 QAM.
6. 6. A digital quadrature amplitude modulator (QAM) comprising: a first QAM input for receiving in-phase data bit streams from a forward error correction encoder (FEC); a second QAM input for receiving phase quadrature data bit streams from the front error correction encoder (FEC); a QAM output; a plurality of first sub-filters, each having an input coupled to the first QAM input and an output coupled to a single input of a multiplexer; a plurality of second sub-filters equal in number to the plurality of first sub-filters; each second sub-filter has an input coupled to the second QAM input and an output coupled to an individual input of the multiplexer; the inputs of the multiplexer are arranged in series so that the coupling of inputs Successive 2064-16 / 6P of the multiplexer are alternated between a coupling with an output of the first sub-filter and a coupling with an output of the second sub-filter and the multiplexer has an output; and a modulator means that provides the displacement of the post-filtered carrier for all data bit streams.
7. 7. A digital quadrature amplitude modulator (QAM) according to claim 6, wherein the modulator means is coupled to the output of the multiplexer and further comprises: a mixer having a first and second inputs and an output; and a signal generator having an output coupled to the mixer, wherein the signal generator switches between a cosine function and a sine function, depending on whether the multiplexer selects a corresponding sub-phase or quadrature phase filter.
8. 8. A digital quadrature amplitude modulator (QAM) according to claim 6, wherein each sub-filter is a look-up table (LUT).
9. 9. A digital quadrature amplitude modulator (QAM) according to claim 6, wherein the data bitstream in phase and quadrature phase represents a constellation of 64 QAM.
10. 10. A quadrature amplitude digital modulator (QAM) according to claim 6, wherein the 2064-16 / 6P data bit streams in phase and quadrature phase represent a 256-QAM constellation.
11. 11. A quadrature amplitude digital modulator (QAM) according to claim 6, wherein the modulator means further comprises: a first modulator means that provides the displacement of the post-filtering carrier coupled to the outputs of the first sub-filter; and a second modulator means that provides the displacement of the post-filtering carrier coupled to the outputs of the second sub-filter.
12. 12. A digital quadrature amplitude modulator (QAM) according to claim 11, wherein the first modulator means further comprises: a plurality of mixers corresponding to each of the first sub-filters, each mixer having a first and a second input and an exit; and a plurality of cosine generators corresponding to the number of the first sub-filters, each having an output coupled to the respective mixers of the first sub-filters; the second modulator means further comprises: a plurality of mixers corresponding to each of the second sub-filters, each mixer having a first and a second inputs and an output; and a plurality of sinus generators corresponding to the number of the second sub-filters, 2064-16 / 6P each having an output coupled to the respective mixers of the second sub-filters.
13. 13. A digital quadrature amplitude modulator (QAM) for cable television (CATV), located in a network head of a cable television system (CATV), comprising: a first QAM input to receive bit streams from in-phase data from a front error correction encoder (FEC); a second QAM input for receiving bit streams of quadrature phase data from the FEC encoder; a QAM output; a plurality of first sub-filters, each having an input coupled to the first QAM input and an output coupled to a single input of a multiplexer; a plurality of second sub-filters equal in number to the plurality of first sub-filters; each second sub-filter having an input coupled to the second QAM input and an output coupled to an individual input of the multiplexer; a first modulator means that provides the displacement of the post-filtered carrier, coupled to the outputs of the first sub-filter; a second modulator means that provides the displacement of the post-filtered carrier, coupled to 2064-16 / 6P the outputs of the second sub-filter; the multiplexer inputs being arranged in series so that the coupling of the successive inputs of the multiplexer is alternated between a coupling with an output of the first sub-filter and a coupling with an output of the second sub-filter; and the multiplexer having an output coupled to the QAM output.
14. 14. A digital quadrature amplitude modulator (QAM) according to claim 13, wherein the first modulator means further comprises: a plurality of mixers corresponding, each, to the first sub-filters, each mixer having a first and a second input and an exit; and a plurality of cosine generators corresponding in number to the first sub-filters, each having an output coupled to the respective mixers of the first sub-filters; the second modulator means further comprises: a plurality of mixers corresponding to each of the second sub-filters, each mixer having a first and a second inlet and an outlet; and a plurality of sine generators corresponding to the number of the second sub-filters, each having an output coupled to the respective mixers of the second sub-filters. 2064-16 / 6P
15. 15. A digital quadrature amplitude (QAM) modulator for cable television (CATV) according to claim 13 wherein each sub-filter is a look-up table (LUT).
16. 16. A digital quadrature amplitude (QAM) modulator for cable television (CATV) according to claim 13, where the data bits in phase and quadrature phase represent a constellation of 64 QAM.
17. 17. A digital quadrature amplitude (QAM) modulator for cable television (CATV) according to claim 13, wherein the data bits in phase and in quadrature phase represent a constellation of 256 QAM.
18. 18. A digital quadrature amplitude (QAM) modulator for cable television (CATV), comprising: a first QAM input to receive in-phase data bit streams from a front error correction encoder (FEC); a second QAM input for receiving quadrature phase data bit streams from the front error correction encoder (FEC); a QAM output; a plurality of first sub-filters, each having an input coupled to the first QAM input and an output coupled to an individual input of a 2064-16 / 6P 2 multiplexor; a plurality of second sub-filters equal in number to the plurality of first sub-filters; each second sub-filter having an input coupled to the second QAM input and an output coupled to an individual input of the multiplexer; the multiplexer inputs being arranged in series so that the coupling of the successive inputs of the multiplexer is alternated between a coupling with an output of the first sub-filter and a coupling with an output of the second sub-filter; and the multiplexer having an output; and a modulator means providing displacement of the post-filtered carrier for all data bit streams.
19. A digital modulator for quadrature amplitude (QAM) for cable television (CATV) according to claim 18, wherein the modulator means is coupled to the output of the multiplexer and further comprises: a mixer having a first and a second input and an exit; and a signal generator having an output coupled to the mixer, wherein the signal generator switches or switches between a cosine function and a sine function depending on whether the multiplexer selects a corresponding sub-phase or quadrature filter.
20. 20. A digital modulator by amplitude in 2064-16 / 6P quadrature (QAM) for cable television (CATV) according to claim 18, wherein each sub-filter is a look-up table (LUT).
21. 21. A digital quadrature amplitude (QAM) modulator for cable television (CATV) according to claim 18, wherein the data bits in phase and in quadrature phase represent a constellation of 64 QAM.
22. 22. A digital quadrature amplitude (QAM) modulator for cable television (CATV) according to claim 18, wherein the data bits in phase and in quadrature phase represent a constellation of 256 QAM.
23. 23. A digital quadrature amplitude (QAM) modulator for cable television (CATV) according to claim 18, wherein the modulator means further comprises; a first modulator means that provides displacement of the post-filtered carrier, coupled to the outputs of the first sub-filter; and a second modulating means that provides the displacement of the post-filtered carrier, coupled to the outputs of the second sub-filter.
24. 24. A digital quadrature amplitude (QAM) modulator for cable television (CATV) according to claim 23, wherein the first modulator means further comprises: 2064-16 / 6P a plurality of mixers corresponding to each of the first sub-filters, each mixer having a first and a second input and an output; and a plurality of cosine generators corresponding to the number of the first sub-filters, each having an output coupled to the respective mixers of the first sub-filters; the second modulator means comprises: a plurality of mixers corresponding to each of the second sub-filters, each mixer having a first and a second inlet and an outlet; and a plurality of sine generators corresponding to the number of the second sub-filters, each having an input coupled to the respective mixers of the second sub-filters. 2064-16 / 6P