MXPA99001789A - Modular multiplexing system - Google Patents

Abstract

A display and control module (100) sends synchronization signals and camera display codes to a loop multiplexer module (200) and a home run multiplexer module (300). The loop multiplexer module has a plurality of cameras coupled to a loop multiplexer unit (210). The loop multiplexer unit controls the synchronization and selection of video from the cameras for sending to the display and control module. The home run multiplexer includesa home run multiplexer unit (310) coupled to a plurality of coaxial cables, each coaxial cable having at least one video camera (321-322, 331, 341-343). The home run multiplexer unit receives the synchronization and control signals from the display and control module and uses those signals for synchronizing and selecting video images from one of the plurality of cameras for sending to the display and control module. The display and control module uses the video signals from the loop multiplexer module and the home run multiplexer module to display on a display.

Description

MODULAR MULTIPLEXAGE SYSTEM BACKGROUND OF THE INVENTION The present invention relates to the multiplexing of video signals, and more specifically, to the control of multiplexing of video signals. The use of multiple cameras in a surveillance system has required the use of multiplexing of those cameras in a single video stream for recording or presentation. As the number of multiplexed cameras in a system grows, the difficulty of multiplexing the video images of those cameras in a single video stream becomes more complicated. After a multiplexed system has a certain number of cameras, the cameras must be divided into multiple multiplexed systems. However, these multiple multiplexed systems operate independently. Therefore, there is a need for methods and devices that control a plurality of multiplexed systems.

SUMMARY OF THE INVENTION According to the present invention, a modular multiplexing system comprises a display and control module having a display and control unit connected to at least one screen. In one embodiment, the presentation and control unit receives video signals from a video playback unit and processes those images for presentation. In another embodiment, the display and control unit sends slave control signals and synchronization signals to at least one slave module, and receives video signals again from the at least one slave module. The slave module includes a plurality of cameras coupled to a control unit that selects the video signals from one of the plurality of video cameras for transmission to the display and control unit based on the slave control signal sent to the slave control unit from the presentation and control unit. In one embodiment, the slave module consists of a loop multiplexing module having a loop multiplexing unit that receives the slave control signals and the synchronization signals from the display and control unit. The loop multiplexer uses the slave control signals and synchronization signals to generate synchronization and control codes for the cameras. The loop multiplexing unit sends the synchronization and control codes on a first end of a coaxial loop or circuit. The plurality of cameras are connected to the coaxial loop and receive the synchronization and control codes from the loop multiplexing unit. One of the plurality of cameras corresponding to the camera code inserted by the loop multiplexer unit will insert a video image signal onto the coaxial loop. The loop multiplexer unit receives the composite video on a second end of the coaxial loop and sends the composite video to the presentation and control unit for presentation in the presentation and control module.

In another embodiment, the slave module consists of a home-grown multiplexer loop having a home-line multiplexer unit coupled to a plurality of coaxial cables, each coaxial cable having at least one video camera therein. The home-based multiplexer unit receives the control signals and slave synchronization signals from the presentation and control unit. The home-based multiplexer unit uses the control signals and slave synchronization signals to generate synchronization and control codes for the cameras. The home-line multiplexer unit sends the synchronization and control code signals in parallel on each of the coaxial loops. One of the plurality of cameras corresponding to the camera code inserted by the home-laying multiplexer unit on the coaxial cables, inserts a video image on the associated coaxial cable when receiving the corresponding camera code from the home-laying multiplexer unit . The home-line multiplexer unit receives the composite signal from the video image from the coaxial cable and transmits the composite video signal to the presentation and control unit in the presentation and control module.

BRIEF DESCRIPTION OF THE DRAWINGS These and other features, aspects and advantages of the present invention will be better understood with respect to the following detailed description, the appended claims and drawings, wherein: Figure 1 is a block diagram of a system of modular multiplexing; Figure 2 is a block diagram of the display and control unit from the display and control module of Figure 1; Figure 3 is a block diagram of the loop multiplexer unit from the multiplexer module in loops in Figure 1; and Figure 4 is a block diagram of the home laying multiplexer unit in the home laying multiplexer module of Figure 1.

DETAILED DESCRIPTION Now with reference to the figures, an embodiment of the present invention illustrated in a modular multiplexing system 10 for recording and displaying a large number of cameras from a single location is shown. The modular multiplexing system 10 consists of three basic modules: a presentation and control module (DC) 100, a multiplexer module in loop (LM) 200 and a multiplexer module for domestic laying (HRM) 300. The ML200 module allows multiple cameras to be connected in a single coaxial cable loop to record over a single video recorder, or to enter into the DC10C module for presentation via the DC100 module. The HRM300 module is similar to the LM module in that it synchronizes and multiplexes video from multiple cameras in a single video stream, but differs in that the cameras on the HRM300 module are connected by multiple non-looping cable runs. The LM200 module and the HRM300 module are slave modules that the DC100 module controls and presents. The DC100 module includes a presentation and control unit (DCU) 11O, a primary display 120, a secondary display 130, a video playback unit (VPU-SVBS) 140, a computer 150 and a video playback unit (VPU_Svid) 160 The DCU110 synchronizes all the slave modules in the modular multiplexing system 10 and also provides a location from which all the slave modules can be configured and controlled. The DCU110 processes the multiple video streams from a combination of up to 8 slave modules, the VPU-CVBS 140 and the VPU-SVid 160, and generates video streams for presentation on the primary display 120 and / or the secondary display 130. computer 150 can be used to configure the system 10. The DCU 110 can be divided into three main divisions: a power supply 111, a synchronizer and control 112 and a video buffer 113. The power supply 111 converts a power input of AC, such as 24 VAC, in a +5 VDC supply and a -5 VDC supply as required by the other circuitry in the DCU 110. The power supply 111 is a standard power supply having a 411 rectifier, a filter 413, a regulator 415 and a converter / regulator DC / DC 417 and has the addition of a cross signal detector of null signal on line 419. The detector of null signal on line latch 419 rec The input alternating input current of the DCU 110 is removed. The null latch signal crossing signal detector 419 generates an on-line latch synchronization signal (LSS) which tracks the sequence and phase of the input energy. The llss of the null line null signal crossing detector 419 is used by the DCU 110 for synchronization. The synchronization and contrcl 112 of the DCU 110 contains the logic for generating synchronization signals that are used in the video buffer 113 and the slave units, and the microcontroller 430 that drives the entire modular multiplexing system 1. Synchronization and control 112 includes a clock generator 420, a phase locked loop (PLL) filter 421, a voltage controlled oscillator (VCO) 422, ur. reference oscillator 423, a memory first inputs-first outputs (FIFO) 424, a time marker NV RAM 429, a microcontroller 430, a board 431, the status LEDs 432 and a buzzer 433. The generator of the clock signals 420 of the synchronizer and control 112 generates time-based ur. it is used to generate a reference frame clock signal. The generator of the clock signals also has a phase comparator which compares the reference frame clock with the signal llss of the detector of the null signal 419 in the power source 111 to determine if the phase of the signal llss is forward c back of the reference frame clock. The clock generator 420 sends a signal to the PLL filter 421 indicating the difference in phase between the llss and the clock-reference frame of the clock generator 420. The PLL filter 421 uses the phase difference information from the clock generator 420 to send a DC voltage signal to the VCO 422. The VCO 422 adjusts its clock output with the clock generator 420 based on the DC voltage signal from the PLL filter 421. The clock generator 420 also uses the reference oscillator 423 to create an acceptance frequency window in which the frequency of the LSS must be within. If the frequency of the llss is not within the acceptance frequency window generated by the clock generator 420 based on the reference oscillator 423, the clock generator 420 places the information signal of the difference of phases on one end of the acceptance frequency window. The clock generator 420 also generates the MCLK signal and the MSYNC signal of the master clock based on the time base within the clock generator 420. The clock generator 420 exchanges control codes with the micro controller 430 about the control lines. The passage of data between the clock generator 420 and the micro controller 430 passes through the FIFO filter 424 which acts as a data buffer. The NV RAM 429 time marker provides storage for the configuration data during periods without power, including time and data. The microcontroller 430 controls the functions of the components in the DCU 110, the slave control codes for controlling the slave modules and the interface with the computer control for the user configuration. The keyboard 431, the status LEDs 432 and the buzzer 433 provide the DCU interface that allows the operator to use the controls of the DCU 110. The video buffer 113 selects one of the video streams from the slave modules, the VPU-CVBS 140 and / or the VPU-SVid 160, and processes the selected video stream for presentation on the primary screen 120 and / or the secondary display 130. The video buffer 113 includes an anti-alias filter 440, a DC 450 multiplexer. , 470, a decoder / scaler 451, 471, an anti-alias filter 453, 473, a sync spacer 454, 474, a lock or lock circuit 455, 475, a code remover 456, 476, a memory controller 460, 480, a latch circuit 461, 481, a VRAM 462, 482, an interpolator 463, 483, an encoder 464, 484, and an on-screen display (OSD) 469, 489. The signals of the VPU-CVBS 140 in the DC 100 module is received by the video buffer 113. The luminance signals of the VPU- SVid 140 are received by the video buffer 113. The chrominance signal of the VPU-SVid 160 passes through the anti-alias or bandpass filter 440 and the decoder / scaler 451, 471. The video signals from the slave modules are received in the DC multiplexer 450, 470. The multiplexer DC 450, 470 is an 8 x 1 multiplexer that selects the video signals of one of the slave modules for an output based on a signal coming from the microcontroller 430 in the synchronizer and control 112. The signals coming from the VPU 140, the VPU 160 and the DC multiplexer 450 are received by a scaler multiplexer of the decoder 452 in the scaler of the decoder 451. The multiplexer of the decoder scaler 452 is a multiplexer 3 x 1 that selects video images from the VPU-CVBS 140, the VPU-SVid 160 or of the DC multiplexer 450, based on the control signal supplied to the decoder scaler 451 from the microcontroller 430 in the control synchronizer 112. The output signal of the scaler multiplexer of the decoder 452 passes through the anti-filter -alias 452 which is a pass band filter that limits the bandwidth before scanning. The video signal coming from the anti-alias filter 453 returns to the scaler input of the decoder 451. The signals coming from the VPU 140, the VPU 160 and the DC multiplexer 470 are received by a decoder scaler multiplexer 472 in the scaler of the decoder 471. The decoder scaler multiplexer 472 is a 3 x 1 multiplexer that selects video images from the VPU-CVBS 140, the VPU-SVid 160 or the DC 470 multiplexer, based on the control signal supplied to the scaler decoder 471 from the microcontroller 430 in the synchronizer and control 112. The output of the decoder multiplexer 472 passes through the anti-alias filter 473 which is a bandpass filter which limits the bandwidth before digitization. The video signal from the anti-alias filter 473 is returned to the decoder scaler input 471. The video signals from the anti-aliasing filters 453 and 473 are also supplied, respectively, to the synchronization separators 454 and 474, and the fixing circuits 455 and 475. The synchronization separators 454 and 474 separate the synchronization components of the composite video and send these signals to the clock generator 420 of the synchronizer and control 112 for synchronization during playback in the VPU. The locking circuits 455 and 475 change the DC component of the video for use by the code eliminators 456 and 476. The code eliminators 456 and 476 eliminate the data codes in the video of the clamping circuits 455 and 475, and send these codes data to the clock generator 420 in the synchronizer and control 112 for transmission to, and use by, the micro controller 430. The decoder scaler 451, 471 digitizes the video received from the anti-alias filters 453, 473 and separates the video signals into luminance signals and chrominance signals for storage. The scaler of the decoder 451, 471 also scales the number of vertical and horizontal images by a predetermined number based on the storage capacity of the VRAM 462. The digitized and scaled video from the scaler of the decoder 451, 471 is held by the latch 461, 481 while the VRAM 462, 482 stores the video data. In a preferred embodiment, VRAM 462, 482 has sufficient memory to store at least one video frame. The interpolator 463, 483 is a video scaler that changes the horizontal pixels of a video to a predetermined number. The encoder 464, 484 converts the digital video signal into an analog signal for the output to the primary display 120 and the secondary display 130. The memory controller 460, 480 provides video processing control as it passes from the latch circuit 461, 481 through the encoder 464, 484. The OSD 469, 489 generates characters that represent the information as time and date, which the micro controller 430 directs the insertion in the video that is being processed by the video buffer 113. In one embodiment, the DC multiplexer 450, 470, the decoder / scaler 451, 471, the anti-alias filter 453, 473, the synchronization separator 454, 474, the fixing circuit 455, 475, the code eliminator 456, 476 , the memory controller 460, 480, the latch circuit 461, 481, the VRAM 462, 482, the interpolator 463, 483, the encoder 464, 484 and the display (OSD) 469, 489 are mounted to the replaceable cards 191, 192, respectively, for modular insertion in the DCU 110. In another embodiment, the video buffer 113 will accept a plurality of these cards allowing additional monitors or video recording units connected to the video buffer 113. The LM 200 module includes a loop multiplexer unit (LMU) 210, a camera loop line 220 connected at both ends of the LMU 210, a plurality of cameras 221, 225 connected to the camera loop line 220, and a video recorder unit (LM-VRU) 250 connected to the LMU 210. The LMU 210 synchronizes the cameras 221-225 on the camera loop line 220. The LMU 210 also controls the insertion of video signals on the camera loop line 220 by means of the cameras 221- 225, and multiplexes these images for the output to the LM-VRU 250 and / or the DC 100 module. In one embodiment, the LMU 21. synchronizes the cameras 221-225 and controls the insertion of the video signals on the camera loop line 220 of in accordance with the teaching of the United States Patent Application Serial No. 08 / 501,261, entitled "Video Multiplexer", filed on July 11, 1995, assigned to the same assignee of the present invention, which is incorporated in your integrity in the present as a reference. When the LM 200 module is connected to the DC 100 module, the LMU 210 receives the slave control and the master clock signals from the DCU 110 of the DC 100 module. The LMU 210 uses the master clock signals from the DCU 110 to synchronize the cameras 221-225. The LMU 210 uses the slave control signals from the DCU 110 to control the video images coming from the cameras 221-225 for the output to the DC 100 module or the LM-VRU 250. When the LM 200 module does not connect to the DC 100 module, the LM 200 module will operate alone and will record the multiplexed video of the cameras 221-225 in the LM-VRU 250. The LMU 210 can be divided into three important divisions: a power source 211, a synchronizer and control 212 , and a video processor 213. The power source 211 converts an AC power input, such as 24 VAC, into a + 5VDC source and a -5VDC source as required by the other circuits of the LMU 210 In the same way as the power source 111 of the DCU 110, the power source 211 of the LMU 210 includes a rectifier 511, a filter 513, a regulator 515, a DC / DC converter / regulator 517 and ur. null line null signal crossing detector 519. The null line null signal crossing detector generates an in-line latch signal from loop modulus (LL-llss) that tracks the frequency and phase of the input energy . The synchronization and control 212 of the LMU 210 contains the logic for the generation of the video synchronization signals and the controller micrc that drives the entire LM 200 module. The synchronizer and control 210 contains a clock signal generator 520, a filter Phase Loop Loop (PLL) 521, a voltage controlled oscillator (VCO) 522, a reference oscillator 523, a memory first initial inputs (FIFO) 524-526, a time marker NVRAM 529, a microcontroller 530, a keypad 531, a status LED 532, a liquid crystal display (LCD) 534 and alarms 535. When the LM 200 module is connected to the DC 100 module, the clock signal generator 520 of the synchronizer and control 212 it uses the CLK and MSYNC signals of the master clock from the DCU 110 to generate the time base and clock of the reference frame for the components of the LMU 210. When the LM 200 module is operated in a stand-alone mode, the signal generator clock 520 uses the PLL filter 521, the VCO 522, the reference oscillator 523 and the LL-llss signals to generate synchronization signals used by the LM 200 module in the same way as the clock generator 420 in the synchronizer and control 112 of the DCU 110 uses the PLL 421 filter, UVCO 422, the reference oscillator 423 and the signal llss to generate the synchronization signals used by the DC 100 module. The clock signal generator 520 of the synchronizer and control 212 exchanges control codes with the micro controller 530 on the lines of control. The data is exchanged between the clock generator 520 and the microcontroller 530 through the FIFO 524-526, which acts as a data buffer. The NVRAM time tag 529 provides the storage for the data configuration during periods of time that the power is not supplied to the LMU 210. The microcontroller 530 generates the control signals that control the operation of the LMU 210, receives the control signals from the output of the slave control of the DCU 110 and provides an interface for the control of the computer allowing the configuration of the LM 200 module. The microcontroller 530 also acts as the interface with a user by means of the keypad 531, the LEDs of state 532 and LCD 234.

A plurality of alarms can be received at the entrance of the alarm interface 535. The microcontroller 530 monitors the status of the alarm and uses the information for decisions on the control of the LM 200 module. The 530 microcontroller can also send an alarm signal activated through the output of the alarm interface 535. The video processor 213 of the LMU 210 is responsible for the interface for the camera loop line 220 and for the processing of the video from the video loop line. camera 220 for sending to the LMU-VRU 250 and / or the DC 100 module. The LMU 210 is the interface to the camera loop line 220 by inserting synchronization signals onto the camera loop line 220 that are used by the cameras 221-225 for the synchronization, inserted data codes on the camera loop line 220 which are used to instruct each of the cameras 221-225 to insert video signals onto the c-loop line mara 220, and receiving the video signals from the camera loop line 220 that are processed to exit the video processor 213. The video processor 213 includes sync inserters 541 ab, code inserters 545 ab, a processor multiplexer of video 550, an AGC 551 sync, a video level detector 552, a frequency compensator 535, a code eliminator 554, a code inserter 555, a buffer 556 and a buffer 566. The interface with the loop line of camera 220 through LMU 210 is achieved by synchronization inserters 541 ab, code inserters 542 ab and multiplexer of video processor 550 of video processor 213. Synchronization insertors 541 ab generate synchronization signals that are inserted in the camera loop line 220 for use by cameras 221-225 for synchronization. In one embodiment, the synchronization signals inserted into the camera loop line 220 by the synchronization inserters 541 a-b are also used as the composite video sync pulse of the composite video. The code inserters 542 a-b generate the data communication codes that are inserted into the camera loop line 220 for use by the cameras 221-225. The data communication codes inserted by the code inserter 542 a-b are used by the cameras 221-225 for the activation of one of the specific cameras corresponding to the specific data code. The multiplexer of the video processor 550 is a 2 x 1 multiplexer that receives the video back from either side of the camera loop line 220. The multiplexer of the video processor 550 selects the side of the camera loop line 220 which is an output of the video processor multiplexer 550 based on the code received from the clock generator 520 in the synchronizer and control 212. In one embodiment, the decision of which side of the camera loop line 220 is a output of the multiplexer of the video processor 550 in the same way and based on the same criteria as the routing system of the video signal for the video signals described in the co-pending application filed concurrently with it as proxy file No. 27761-00055, entitled "Video signal routing system", assigned to the assignee of the present invention, which is hereby incorporated in its entirety as a reference. The video processing for the output by means of the LMU 210 to the LM-VRU 250 and / or the DC 100 module is achieved by the sync AGC 551, the video level detector 552, the frequency compensator 553, the eliminator code 554, code inserter 555, buffer 556 and buffer 566 of video processor 213. The AGC 551 sync scales up or down the video level so that the level of the synchronization signal is at a nominal value. Scaling of the video level by means of the AGC 550 sync is necessary to compensate for the losses resulting from the transmission of the synchronization signal around a large cable loop. The video level detector 552 determines the video losses for each individual camera 221-225 by comparing a reference signal generated by each camera at a known level. The comparison information of the video level detection 552 is transmitted again to each of the individual cameras 221-225, where the individual cameras 221-225 use it to adjust the gain of individual cameras. The 553 frequency compensator makes adjustments for frequency losses. In addition to the data communication codes inserted at the source end of the camera loop line 220 by means of the code inserters 545 ab, the return video will contain data communication codes inserted by the cameras 221-225 . In one embodiment, cameras 221-225 will insert data codes into the video signal in accordance with the teaching of US Patent Application Serial No. 08 / 501,261, entitled "Video Multiplexer", filed July 11, 1995, assigned to the same assignee of the present invention, which is incorporated herein by reference in its entirety. The code eliminator 554 eliminates the codes generated by the 221-225 cameras turned off from the return video and makes these codes available for the other parts of the video processor 203. The additional data communication codes, such as time, date and camera title, they are inserted into the video by the code inserter 555 before the video is sent to the LM-VRU 250 and / or the DC 100 module. The video signal from the video processor 213 passes through the buffer 556 before being sent to the LM-VRU 250, and through the buffer 566 before being sent to the DC 100 module. The HRM 300 module is similar to the LM 200 module in that it synchronizes and multiplexes the video currents from Multiple cameras in a video stream ready for recording or presentation, but differs in that their cameras are connected by multiple non-loop forming cable runs. Each of these cable runs can support multiple cameras. Although this configuration is more expensive in its installation, it provides superior performance in the presentation speed and can support the use of a call monitor. The HRM 300 module includes a homebreaking multiplexer unit (HRMU) 310, a video recording unit (HRM-VRU) 350 connected to the HRMU 310 and a 360 call monitor connected to the HRMU 310. The HRMU 310 synchronizes and controls the cameras 321-322, 331 and 341-343, on the cable runs 320, 330 and 340, respectively. The HRMU 310 also controls the insertion of the video signals on the lines of camera lines 320, 330 and 340, by the cameras 321-322, 331 and 341-343, and multiplexes the images to be sent to the HRM-VRU 350 and / or the DC 100 module. In one embodiment, the HRMU 310 synchronizes the cameras 321-322, 331, 341-343, according to the teaching of the US patent application serial No. 08 / 501,261, entitled "Video multiplexer. ", filed on July 11, 1995, assigned to the same assignee of the present invention, which is hereby incorporated in its entirety as a reference. When the HRM 300 module is connected to a DC 100 module, the HRMU 310 receives the signals from the slave control and the master clock from the DCU 110 of the DC 100 module. The HRMU 310 uses the master clock signals from the DCU 100 to synchronize the cameras 321-322, 331 and 341-343. The HRMU 310 uses the slave control signals from the DCU 110 to control the video images from the cameras 321-322, 331 and 341-343 to send them to the HRM-VRU 350 and / or the DC 100 module. When the HRM 300 module does not connect to the DC 100 module, the HRM 300 module will operate independently and will record the multiplexed video from the 321-322, 331 and 341-343 cameras on the HRM-VRU 350. The HRMU 310 can be divided into three major divisions: a power source 311, a synchronizer and control 312, and a video processor 313. The power source 311 converts the AC power supply, such as 24 VAC, into a + 5VDC supply and one -5VDC as required by the other circuitry in the HRMU 310. The power source 311 is similar to the power source 111 of the DCU 110 and the power source 211 of the LMU 210. The power source 311 includes a rectifier 611, a filter 613, a regulator 615, a converter / regulator DC / DC 617 and a detector of null signal of latching on line 619. The detector of null signal crossing of latching on line 619 of the power source 311 generates an signal • HRM online hitch synchronism (HRM-llss) that tracks the frequency and phase of the input power. The synchronizer and control 312 ae of the HRMU 310 contains the logic for the generation of the video synchronization signals and the micro controller that handles the entire HRM 300 module. The synchronizer and control 312 includes a clock generator 620, a filter phase locked loop (PLL) 621, a voltage controlled oscillator (VCO) 622, a reference oscillator 623, memories first inputs first outputs (FIFO) 624-627, a time marker MVRAM 629, a microcontroller 630 , a keypad 631, status LED 632, a liquid crystal display (LCD) 634 and alarm 635. When the HRM 300 module is connected to the DC 100 module, the clock signal generator 620 of the synchronizer and control 312 uses the MSLK and MSYNC signals from the master clock coming from the DCU 110 to generate the time base and reference frame clock for the components of the HRMU 310. When the HRM 300 module is operated in an independent mode, the signal generator The 620 clock uses the PLL 621 filter, the VCO 622, the reference oscillator 623 and the HRM-llss signal to generate the synchronization signals used by the HRM 300 module, in the same way as the clock generator 420 in the synchronizer and control 112 of the DCU 110 uses the PLL filter 421, the VCO 422, the reference oscillator 423 and the signal llss to generate the synchronization signals used by the DC 100 module. The clock signal generator 620 of the synchronizer and control 312 exchanges the control codes with the micro controller 530 over the control lines. The data is exchanged between the clock generator 620 and the microcontroller 630 through the FIFO 624-627, which act as data buffers. The NVRAM time tag 629 provides storage for data configuration during periods of time that power is not supplied to the HRMU 310. The microcontroller 630 generates the control signals that control the operation of the HRMU 310, receives the control signals from of the output of the slave control of the DCU 110 and provides an interface for the control of the computer allowing the configuration of the HRM 300 module. The microcontroller 630 also functions as an interface with a user through the 631 keypad, the ELDs of the 632 state and the LCD 634. A plurality of alarms can be received at the input of the alarm interface 635. The microcontroller 630 monitors the status of the alarm and uses the information for decisions about the control of the HRM 300 module. The microcontroller 630 also can send an alarm signal activated through the output of the alarm interface 635. The video processor 313 of the HRMU 310 contains all the necessary components to insert camera synchronization signals on all cable runs, insert data communication codes for each of the runs separately, multiplex any cable runs for the HRM-VRU 350 or the DC 100 module , and process this video in the meantime. Video processor 313 includes synchronization inserters 641 ah, code inserters 642 ah, multiplexer HRM-VRU 650, video level detector 652, frequency compensator 653, code eliminator 654, code inserter 655, buffer 656 , multiplexer HRM-DC 660, frequency compensator 663, buffer 666 and buffer 676. The synchronization inserters 641 ah of the synchronization signals inserted in parallel on all the cable runs 320, 330 and 340, for use by the cameras 321-322, 331, and 341-343, respectively, on these cable runs. Code inserters 642 a-h insert data communication codes in cable runs 320, 330 and 340, and can apply data communications to each run separately, and two different data packets can be applied to two different cable runs at the same time. This structure allows two cameras in two different cable runs to be addressed (activated) and controlled simultaneously, so that one can be routed to the HRM-VRU 350, and one can be routed to the DC 100 module. cameras 321-322, 331, 341-343 and the HRMU 310 compensate for delays in the video signal that occur as a result of the transmission on the cable runs 320, 330 and 340 in the same manner as described in the co-pending application filed concurrently with the present as proxy file No. 27761-00054, entitled "Phase Compensation for Video Cameras", assigned to the assignee of the present invention, which is hereby incorporated in its entirety as a reference. The multiplexer of the HRM-VRU 650 in the video processor 313 receives the return video from the cable runs 320, 330 and 340. The multiplexer of the HRM-VRU 650 is an 8 x 1 multiplexer that selects which of the lines of cameras is an output of the multiplexer of the HRM-VRU 650 based on an instruction signal sent to the multiplexer of the HRM-VRU 650 from the microcontroller 630 in the synchronizer and control 312, through the clock generator 620 The video streams in the output of the HRM-VRU 650 multiplexer require some processing before these can be sent to the HRM-VRU 350. The change of processing of the video stream by means of the video processor 313 to send it The HRM-VRU 350 is the same as in the video processor 213 of the LMU 210, except that the sync AGC is not required due to the fact that the synchronization signal does not have to travel through any cable length. The video level detector 652 receives the video signals from the multiplexer of the VRU 650 and determines the video losses for each individual camera 331-332, 341, 341-343, comparing a reference signal generated by each camera to a known level. This information is transmitted back to each individual camera by the video level detector 652 where the individual cameras use it to adjust the camera gain. The frequency compensator 653 makes adjustments to the camera gain that are necessary to compensate for the losses resulting from the transmission of the video fields below the long cable runs. Each camera must have a different gain arrangement because each camera will be connected to the video processor 313 by a different cable length. In addition to the data communication codes inserted at the source end of the cable runs 320, 330 and 340 by the code inserters 642 ah of the video processor 313, the return video will contain data communication codes inserted by the individual cameras 321-322, 331 and 341-343. In one embodiment, cameras 321-322, 331 and 343-343 will insert data codes into the video signal, in accordance with the teaching of US Patent Application Serial No. 08 / 501,261, entitled "Video Multiplexer", filed on July 11, 1995, assigned to the same assignee of the present invention, which is hereby incorporated herein by reference in its entirety. The code eliminator 654 removes those individual camera codes from the video and makes them available to the other parts of the video processor 313. The additional data communication codes are inserted into the video by means of the code inserter 655 before these are sent to the HRM-VRU 350. The video of the video processor 315 passes through the buffer 656 before being sent to the HRM-VRU 350. The multiplexer of the HRM-DC 660 also receives return video from the cable runs 320, 330 and 340. The HRM-DC multiplexer is an 8 x 1 multiplexer that selects which of the camera runs 320, 330 or 340 is used as an output from the HRM-DC 660 multiplexer to the DC 100 module with base in a control from the microcontroller 630 in the synchronizer and control 312. The video current in the output of the multiplexer HRM-DC 660 only requires a frequency compensation by the frequency compensator 663 before it is sent to the DC 100 module. The frequency compensator 663 makes adjustments of the camera gain for the frequency losses in the video received from the DC 660 multiplexer for each individual camera. The video coming from the frequency compensator 663 passes through the buffer 666 before being sent to the DC 100 module. The call monitor 360 is supported by the buffer 676 being directly connected to the laying of the camera line 320, 330 or 340 which monitor the call monitor 360. In one embodiment, the call monitor is selectively connected to any of the cable runs 320, 330 and 340 by a multiplexer based on a control from the microcontroller 630 in the synchronizer and control 312. The DC 100 module is responsible for ensuring that the cameras for presentation are activated, and that the signals coming from the presentation camera are routed to the appropriate screen 120 and / or 130. The DC 100 module accomplishes this by sending the modules slaves a camera presentation instruction instructing the slave modules to insert a specific presentation camera into the camera sequence, and routing this field or fields to the appropriate screen 120 and / or 130. The DC 100 module uses four stacks of screens to generate the presentation of the instructions of the cameras [sic]. Each stack of screens is a sequential list of cameras from a slave module that will not be displayed. If the total number of slave modules is greater than four, each stack will have up to two slave modules assigned to it. The presentation camera command is selected by cycling through the four batteries and increasing through the cameras in these batteries. In each field or video phase, a camera is selected from the next stack. The camera selected in each phase is the camera an increment after the last selected camera in the same stack. If one of the presentation batteries does not have a camera, then no presentation will be instructed by the DC 100 module during this phase or specific field. The maximum refresh rate of the presentation camera for any slave module is one in four phases or ~ fields. The control unit (LMU or HRMU) of each slave module is responsible for determining which camera in a corresponding slave module will be activated later. This determination is made using three batteries. The first stack is the stack of the control command that maintains the number of the camera instructed by the DC 100 module, if present, to which the slave module will send images from the DC 100 module for presentation. The second stack is the alarm camera stack that maintains the camera numbers of all cameras that are associated with a specific alarm in an alarm state. The third stack is a stack "all cameras" that keeps the list of all the cameras detected by the slave module. The stack of the control command is a stack of a single camera number, this camera number being the camera code sent to the slave module by the DC 100 module. If a camera number is present in the stack of the control command, the module The slave will retrieve the image for the camera instructed by the DC 100 module before returning it to any other camera. If no display camera is located in the stack of the control command, the slave module will observe if there is a camera number in the alarm camera stack. If there is a camera number in the alarm camera stack, the slave module will alternate between the cameras in the alarm stack and the cameras in the stack all the cameras selected one camera for each stack that is in the camera immediately after the previously selected camera number in the respective stack. If there is no camera number in the alarm camera stack or the alarm command stack, the slave module will cycle through the cameras in the stack all the cameras selected by a camera from the stack of the module camera Let the camera be immediately after the camera number previously selected in the stack all the cameras. Although a preferred embodiment of the method and apparatus of the present invention has been illustrated in the accompanying drawings and described in the above detailed description, it will be understood that the invention is not limited to the described mode, but is capable of numerous rearrangements, modifications and modifications. substitutions without departing from the spirit of the invention as set forth and defined by the following claims.

Claims (1)

1. A system for controlling the multiplexing of video signals, the system consists of: a slave module having a plurality of cameras coupled to a slave control unit for selecting the video signals from one of the plurality of cameras to send them from these; a master control module having a monitor and a master control unit for receiving the video signals from the slave control unit and transmitting the video signals to the monitor and for sending a camera selection signal to the unit slave control, corresponding to one of the plurality of cameras; and wherein the slave control unit selects the video signals from one of the plurality of cameras by sequentially selecting from a list of the plurality of cameras until the master control unit sends the camera selection signal to the camera unit. slave control and upon receiving the selection signal from the camera, the slave control unit selects the video signals coming from the camera corresponding to the camera selection signal.