[go: up one dir, main page]

Benhammadi et al., 2022 - Google Patents

PRECISE: A 5Gbps Serialiser for Scientific Detectors in a 180nm CMOS Image Sensor Process

Benhammadi et al., 2022

View PDF
Document ID
2132965770009633941
Author
Benhammadi S
Guerrini N
Krukauskas D
Mifsud A
Sedgwick I
Publication year
Publication venue
2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

External Links

Snippet

This paper describes a serialiser system tailored for scientific CMOS image sensor applications. The system first structures the data using the Xilinx Aurora 64B/66B protocol, thus enabling rapid system startup, skew compensation without an additional clock output …
Continue reading at epubs.stfc.ac.uk (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits

Similar Documents

Publication Publication Date Title
Takauchi et al. A CMOS multichannel 10-Gb/s transceiver
Kim et al. A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS
Yang et al. A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling
US6888417B2 (en) Voltage controlled oscillator
Cao et al. OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS
US8704567B2 (en) Hybrid phase-locked loop architectures
US20090196312A1 (en) Integrated circuit
CN109314518A (en) High Performance Phase Locked Loop
US20040210790A1 (en) 0.6-2.5 GBaud CMOS tracked 3X oversampling transceiver with dead zone phase detection for robust clock/data recovery
US20140269011A1 (en) Multi-phase ground-referenced single-ended signaling
CN107528585B (en) Phase-locked loop with electrical overload protection circuit
Farjad-Rad et al. A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os
Hafez et al. A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS
Byun et al. A 10-Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector
Moon et al. A 0.6-2.5-GBaud CMOS tracked 3/spl times/oversampling transceiver with dead-zone phase detection for robust clock/data recovery
US7551909B1 (en) CMOS transceiver with dual current path VCO
US20080116949A1 (en) Wideband dual-loop data recovery DLL architecture
Benhammadi et al. PRECISE: A 5Gbps Serialiser for Scientific Detectors in a 180nm CMOS Image Sensor Process
Nedovic et al. A 3 Watt 39.8–44.6 Gb/s dual-mode SFI5. 2 SerDes chip set in 65 nm CMOS
Cervelli et al. A 0.13/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments
Moreira et al. A 1.25 Gbit/s serializer for LHC data and trigger optical links
Kaeriyama et al. A 10Gb/s/ch 50mW 120/spl times/130/spl mu/m/sup 2/clock and data recovery circuit
Chen et al. 6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links
Bae et al. A low-power pulse position modulation transceiver
Lee et al. An on-chip monitoring circuit for signal-integrity analysis of 8-Gb/s chip-to-chip interfaces with source-synchronous clock