Foley et al., 2000 - Google Patents
A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5/spl mu/m CMOSFoley et al., 2000
View PDF- Document ID
- 2077802815921111743
- Author
- Foley D
- Flynn M
- Publication year
- Publication venue
- 2000 IEEE International Symposium on Circuits and Systems (ISCAS)
External Links
Snippet
This paper describes a 1.6 GHz clock synthesizer which employs a delay locked loop (DLL) to generate multiple phases that are combined to produce the desired output clock frequency. A self correcting circuit ensures that the DLL arrives at the correct locked state …
- 238000000034 method 0 abstract description 7
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D13/00—Circuits for comparing the phase or frequency of two mutually-independant oscillations
- H03D13/003—Circuits for comparing the phase or frequency of two mutually-independant oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Johansson | A simple precharged CMOS phase frequency detector | |
| US5977801A (en) | Self-resetting phase/frequency detector with reduced dead zone | |
| US6275555B1 (en) | Digital delay locked loop for adaptive de-skew clock generation | |
| Shin et al. | A 7 ps jitter 0.053 mm $^{2} $ fast lock all-digital DLL with a wide range and high resolution DCC | |
| US5631591A (en) | Method and apparatus for synchronizing timing signals of two integrated circuit chips | |
| US6150889A (en) | Circuit and method for minimizing recovery time | |
| EP1107457A2 (en) | Method of synchronizing a phase-locked loop, phase-locked loop and semiconductor provided with same | |
| US8633749B2 (en) | Phase-locked loop (PLL) fail-over circuit technique and method to mitigate effects of single-event transients | |
| Cheng et al. | A difference detector PFD for low jitter PLL | |
| US20050046486A1 (en) | Lock detectors having a narrow sensitivity range | |
| US6636979B1 (en) | System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays | |
| US6538517B2 (en) | Frequency phase detector for differentiating frequencies having small phase differences | |
| Foley et al. | A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5/spl mu/m CMOS | |
| US6137333A (en) | Optimal delay controller | |
| US7855584B2 (en) | Low lock time delay locked loops using time cycle suppressor | |
| KR100897381B1 (en) | Clock generator independent of input signal duty ratio | |
| US7382163B2 (en) | Phase frequency detector used in digital PLL system | |
| CN100495925C (en) | A Frequency and Phase Detector Circuit Effectively Suppressing Frequency Doubling Mislocking | |
| US7256635B2 (en) | Low lock time delay locked loops using time cycle suppressor | |
| US7233173B1 (en) | System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator | |
| Lee et al. | A 21%-jitter-improved self-aligned dividerless injection-locked PLL with a VCO control voltage ripple-compensated phase detector | |
| US7023944B2 (en) | Method and circuit for glitch-free changing of clocks having different phases | |
| Hsu et al. | A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory | |
| US7480361B1 (en) | Phase lock detector | |
| Shin et al. | A 7ps-jitter 0.053 mm2 fast-lock addll with wide-range and high-resolution all-digital dcc |