[go: up one dir, main page]

Brambilla et al., 2002 - Google Patents

Statistical method for the analysis of interconnects delay in submicrometer layouts

Brambilla et al., 2002

View PDF
Document ID
18323670183949989986
Author
Brambilla A
Maffezzoni P
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

In deep-submicrometer layouts, the determination of the signal delay due to interconnects is a main aspect of the design. Usually, on-chip interconnects are modeled by a distributed resistance-capacitance (RC) line. Key aspects of the interconnect modeling are the …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5018Computer-aided design using simulation using finite difference methods or finite element methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/11Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
    • G06F17/13Differential equations
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30861Retrieval from the Internet, e.g. browsers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/82Noise analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/16Numerical modeling

Similar Documents

Publication Publication Date Title
Brambilla et al. Statistical method for the analysis of interconnects delay in submicrometer layouts
Daniel et al. A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models
US7124069B2 (en) Method and apparatus for simulating physical fields
Niknejad et al. Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits
Ferranti et al. Physics-based passivity-preserving parameterized model order reduction for PEEC circuit analysis
Prasad et al. Multidimensional variability analysis of complex power distribution networks via scalable stochastic collocation approach
US9507906B2 (en) Metal interconnect modeling
Veremey et al. Efficient computation of interconnect capacitances using the domain decomposition approach
Alam et al. Model order reduction using spline-based dynamic multi-point rational interpolation for passive circuits
Yu et al. Capacitance extraction
US7562000B2 (en) Electromagnetic simulator systems and methods
EP1168191B1 (en) A method and apparatus for simulating electromagnetic fields
Hu et al. Fast on-chip inductance simulation using a precorrected-FFT method
Antonini et al. Full-Wave Time Domain PEEC Formulation Using a Modified Nodal Analysis Approach
Daniel et al. Interconnect electromagnetic modeling using conduction modes as global basis functions
Lee et al. Fast structure-aware direct time-domain finite-element solver for the analysis of large-scale on-chip circuits
Braunisch et al. Time-domain simulation of large lossy interconnect systems on conducting substrates
Maheshwari et al. Efficient coupled noise estimation for RLC on-chip interconnect
Chen et al. SuPREME: Substrate and power-delivery reluctance-enhanced macromodel evaluation
Feldmann et al. Efficient techniques for modeling chip-level interconnect, substrate and package parasitics
Avula et al. A novel iterative method for approximating frequency response with equivalent pole/residues
Mondal et al. Fast frequency domain crosstalk analysis for board-level EMC rule checking and optimization
Ruehli Circuit oriented electromagnetic solutions in the time and frequency domain
Kavicharan et al. Efficient delay and crosstalk estimation models for current-mode high speed interconnects under ramp input
Maffezzoni et al. A statistical approach to derive an electrical port model of capacitively coupled interconnects